From a8eb9d521c9f94c19bde099edf678f0fb21f7f85 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 12:58:03 -0500
Subject: [PATCH] ARM: Eliminate the unused rhi and rlo operands.

---
 src/arch/arm/intregs.hh       | 2 --
 src/arch/arm/isa/operands.isa | 2 --
 2 files changed, 4 deletions(-)

diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 15499601a..d13cca6df 100644
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -96,8 +96,6 @@ enum IntRegIndex
 
     INTREG_ZERO, // Dummy zero reg since there has to be one.
     INTREG_UREG0,
-    INTREG_RHI,
-    INTREG_RLO,
     INTREG_CONDCODES,
 
     NUM_INTREGS,
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 2621106ac..d80c0c712 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -109,8 +109,6 @@ def operands {{
     'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
     'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
 
-    'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
-    'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
     'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
     'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),