ruby: slicc: have a static MachineType

This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one.  The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.

The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier.  This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix

src/mem/protocol/MESI_Three_Level-L0cache.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L0Cache, "MESI Directory L0 Cache")
+machine(MachineType:L0Cache, "MESI Directory L0 Cache")
  : Sequencer * sequencer;
    CacheMemory * Icache;
    CacheMemory * Dcache;

src/mem/protocol/MESI_Three_Level-L1cache.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L1Cache, "MESI Directory L1 Cache CMP")
+machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
  : CacheMemory * cache;
    int l2_select_num_bits;
    Cycles l1_request_latency := 2;

src/mem/protocol/MESI_Two_Level-L1cache.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L1Cache, "MESI Directory L1 Cache CMP")
+machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
  : Sequencer * sequencer;
    CacheMemory * L1Icache;
    CacheMemory * L1Dcache;

src/mem/protocol/MESI_Two_Level-L2cache.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L2Cache, "MESI Directory L2 Cache CMP")
+machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")
  : CacheMemory * L2cache;
    Cycles l2_request_latency := 2;
    Cycles l2_response_latency := 2;

src/mem/protocol/MESI_Two_Level-dir.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(Directory, "MESI Two Level directory protocol")
+machine(MachineType:Directory, "MESI Two Level directory protocol")
  : DirectoryMemory * directory;
    Cycles to_mem_ctrl_latency := 1;
    Cycles directory_latency := 6;

src/mem/protocol/MESI_Two_Level-dma.sm

@@ -27,7 +27,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
 : DMASequencer * dma_sequencer;
   Cycles request_latency := 6;
 

src/mem/protocol/MI_example-cache.sm

@@ -27,7 +27,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L1Cache, "MI Example L1 Cache")
+machine(MachineType:L1Cache, "MI Example L1 Cache")
     : Sequencer * sequencer;
       CacheMemory * cacheMemory;
       Cycles cache_response_latency := 12;

src/mem/protocol/MI_example-dir.sm

@@ -27,7 +27,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(Directory, "Directory protocol") 
+machine(MachineType:Directory, "Directory protocol") 
     : DirectoryMemory * directory;
       Cycles directory_latency := 12;
       Cycles to_memory_controller_latency := 1;

src/mem/protocol/MI_example-dma.sm

@@ -27,7 +27,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(DMA, "DMA Controller") 
+machine(MachineType:DMA, "DMA Controller") 
     : DMASequencer * dma_sequencer;
       Cycles request_latency := 6;
 

src/mem/protocol/MOESI_CMP_directory-L1cache.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L1Cache, "Directory protocol")
+machine(MachineType:L1Cache, "Directory protocol")
  : Sequencer * sequencer;
    CacheMemory * L1Icache;
    CacheMemory * L1Dcache;

src/mem/protocol/MOESI_CMP_directory-L2cache.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L2Cache, "Token protocol")
+machine(MachineType:L2Cache, "Token protocol")
 : CacheMemory * L2cache;
   Cycles response_latency := 2;
   Cycles request_latency := 2;

src/mem/protocol/MOESI_CMP_directory-dir.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(Directory, "Directory protocol")
+machine(MachineType:Directory, "Directory protocol")
 :  DirectoryMemory * directory;
    Cycles directory_latency := 6;
    Cycles to_memory_controller_latency := 1;

src/mem/protocol/MOESI_CMP_directory-dma.sm

@@ -27,7 +27,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
     : DMASequencer * dma_sequencer;
       Cycles request_latency := 14;
       Cycles response_latency := 14;

src/mem/protocol/MOESI_CMP_token-L1cache.sm

@@ -31,7 +31,7 @@
  *
  */
 
-machine(L1Cache, "Token protocol")
+machine(MachineType:L1Cache, "Token protocol")
  : Sequencer * sequencer;
    CacheMemory * L1Icache;
    CacheMemory * L1Dcache;

src/mem/protocol/MOESI_CMP_token-L2cache.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(L2Cache, "Token protocol")
+machine(MachineType:L2Cache, "Token protocol")
  : CacheMemory * L2cache;
    int N_tokens;
    Cycles l2_request_latency := 5;

src/mem/protocol/MOESI_CMP_token-dir.sm

@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-machine(Directory, "Token protocol")
+machine(MachineType:Directory, "Token protocol")
  : DirectoryMemory * directory;
    int l2_select_num_bits;
    Cycles directory_latency := 5;

src/mem/protocol/MOESI_CMP_token-dma.sm

@@ -27,7 +27,7 @@
  */
 
 
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
     : DMASequencer * dma_sequencer;
       Cycles request_latency := 6;
 

src/mem/protocol/MOESI_hammer-cache.sm

@@ -33,7 +33,7 @@
  *          Brad Beckmann
  */
 
-machine(L1Cache, "AMD Hammer-like protocol")
+machine(MachineType:L1Cache, "AMD Hammer-like protocol")
     : Sequencer * sequencer;
       CacheMemory * L1Icache;
       CacheMemory * L1Dcache;

src/mem/protocol/MOESI_hammer-dir.sm

@@ -33,7 +33,7 @@
  *          Brad Beckmann
  */
 
-machine(Directory, "AMD Hammer-like protocol") 
+machine(MachineType:Directory, "AMD Hammer-like protocol") 
     : DirectoryMemory * directory;
       CacheMemory * probeFilter;
       Cycles from_memory_controller_latency := 2;

src/mem/protocol/MOESI_hammer-dma.sm

@@ -27,7 +27,7 @@
  */
 
 
-machine(DMA, "DMA Controller") 
+machine(MachineType:DMA, "DMA Controller") 
     : DMASequencer * dma_sequencer;
       Cycles request_latency := 6;
 

src/mem/protocol/Network_test-cache.sm

@@ -31,7 +31,7 @@
  */
 
 
-machine(L1Cache, "Network_test L1 Cache")
+machine(MachineType:L1Cache, "Network_test L1 Cache")
     : Sequencer * sequencer;
       Cycles issue_latency := 2;
 

src/mem/protocol/Network_test-dir.sm

@@ -31,7 +31,7 @@
  */
 
 
-machine(Directory, "Network_test Directory")
+machine(MachineType:Directory, "Network_test Directory")
     : MessageBuffer * requestToDir, network="From", virtual_network="0",
             vnet_type = "request";
       MessageBuffer * forwardToDir, network="From", virtual_network="1",

src/mem/protocol/RubySlicc_Exports.sm

@@ -173,6 +173,24 @@ enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestT
   Default,    desc="Replace this with access_types passed to the DMA Ruby object";
 }
 
+
+// These are statically defined types of states machines that we can have.
+// If you want to add a new machine type, edit this enum.  It is not necessary
+// for a protocol to have state machines defined for the all types here.  But
+// you cannot use anything other than the ones defined here.  Also, a protocol
+// can have only one state machine for a given type.
+enumeration(MachineType, desc="...", default="MachineType_NULL") {
+    L1Cache,     desc="L1 Cache Mach";
+    L2Cache,     desc="L2 Cache Mach";
+    L3Cache,     desc="L3 Cache Mach";
+    Directory,   desc="Directory Mach";
+    DMA,         desc="DMA Mach";
+    Collector,   desc="Collector Mach";
+    L1Cache_wCC, desc="L1 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
+    L2Cache_wCC, desc="L2 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
+    NULL,        desc="null mach type";
+}
+
 // MessageSizeType
 enumeration(MessageSizeType, desc="...") {
   Control,    desc="Control Message";

src/mem/slicc/ast/DeclListAST.py

@@ -45,9 +45,6 @@ class DeclListAST(AST):
         return s
 
     def generate(self):
-        for decl in self.decls:
-            decl.generate()
-
-    def findMachines(self):
         for decl in self.decls:
             decl.findMachines()
+            decl.generate()

src/mem/slicc/ast/MachineAST.py

@@ -29,10 +29,10 @@ from slicc.ast.DeclAST import DeclAST
 from slicc.symbols import StateMachine, Type
 
 class MachineAST(DeclAST):
-    def __init__(self, slicc, ident, pairs_ast, config_parameters, decls):
+    def __init__(self, slicc, mtype, pairs_ast, config_parameters, decls):
         super(MachineAST, self).__init__(slicc, pairs_ast)
 
-        self.ident = ident
+        self.ident = mtype.value
         self.pairs_ast = pairs_ast
         self.config_parameters = config_parameters
         self.decls = decls
@@ -72,11 +72,5 @@ class MachineAST(DeclAST):
     def findMachines(self):
         mtype = self.ident
         machine_type = self.symtab.find("MachineType", Type)
-        pairs = self.pairs_ast.pairs
+        if not machine_type.checkEnum(mtype):
-
-        pairs["Primary"] = True
-        if not machine_type.addEnum(mtype, pairs):
             self.error("Duplicate machine name: %s:%s" % (machine_type, mtype))
-
-        # Generate code for all the internal decls
-        self.decls.findMachines()

src/mem/slicc/parser.py

@@ -62,7 +62,6 @@ class SLICC(Grammar):
         return code
 
     def process(self):
-        self.decl_list.findMachines()
         self.decl_list.generate()
 
     def writeCodeFiles(self, code_path, includes):
@@ -72,10 +71,7 @@ class SLICC(Grammar):
         self.symtab.writeHTMLFiles(html_path)
 
     def files(self):
-        f = set([
+        f = set(['Types.hh'])
-            'MachineType.cc',
-            'MachineType.hh',
-            'Types.hh' ])
 
         f |= self.decl_list.files()
 
@@ -259,11 +255,11 @@ class SLICC(Grammar):
         p[0] = self.parse_file(filename)
 
     def p_decl__machine0(self, p):
-        "decl : MACHINE '(' ident ')' ':' obj_decls '{' decls '}'"
+        "decl : MACHINE '(' enumeration ')' ':' obj_decls '{' decls '}'"
         p[0] = ast.MachineAST(self, p[3], [], p[7], p[9])
 
     def p_decl__machine1(self, p):
-        "decl : MACHINE '(' ident pairs ')' ':' obj_decls '{' decls '}'"
+        "decl : MACHINE '(' enumeration pairs ')' ':' obj_decls '{' decls '}'"
         p[0] = ast.MachineAST(self, p[3], p[4], p[7], p[9])
 
     def p_decl__action(self, p):

src/mem/slicc/symbols/SymbolTable.py

@@ -40,12 +40,6 @@ class SymbolTable(object):
         self.sym_map_vec = [ {} ]
         self.machine_components = {}
 
-        pairs = {}
-        pairs["enumeration"] = "yes"
-        location = Location("init", 0, no_warning=not slicc.verbose)
-        MachineType = Type(self, "MachineType", location, pairs)
-        self.newSymbol(MachineType)
-
         pairs = {}
         pairs["primitive"] = "yes"
         pairs["external"] = "yes"

src/mem/slicc/symbols/Type.py

@@ -42,6 +42,7 @@ class Enumeration(PairContainer):
     def __init__(self, ident, pairs):
         super(Enumeration, self).__init__(pairs)
         self.ident = ident
+        self.primary = False
 
 class Type(Symbol):
     def __init__(self, table, ident, location, pairs, machine=None):
@@ -165,6 +166,14 @@ class Type(Symbol):
 
         return True
 
+    ## Used to check if an enum has been already used and therefore
+    ## should not be used again.
+    def checkEnum(self, ident):
+        if ident in self.enums and not self.enums[ident].primary:
+            self.enums[ident].primary = True
+            return True
+        return False
+
     def writeCodeFiles(self, path, includes):
         if self.isExternal:
             # Do nothing
@@ -567,7 +576,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
 
         if self.isMachineType:
             for enum in self.enums.itervalues():
-                if enum.get("Primary"):
+                if enum.primary:
                     code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
             code('#include "mem/ruby/common/MachineID.hh"')
 
@@ -706,7 +715,7 @@ ${{self.c_ident}}_base_number(const ${{self.c_ident}}& obj)
             code('  case ${{self.c_ident}}_NUM:')
             for enum in reversed(self.enums.values()):
                 # Check if there is a defined machine with this type
-                if enum.get("Primary"):
+                if enum.primary:
                     code('    base += ${{enum.ident}}_Controller::getNumControllers();')
                 else:
                     code('    base += 0;')
@@ -734,7 +743,7 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj)
             # For each field
             for enum in self.enums.itervalues():
                 code('case ${{self.c_ident}}_${{enum.ident}}:')
-                if enum.get("Primary"):
+                if enum.primary:
                     code('return ${{enum.ident}}_Controller::getNumControllers();')
                 else:
                     code('return 0;')