From a3177645773b8eb4b835050c395554d3e2b4664a Mon Sep 17 00:00:00 2001 From: Tony Gutierrez Date: Mon, 20 Jul 2015 09:15:18 -0500 Subject: [PATCH] ruby: slicc: have a static MachineType This patch is imported from reviewboard patch 2551 by Nilay. This patch moves from a dynamically defined MachineType to a statically defined one. The need for this patch was felt since a dynamically defined type prevents us from having types for which no machine definition may exist. The following changes have been made: i. each machine definition now uses a type from the MachineType enumeration instead of any random identifier. This required changing the grammar and the *.sm files. ii. MachineType enumeration defined statically in RubySlicc_Exports.sm. * * * normal protocol fixes for nilay's parser machine type fix --- src/mem/protocol/MESI_Three_Level-L0cache.sm | 2 +- src/mem/protocol/MESI_Three_Level-L1cache.sm | 2 +- src/mem/protocol/MESI_Two_Level-L1cache.sm | 2 +- src/mem/protocol/MESI_Two_Level-L2cache.sm | 2 +- src/mem/protocol/MESI_Two_Level-dir.sm | 2 +- src/mem/protocol/MESI_Two_Level-dma.sm | 2 +- src/mem/protocol/MI_example-cache.sm | 2 +- src/mem/protocol/MI_example-dir.sm | 2 +- src/mem/protocol/MI_example-dma.sm | 2 +- .../protocol/MOESI_CMP_directory-L1cache.sm | 2 +- .../protocol/MOESI_CMP_directory-L2cache.sm | 2 +- src/mem/protocol/MOESI_CMP_directory-dir.sm | 2 +- src/mem/protocol/MOESI_CMP_directory-dma.sm | 2 +- src/mem/protocol/MOESI_CMP_token-L1cache.sm | 2 +- src/mem/protocol/MOESI_CMP_token-L2cache.sm | 2 +- src/mem/protocol/MOESI_CMP_token-dir.sm | 2 +- src/mem/protocol/MOESI_CMP_token-dma.sm | 2 +- src/mem/protocol/MOESI_hammer-cache.sm | 2 +- src/mem/protocol/MOESI_hammer-dir.sm | 2 +- src/mem/protocol/MOESI_hammer-dma.sm | 2 +- src/mem/protocol/Network_test-cache.sm | 2 +- src/mem/protocol/Network_test-dir.sm | 2 +- src/mem/protocol/RubySlicc_Exports.sm | 18 ++++++++++++++++++ src/mem/slicc/ast/DeclListAST.py | 5 +---- src/mem/slicc/ast/MachineAST.py | 12 +++--------- src/mem/slicc/parser.py | 10 +++------- src/mem/slicc/symbols/SymbolTable.py | 6 ------ src/mem/slicc/symbols/Type.py | 15 ++++++++++++--- 28 files changed, 59 insertions(+), 51 deletions(-) diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm index 30105727c..4950d63b2 100644 --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L0Cache, "MESI Directory L0 Cache") +machine(MachineType:L0Cache, "MESI Directory L0 Cache") : Sequencer * sequencer; CacheMemory * Icache; CacheMemory * Dcache; diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm index c6b4cda64..e960486a7 100644 --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L1Cache, "MESI Directory L1 Cache CMP") +machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") : CacheMemory * cache; int l2_select_num_bits; Cycles l1_request_latency := 2; diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index b8a4c6220..2242250ad 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L1Cache, "MESI Directory L1 Cache CMP") +machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") : Sequencer * sequencer; CacheMemory * L1Icache; CacheMemory * L1Dcache; diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index 0fd9028c6..d7a88c199 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L2Cache, "MESI Directory L2 Cache CMP") +machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP") : CacheMemory * L2cache; Cycles l2_request_latency := 2; Cycles l2_response_latency := 2; diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm index c9fbe3875..440114a79 100644 --- a/src/mem/protocol/MESI_Two_Level-dir.sm +++ b/src/mem/protocol/MESI_Two_Level-dir.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(Directory, "MESI Two Level directory protocol") +machine(MachineType:Directory, "MESI Two Level directory protocol") : DirectoryMemory * directory; Cycles to_mem_ctrl_latency := 1; Cycles directory_latency := 6; diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm index 84774ede8..68cb7e968 100644 --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -27,7 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(DMA, "DMA Controller") +machine(MachineType:DMA, "DMA Controller") : DMASequencer * dma_sequencer; Cycles request_latency := 6; diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 1a83704e2..0e3e6e1eb 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -27,7 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L1Cache, "MI Example L1 Cache") +machine(MachineType:L1Cache, "MI Example L1 Cache") : Sequencer * sequencer; CacheMemory * cacheMemory; Cycles cache_response_latency := 12; diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index f12e474b0..e2d834201 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -27,7 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(Directory, "Directory protocol") +machine(MachineType:Directory, "Directory protocol") : DirectoryMemory * directory; Cycles directory_latency := 12; Cycles to_memory_controller_latency := 1; diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index 76d87516a..6032229ee 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -27,7 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(DMA, "DMA Controller") +machine(MachineType:DMA, "DMA Controller") : DMASequencer * dma_sequencer; Cycles request_latency := 6; diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 1327471fc..0d48e2195 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L1Cache, "Directory protocol") +machine(MachineType:L1Cache, "Directory protocol") : Sequencer * sequencer; CacheMemory * L1Icache; CacheMemory * L1Dcache; diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index 07cfe18d3..4db262cb0 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L2Cache, "Token protocol") +machine(MachineType:L2Cache, "Token protocol") : CacheMemory * L2cache; Cycles response_latency := 2; Cycles request_latency := 2; diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index 7175edc8d..9b73a2bb2 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(Directory, "Directory protocol") +machine(MachineType:Directory, "Directory protocol") : DirectoryMemory * directory; Cycles directory_latency := 6; Cycles to_memory_controller_latency := 1; diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index 72dec6466..5eb2f2587 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -27,7 +27,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(DMA, "DMA Controller") +machine(MachineType:DMA, "DMA Controller") : DMASequencer * dma_sequencer; Cycles request_latency := 14; Cycles response_latency := 14; diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index b8c2da761..7961aa3be 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -31,7 +31,7 @@ * */ -machine(L1Cache, "Token protocol") +machine(MachineType:L1Cache, "Token protocol") : Sequencer * sequencer; CacheMemory * L1Icache; CacheMemory * L1Dcache; diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index 2ab593394..c9995011d 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(L2Cache, "Token protocol") +machine(MachineType:L2Cache, "Token protocol") : CacheMemory * L2cache; int N_tokens; Cycles l2_request_latency := 5; diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm index 63790531f..c3a585b96 100644 --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(Directory, "Token protocol") +machine(MachineType:Directory, "Token protocol") : DirectoryMemory * directory; int l2_select_num_bits; Cycles directory_latency := 5; diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm index efe3db3cd..3b144771d 100644 --- a/src/mem/protocol/MOESI_CMP_token-dma.sm +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm @@ -27,7 +27,7 @@ */ -machine(DMA, "DMA Controller") +machine(MachineType:DMA, "DMA Controller") : DMASequencer * dma_sequencer; Cycles request_latency := 6; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index d4e7d7e3c..9b2e4cab3 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -33,7 +33,7 @@ * Brad Beckmann */ -machine(L1Cache, "AMD Hammer-like protocol") +machine(MachineType:L1Cache, "AMD Hammer-like protocol") : Sequencer * sequencer; CacheMemory * L1Icache; CacheMemory * L1Dcache; diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index 4f5b00658..42522c727 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -33,7 +33,7 @@ * Brad Beckmann */ -machine(Directory, "AMD Hammer-like protocol") +machine(MachineType:Directory, "AMD Hammer-like protocol") : DirectoryMemory * directory; CacheMemory * probeFilter; Cycles from_memory_controller_latency := 2; diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm index 7157082c4..3592e9991 100644 --- a/src/mem/protocol/MOESI_hammer-dma.sm +++ b/src/mem/protocol/MOESI_hammer-dma.sm @@ -27,7 +27,7 @@ */ -machine(DMA, "DMA Controller") +machine(MachineType:DMA, "DMA Controller") : DMASequencer * dma_sequencer; Cycles request_latency := 6; diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm index dab8f1089..39ec3b986 100644 --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -31,7 +31,7 @@ */ -machine(L1Cache, "Network_test L1 Cache") +machine(MachineType:L1Cache, "Network_test L1 Cache") : Sequencer * sequencer; Cycles issue_latency := 2; diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm index 6bd6920b3..f7feea4d5 100644 --- a/src/mem/protocol/Network_test-dir.sm +++ b/src/mem/protocol/Network_test-dir.sm @@ -31,7 +31,7 @@ */ -machine(Directory, "Network_test Directory") +machine(MachineType:Directory, "Network_test Directory") : MessageBuffer * requestToDir, network="From", virtual_network="0", vnet_type = "request"; MessageBuffer * forwardToDir, network="From", virtual_network="1", diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 7c2069203..617989d15 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -173,6 +173,24 @@ enumeration(MemoryControlRequestType, desc="...", default="MemoryControlRequestT Default, desc="Replace this with access_types passed to the DMA Ruby object"; } + +// These are statically defined types of states machines that we can have. +// If you want to add a new machine type, edit this enum. It is not necessary +// for a protocol to have state machines defined for the all types here. But +// you cannot use anything other than the ones defined here. Also, a protocol +// can have only one state machine for a given type. +enumeration(MachineType, desc="...", default="MachineType_NULL") { + L1Cache, desc="L1 Cache Mach"; + L2Cache, desc="L2 Cache Mach"; + L3Cache, desc="L3 Cache Mach"; + Directory, desc="Directory Mach"; + DMA, desc="DMA Mach"; + Collector, desc="Collector Mach"; + L1Cache_wCC, desc="L1 Cache Mach to track cache-to-cache transfer (used for miss latency profile)"; + L2Cache_wCC, desc="L2 Cache Mach to track cache-to-cache transfer (used for miss latency profile)"; + NULL, desc="null mach type"; +} + // MessageSizeType enumeration(MessageSizeType, desc="...") { Control, desc="Control Message"; diff --git a/src/mem/slicc/ast/DeclListAST.py b/src/mem/slicc/ast/DeclListAST.py index 36c520070..4ba41ed6c 100644 --- a/src/mem/slicc/ast/DeclListAST.py +++ b/src/mem/slicc/ast/DeclListAST.py @@ -45,9 +45,6 @@ class DeclListAST(AST): return s def generate(self): - for decl in self.decls: - decl.generate() - - def findMachines(self): for decl in self.decls: decl.findMachines() + decl.generate() diff --git a/src/mem/slicc/ast/MachineAST.py b/src/mem/slicc/ast/MachineAST.py index 4487b094e..c67d0e695 100644 --- a/src/mem/slicc/ast/MachineAST.py +++ b/src/mem/slicc/ast/MachineAST.py @@ -29,10 +29,10 @@ from slicc.ast.DeclAST import DeclAST from slicc.symbols import StateMachine, Type class MachineAST(DeclAST): - def __init__(self, slicc, ident, pairs_ast, config_parameters, decls): + def __init__(self, slicc, mtype, pairs_ast, config_parameters, decls): super(MachineAST, self).__init__(slicc, pairs_ast) - self.ident = ident + self.ident = mtype.value self.pairs_ast = pairs_ast self.config_parameters = config_parameters self.decls = decls @@ -72,11 +72,5 @@ class MachineAST(DeclAST): def findMachines(self): mtype = self.ident machine_type = self.symtab.find("MachineType", Type) - pairs = self.pairs_ast.pairs - - pairs["Primary"] = True - if not machine_type.addEnum(mtype, pairs): + if not machine_type.checkEnum(mtype): self.error("Duplicate machine name: %s:%s" % (machine_type, mtype)) - - # Generate code for all the internal decls - self.decls.findMachines() diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py index 364bb92f7..4afe0d367 100644 --- a/src/mem/slicc/parser.py +++ b/src/mem/slicc/parser.py @@ -62,7 +62,6 @@ class SLICC(Grammar): return code def process(self): - self.decl_list.findMachines() self.decl_list.generate() def writeCodeFiles(self, code_path, includes): @@ -72,10 +71,7 @@ class SLICC(Grammar): self.symtab.writeHTMLFiles(html_path) def files(self): - f = set([ - 'MachineType.cc', - 'MachineType.hh', - 'Types.hh' ]) + f = set(['Types.hh']) f |= self.decl_list.files() @@ -259,11 +255,11 @@ class SLICC(Grammar): p[0] = self.parse_file(filename) def p_decl__machine0(self, p): - "decl : MACHINE '(' ident ')' ':' obj_decls '{' decls '}'" + "decl : MACHINE '(' enumeration ')' ':' obj_decls '{' decls '}'" p[0] = ast.MachineAST(self, p[3], [], p[7], p[9]) def p_decl__machine1(self, p): - "decl : MACHINE '(' ident pairs ')' ':' obj_decls '{' decls '}'" + "decl : MACHINE '(' enumeration pairs ')' ':' obj_decls '{' decls '}'" p[0] = ast.MachineAST(self, p[3], p[4], p[7], p[9]) def p_decl__action(self, p): diff --git a/src/mem/slicc/symbols/SymbolTable.py b/src/mem/slicc/symbols/SymbolTable.py index 844e4c63f..e991fec2b 100644 --- a/src/mem/slicc/symbols/SymbolTable.py +++ b/src/mem/slicc/symbols/SymbolTable.py @@ -40,12 +40,6 @@ class SymbolTable(object): self.sym_map_vec = [ {} ] self.machine_components = {} - pairs = {} - pairs["enumeration"] = "yes" - location = Location("init", 0, no_warning=not slicc.verbose) - MachineType = Type(self, "MachineType", location, pairs) - self.newSymbol(MachineType) - pairs = {} pairs["primitive"] = "yes" pairs["external"] = "yes" diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index a3223b3ac..bd92e20c9 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -42,6 +42,7 @@ class Enumeration(PairContainer): def __init__(self, ident, pairs): super(Enumeration, self).__init__(pairs) self.ident = ident + self.primary = False class Type(Symbol): def __init__(self, table, ident, location, pairs, machine=None): @@ -165,6 +166,14 @@ class Type(Symbol): return True + ## Used to check if an enum has been already used and therefore + ## should not be used again. + def checkEnum(self, ident): + if ident in self.enums and not self.enums[ident].primary: + self.enums[ident].primary = True + return True + return False + def writeCodeFiles(self, path, includes): if self.isExternal: # Do nothing @@ -567,7 +576,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj) if self.isMachineType: for enum in self.enums.itervalues(): - if enum.get("Primary"): + if enum.primary: code('#include "mem/protocol/${{enum.ident}}_Controller.hh"') code('#include "mem/ruby/common/MachineID.hh"') @@ -706,7 +715,7 @@ ${{self.c_ident}}_base_number(const ${{self.c_ident}}& obj) code(' case ${{self.c_ident}}_NUM:') for enum in reversed(self.enums.values()): # Check if there is a defined machine with this type - if enum.get("Primary"): + if enum.primary: code(' base += ${{enum.ident}}_Controller::getNumControllers();') else: code(' base += 0;') @@ -734,7 +743,7 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj) # For each field for enum in self.enums.itervalues(): code('case ${{self.c_ident}}_${{enum.ident}}:') - if enum.get("Primary"): + if enum.primary: code('return ${{enum.ident}}_Controller::getNumControllers();') else: code('return 0;')