sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

ARM: Handle accesses to the DACR.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:13 -05:00
parent 951b7edaba
commit 9fb573d91e
1 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/arch/arm/miscregs.hh
View file

@ -108,6 +108,7 @@ namespace ArmISA
MISCREG_MIDR, MISCREG_MIDR,
MISCREG_TTBR0, MISCREG_TTBR0,
MISCREG_TTBR1, MISCREG_TTBR1,
MISCREG_DACR,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TLBTR, MISCREG_TLBTR,
@ -130,7 +131,6 @@ namespace ArmISA
MISCREG_PAR, MISCREG_PAR,
MISCREG_AIDR, MISCREG_AIDR,
MISCREG_ACTLR, MISCREG_ACTLR,
MISCREG_DACR,
MISCREG_DFSR, MISCREG_DFSR,
MISCREG_IFSR, MISCREG_IFSR,
MISCREG_ADFSR, MISCREG_ADFSR,
@ -198,11 +198,11 @@ namespace ArmISA
"clidr", "ccsidr", "csselr", "clidr", "ccsidr", "csselr",
"icialluis", "iciallu", "icimvau", "icialluis", "iciallu", "icimvau",
"bpimva", "bpiallis", "bpiall", "bpimva", "bpiallis", "bpiall",
"midr", "ttbr0", "ttbr1", "ctr", "tlbtr", "tcmtr", "mpidr", "midr", "ttbr0", "ttbr1", "dacr", "ctr", "tlbtr", "tcmtr", "mpidr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"par", "aidr", "actlr", "dacr", "par", "aidr", "actlr",
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"dcimvac", "dcisw", "mccsw", "dcimvac", "dcisw", "mccsw",
"dccmvau", "dccmvau",