ARM: Track the current ISA mode using the PC.
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6 changed files with 121 additions and 19 deletions
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@ -1,4 +1,16 @@
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/*
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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* All rights reserved.
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@ -95,8 +107,7 @@ ArmFaultBase::invoke(ThreadContext *tc)
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cpsr.it1 = cpsr.it2 = 0;
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cpsr.it1 = cpsr.it2 = 0;
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cpsr.j = 0;
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cpsr.j = 0;
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if (sctlr.te)
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cpsr.t = sctlr.te;
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cpsr.t = 1;
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cpsr.a = cpsr.a | abortDisable();
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cpsr.a = cpsr.a | abortDisable();
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cpsr.f = cpsr.f | fiqDisable();
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cpsr.f = cpsr.f | fiqDisable();
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cpsr.i = 1;
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cpsr.i = 1;
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@ -124,10 +135,12 @@ ArmFaultBase::invoke(ThreadContext *tc)
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panic("unknown Mode\n");
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panic("unknown Mode\n");
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}
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}
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DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", name(), cpsr,
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Addr pc = tc->readPC();
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tc->readPC(), tc->readIntReg(INTREG_LR));
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DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
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tc->setPC(getVector(tc));
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name(), cpsr, pc, tc->readIntReg(INTREG_LR));
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tc->setNextPC(getVector(tc) + cpsr.t ? 2 : 4 );
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Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
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tc->setPC(newPc);
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tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
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}
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}
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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@ -1,4 +1,17 @@
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/* Copyright (c) 2007-2008 The Florida State University
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -124,6 +137,14 @@ class ArmStaticInst : public StaticInst
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return ((spsr & ~bitMask) | (val & bitMask));
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return ((spsr & ~bitMask) | (val & bitMask));
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}
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}
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template<class XC>
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static void
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setNextPC(XC *xc, Addr val)
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{
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xc->setNextPC((xc->readNextPC() & PcModeMask) |
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(val & ~PcModeMask));
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}
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};
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};
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}
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}
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@ -1,4 +1,16 @@
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/*
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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* All rights reserved.
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*
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*
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@ -127,6 +139,19 @@ namespace ArmISA
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MiscReg
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MiscReg
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readMiscReg(int misc_reg, ThreadContext *tc)
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readMiscReg(int misc_reg, ThreadContext *tc)
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{
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{
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if (misc_reg == MISCREG_CPSR) {
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CPSR cpsr = miscRegs[misc_reg];
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Addr pc = tc->readPC();
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if (pc & (ULL(1) << PcJBitShift))
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cpsr.j = 1;
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else
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cpsr.j = 0;
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if (pc & (ULL(1) << PcTBitShift))
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cpsr.t = 1;
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else
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cpsr.t = 0;
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return cpsr;
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}
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return readMiscRegNoEffect(misc_reg);
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return readMiscRegNoEffect(misc_reg);
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}
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}
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@ -171,6 +196,14 @@ namespace ArmISA
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{
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{
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if (misc_reg == MISCREG_CPSR) {
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if (misc_reg == MISCREG_CPSR) {
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updateRegMap(val);
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updateRegMap(val);
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CPSR cpsr = val;
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Addr npc = tc->readNextPC() & ~PcModeMask;
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if (cpsr.j)
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npc = npc | (ULL(1) << PcJBitShift);
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if (cpsr.t)
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npc = npc | (ULL(1) << PcTBitShift);
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tc->setNextPC(npc);
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}
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}
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return setMiscRegNoEffect(misc_reg, val);
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return setMiscRegNoEffect(misc_reg, val);
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}
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}
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@ -53,13 +53,16 @@ def operand_types {{
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let {{
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let {{
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maybePCRead = '''
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maybePCRead = '''
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((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) :
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((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
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xc->%(func)s(this, %(op_idx)s))
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xc->%(func)s(this, %(op_idx)s))
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'''
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'''
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maybePCWrite = '''
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maybePCWrite = '''
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((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) :
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((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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xc->%(func)s(this, %(op_idx)s, %(final_val)s))
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'''
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'''
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readNPC = 'xc->readNextPC() & ~PcModeMask'
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writeNPC = 'setNextPC(xc, %(final_val)s)'
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}};
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}};
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def operands {{
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def operands {{
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@ -92,13 +95,12 @@ def operands {{
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#Memory Operand
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#Memory Operand
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
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'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', None, 40),
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'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
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'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
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'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
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'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
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'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
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'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
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'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
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'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
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'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
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'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
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'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
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'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50),
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'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 50,
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'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51)
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readNPC, writeNPC),
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}};
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}};
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@ -1,4 +1,16 @@
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/*
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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* All rights reserved.
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*
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*
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@ -97,6 +109,13 @@ namespace ArmISA
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// integer register to allow renaming.
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// integer register to allow renaming.
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static const uint32_t CondCodesMask = 0xF80F0000;
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static const uint32_t CondCodesMask = 0xF80F0000;
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// These otherwise unused bits of the PC are used to select a mode
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// like the J and T bits of the CPSR.
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static const Addr PcJBitShift = 33;
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static const Addr PcTBitShift = 34;
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static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
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(ULL(1) << PcTBitShift);
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BitUnion32(SCTLR)
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BitUnion32(SCTLR)
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Bitfield<30> te; // Thumb Exception Enable
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Bitfield<30> te; // Thumb Exception Enable
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Bitfield<29> afe; // Access flag enable
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Bitfield<29> afe; // Access flag enable
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@ -1,4 +1,16 @@
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/*
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2007-2008 The Florida State University
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@ -278,18 +290,20 @@ TLB::regStats()
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Fault
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Fault
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TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
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TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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{
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Addr vaddr = req->getVaddr() & ~PcModeMask;
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#if !FULL_SYSTEM
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#if !FULL_SYSTEM
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Process * p = tc->getProcessPtr();
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Process * p = tc->getProcessPtr();
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Fault fault = p->pTable->translate(req);
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Addr paddr;
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if(fault != NoFault)
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if (!p->pTable->translate(vaddr, paddr))
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return fault;
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return Fault(new GenericPageTableFault(vaddr));
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req->setPaddr(paddr);
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return NoFault;
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return NoFault;
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#else
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#else
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
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if (!sctlr.m) {
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if (!sctlr.m) {
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req->setPaddr(req->getVaddr());
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req->setPaddr(vaddr);
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return NoFault;
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return NoFault;
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}
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}
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panic("MMU translation not implemented\n");
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panic("MMU translation not implemented\n");
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