From 9ef82c0bc437a962398857dcb365a8493a9ac5c7 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 2 Jun 2010 12:57:59 -0500 Subject: [PATCH] ARM: Track the current ISA mode using the PC. --- src/arch/arm/faults.cc | 29 +++++++++++++++++++-------- src/arch/arm/insts/static_inst.hh | 23 ++++++++++++++++++++- src/arch/arm/isa.hh | 33 +++++++++++++++++++++++++++++++ src/arch/arm/isa/operands.isa | 14 +++++++------ src/arch/arm/miscregs.hh | 19 ++++++++++++++++++ src/arch/arm/tlb.cc | 22 +++++++++++++++++---- 6 files changed, 121 insertions(+), 19 deletions(-) diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index b7dd2d503..2f939ea8c 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2003-2005 The Regents of The University of Michigan * Copyright (c) 2007-2008 The Florida State University * All rights reserved. @@ -95,8 +107,7 @@ ArmFaultBase::invoke(ThreadContext *tc) cpsr.it1 = cpsr.it2 = 0; cpsr.j = 0; - if (sctlr.te) - cpsr.t = 1; + cpsr.t = sctlr.te; cpsr.a = cpsr.a | abortDisable(); cpsr.f = cpsr.f | fiqDisable(); cpsr.i = 1; @@ -122,12 +133,14 @@ ArmFaultBase::invoke(ThreadContext *tc) break; default: panic("unknown Mode\n"); - } - - DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", name(), cpsr, - tc->readPC(), tc->readIntReg(INTREG_LR)); - tc->setPC(getVector(tc)); - tc->setNextPC(getVector(tc) + cpsr.t ? 2 : 4 ); + } + + Addr pc = tc->readPC(); + DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", + name(), cpsr, pc, tc->readIntReg(INTREG_LR)); + Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0); + tc->setPC(newPc); + tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); } #endif // FULL_SYSTEM diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index f2881c3b6..7a87fce2b 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -1,4 +1,17 @@ -/* Copyright (c) 2007-2008 The Florida State University +/* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2007-2008 The Florida State University * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -124,6 +137,14 @@ class ArmStaticInst : public StaticInst return ((spsr & ~bitMask) | (val & bitMask)); } + + template + static void + setNextPC(XC *xc, Addr val) + { + xc->setNextPC((xc->readNextPC() & PcModeMask) | + (val & ~PcModeMask)); + } }; } diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 905eb0183..c64f7bef9 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * @@ -127,6 +139,19 @@ namespace ArmISA MiscReg readMiscReg(int misc_reg, ThreadContext *tc) { + if (misc_reg == MISCREG_CPSR) { + CPSR cpsr = miscRegs[misc_reg]; + Addr pc = tc->readPC(); + if (pc & (ULL(1) << PcJBitShift)) + cpsr.j = 1; + else + cpsr.j = 0; + if (pc & (ULL(1) << PcTBitShift)) + cpsr.t = 1; + else + cpsr.t = 0; + return cpsr; + } return readMiscRegNoEffect(misc_reg); } @@ -171,6 +196,14 @@ namespace ArmISA { if (misc_reg == MISCREG_CPSR) { updateRegMap(val); + CPSR cpsr = val; + Addr npc = tc->readNextPC() & ~PcModeMask; + if (cpsr.j) + npc = npc | (ULL(1) << PcJBitShift); + if (cpsr.t) + npc = npc | (ULL(1) << PcTBitShift); + + tc->setNextPC(npc); } return setMiscRegNoEffect(misc_reg, val); } diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index a476590a0..a27f61228 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -53,13 +53,16 @@ def operand_types {{ let {{ maybePCRead = ''' - ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) : + ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) : xc->%(func)s(this, %(op_idx)s)) ''' maybePCWrite = ''' - ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) : + ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : xc->%(func)s(this, %(op_idx)s, %(final_val)s)) ''' + + readNPC = 'xc->readNextPC() & ~PcModeMask' + writeNPC = 'setNextPC(xc, %(final_val)s)' }}; def operands {{ @@ -92,13 +95,12 @@ def operands {{ #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), - 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', None, 40), + 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), - 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50), - 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51) - + 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 50, + readNPC, writeNPC), }}; diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index d100efb8e..cff6b8f2a 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2009 The Regents of The University of Michigan * All rights reserved. * @@ -97,6 +109,13 @@ namespace ArmISA // integer register to allow renaming. static const uint32_t CondCodesMask = 0xF80F0000; + // These otherwise unused bits of the PC are used to select a mode + // like the J and T bits of the CPSR. + static const Addr PcJBitShift = 33; + static const Addr PcTBitShift = 34; + static const Addr PcModeMask = (ULL(1) << PcJBitShift) | + (ULL(1) << PcTBitShift); + BitUnion32(SCTLR) Bitfield<30> te; // Thumb Exception Enable Bitfield<29> afe; // Access flag enable diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 864c061a2..5ed77aea1 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2001-2005 The Regents of The University of Michigan * Copyright (c) 2007 MIPS Technologies, Inc. * Copyright (c) 2007-2008 The Florida State University @@ -278,18 +290,20 @@ TLB::regStats() Fault TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) { + Addr vaddr = req->getVaddr() & ~PcModeMask; #if !FULL_SYSTEM Process * p = tc->getProcessPtr(); - Fault fault = p->pTable->translate(req); - if(fault != NoFault) - return fault; + Addr paddr; + if (!p->pTable->translate(vaddr, paddr)) + return Fault(new GenericPageTableFault(vaddr)); + req->setPaddr(paddr); return NoFault; #else SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); if (!sctlr.m) { - req->setPaddr(req->getVaddr()); + req->setPaddr(vaddr); return NoFault; } panic("MMU translation not implemented\n");