Streamline Cache/Tags interface: get rid of redundant functions,

don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.

--HG--
extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
This commit is contained in:
Steve Reinhardt 2006-12-18 23:07:52 -08:00
parent f655932700
commit 9d7db8bb2b
14 changed files with 38 additions and 350 deletions

View file

@ -279,21 +279,6 @@ class Cache : public BaseCache
*/
PacketPtr writebackBlk(BlkType *blk);
BlkType* findBlock(Addr addr)
{
return tags->findBlock(addr);
}
BlkType* findBlock(PacketPtr &pkt)
{
return tags->findBlock(pkt->getAddr());
}
void invalidateBlk(CacheBlk *blk)
{
tags->invalidateBlk(tags->regenerateBlkAddr(blk->tag, blk->set));
}
public:
class Params
@ -398,14 +383,6 @@ class Cache : public BaseCache
void snoopResponse(PacketPtr &pkt);
/**
* Invalidates the block containing address if found.
* @param addr The address to look for.
* @param asid The address space ID of the address.
* @todo Is this function necessary?
*/
void invalidateBlk(Addr addr);
/**
* Squash all requests associated with specified thread.
* intended for use by I-cache.

View file

@ -113,7 +113,7 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat,
BlkType *blk = NULL;
if (update) {
blk = tags->findBlock(pkt, lat);
blk = tags->findBlock(pkt->getAddr(), lat);
} else {
blk = tags->findBlock(pkt->getAddr());
lat = 0;
@ -221,7 +221,7 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, PacketPtr &pkt,
PacketPtr target)
{
#ifndef NDEBUG
BlkType *tmp_blk = findBlock(pkt->getAddr());
BlkType *tmp_blk = tags->findBlock(pkt->getAddr());
assert(tmp_blk == blk);
#endif
blk = doReplacement(blk, pkt, new_state, writebacks);
@ -239,7 +239,7 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, PacketPtr &pkt,
target->flags |= SATISFIED;
if (target->cmd == Packet::InvalidateReq) {
invalidateBlk(blk);
tags->invalidateBlk(blk);
blk = NULL;
}
@ -318,7 +318,7 @@ Cache<TagStore,Coherence>::handleFill(BlkType *blk, MSHR * mshr,
if (target->cmd == Packet::InvalidateReq) {
//Mark the blk as invalid now, if it hasn't been already
if (blk) {
invalidateBlk(blk);
tags->invalidateBlk(blk);
blk = NULL;
}
@ -396,7 +396,7 @@ Cache<TagStore,Coherence>::handleSnoop(BlkType *blk,
{
if (blk && blk->status != new_state) {
if ((new_state && BlkValid) == 0) {
invalidateBlk(blk);
tags->invalidateBlk(blk);
} else {
assert(new_state >= 0 && new_state < 128);
blk->status = new_state;
@ -628,7 +628,7 @@ Cache<TagStore,Coherence>::getPacket()
if (!pkt->req->isUncacheable()) {
if (pkt->cmd == Packet::HardPFReq)
misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
BlkType *blk = findBlock(pkt);
BlkType *blk = tags->findBlock(pkt->getAddr());
Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
(blk)? blk->status : 0);
missQueue->setBusCmd(pkt, cmd);
@ -657,7 +657,7 @@ Cache<TagStore,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
if (upgrade) {
assert(pkt); //Upgrades need to be fixed
pkt->flags &= ~CACHE_LINE_FILL;
BlkType *blk = findBlock(pkt);
BlkType *blk = tags->findBlock(pkt->getAddr());
CacheBlk::State old_state = (blk) ? blk->status : 0;
CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
if (old_state != new_state)
@ -708,7 +708,7 @@ Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
DPRINTF(Cache, "Block for addr %x being updated in Cache\n",
pkt->getAddr());
blk = findBlock(pkt);
blk = tags->findBlock(pkt->getAddr());
CacheBlk::State old_state = (blk) ? blk->status : 0;
PacketList writebacks;
CacheBlk::State new_state = coherence->getNewState(pkt,old_state);
@ -765,7 +765,7 @@ Cache<TagStore,Coherence>::snoop(PacketPtr &pkt)
}
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = findBlock(pkt);
BlkType *blk = tags->findBlock(pkt->getAddr());
MSHR *mshr = missQueue->findMSHR(blk_addr);
if (coherence->hasProtocol() || pkt->isInvalidate()) {
//@todo Move this into handle bus req
@ -898,13 +898,6 @@ Cache<TagStore,Coherence>::snoopResponse(PacketPtr &pkt)
}
}
template<class TagStore, class Coherence>
void
Cache<TagStore,Coherence>::invalidateBlk(Addr addr)
{
tags->invalidateBlk(addr);
}
/**
* @todo Fix to not assume write allocate
@ -990,7 +983,7 @@ Cache<TagStore,Coherence>::probe(PacketPtr &pkt, bool update,
if (!pkt->req->isUncacheable() /*Uncacheables just go through*/
&& (pkt->cmd != Packet::Writeback)/*Writebacks on miss fall through*/) {
// Fetch the cache block to fill
BlkType *blk = findBlock(pkt);
BlkType *blk = tags->findBlock(pkt->getAddr());
Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
(blk)? blk->status : 0);
@ -1072,7 +1065,7 @@ Cache<TagStore,Coherence>::snoopProbe(PacketPtr &pkt)
}
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = findBlock(pkt);
BlkType *blk = tags->findBlock(pkt->getAddr());
MSHR *mshr = missQueue->findMSHR(blk_addr);
CacheBlk::State new_state = 0;
bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);

View file

@ -153,12 +153,9 @@ FALRU::probe(Addr addr) const
}
void
FALRU::invalidateBlk(Addr addr)
FALRU::invalidateBlk(FALRU::BlkType *blk)
{
Addr blkAddr = blkAlign(addr);
FALRUBlk* blk = (*tagHash.find(blkAddr)).second;
if (blk) {
assert(blk->tag == blkAddr);
blk->status = 0;
blk->isTouched = false;
tagsInUse--;
@ -202,44 +199,6 @@ FALRU::findBlock(Addr addr, int &lat, int *inCache)
return blk;
}
FALRUBlk*
FALRU::findBlock(PacketPtr &pkt, int &lat, int *inCache)
{
Addr addr = pkt->getAddr();
accesses++;
int tmp_in_cache = 0;
Addr blkAddr = blkAlign(addr);
FALRUBlk* blk = hashLookup(blkAddr);
if (blk && blk->isValid()) {
assert(blk->tag == blkAddr);
tmp_in_cache = blk->inCache;
for (int i = 0; i < numCaches; i++) {
if (1<<i & blk->inCache) {
hits[i]++;
} else {
misses[i]++;
}
}
hits[numCaches]++;
if (blk != head){
moveToHead(blk);
}
} else {
blk = NULL;
for (int i = 0; i < numCaches+1; ++i) {
misses[i]++;
}
}
if (inCache) {
*inCache = tmp_in_cache;
}
lat = hitLatency;
//assert(check());
return blk;
}
FALRUBlk*
FALRU::findBlock(Addr addr) const

View file

@ -173,11 +173,10 @@ public:
bool probe(Addr addr) const;
/**
* Invalidate the cache block that contains the given addr.
* @param asid The address space ID.
* @param addr The address to invalidate.
* Invalidate a cache block.
* @param blk The block to invalidate.
*/
void invalidateBlk(Addr addr);
void invalidateBlk(BlkType *blk);
/**
* Find the block in the cache and update the replacement data. Returns
@ -190,16 +189,6 @@ public:
*/
FALRUBlk* findBlock(Addr addr, int &lat, int *inCache = 0);
/**
* Find the block in the cache and update the replacement data. Returns
* the access latency and the in cache flags as a side effect
* @param pkt The req whose block to find
* @param lat The latency of the access.
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
*/
FALRUBlk* findBlock(PacketPtr &pkt, int &lat, int *inCache = 0);
/**
* Find the block in the cache, do not update the replacement data.
* @param addr The address to look for.

View file

@ -284,65 +284,6 @@ IIC::findBlock(Addr addr, int &lat)
return tag_ptr;
}
IICTag*
IIC::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
Addr tag = extractTag(addr);
unsigned set = hash(addr);
int set_lat;
unsigned long chain_ptr;
if (PROFILE_IIC)
setAccess.sample(set);
IICTag *tag_ptr = sets[set].findTag(tag, chain_ptr);
set_lat = 1;
if (tag_ptr == NULL && chain_ptr != tagNull) {
int secondary_depth;
tag_ptr = secondaryChain(tag, chain_ptr, &secondary_depth);
set_lat += secondary_depth;
// set depth for statistics fix this later!!! egh
sets[set].depth = set_lat;
if (tag_ptr != NULL) {
/* need to move tag into primary table */
// need to preserve chain: fix this egh
sets[set].tags[assoc-1]->chain_ptr = tag_ptr->chain_ptr;
tagSwap(tag_ptr - tagStore, sets[set].tags[assoc-1] - tagStore);
tag_ptr = sets[set].findTag(tag, chain_ptr);
assert(tag_ptr!=NULL);
}
}
set_lat = set_lat * hashDelay + hitLatency;
if (tag_ptr != NULL) {
// IIC replacement: if this is not the first element of
// list, reorder
sets[set].moveToHead(tag_ptr);
hitHashDepth.sample(sets[set].depth);
hashHit++;
hitDepthTotal += sets[set].depth;
tag_ptr->status |= BlkReferenced;
lat = set_lat;
if (tag_ptr->whenReady > curTick && tag_ptr->whenReady - curTick > set_lat) {
lat = tag_ptr->whenReady - curTick;
}
tag_ptr->refCount += 1;
}
else {
// fall through: cache block not found, not a hit...
missHashDepth.sample(sets[set].depth);
hashMiss++;
missDepthTotal += sets[set].depth;
lat = set_lat;
}
return tag_ptr;
}
IICTag*
IIC::findBlock(Addr addr) const
@ -695,9 +636,8 @@ IIC::compressBlock(unsigned long index)
}
void
IIC::invalidateBlk(Addr addr)
IIC::invalidateBlk(IIC::BlkType *tag_ptr)
{
IICTag* tag_ptr = findBlock(addr);
if (tag_ptr) {
for (int i = 0; i < tag_ptr->numData; ++i) {
dataReferenceCount[tag_ptr->data_ptr[i]]--;

View file

@ -435,11 +435,10 @@ class IIC : public BaseTags
void compressBlock(unsigned long index);
/**
* Invalidate the block containing the address.
* @param asid The address space ID.
* @param addr The address to invalidate.
* Invalidate a block.
* @param blk The block to invalidate.
*/
void invalidateBlk(Addr addr);
void invalidateBlk(BlkType *blk);
/**
* Find the block and update the replacement data. This call also returns
@ -451,15 +450,6 @@ class IIC : public BaseTags
*/
IICTag* findBlock(Addr addr, int &lat);
/**
* Find the block and update the replacement data. This call also returns
* the access latency as a side effect.
* @param pkt The req whose block to find
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
IICTag* findBlock(PacketPtr &pkt, int &lat);
/**
* Find the block, do not update the replacement data.
* @param addr The address to find.

View file

@ -183,27 +183,6 @@ LRU::findBlock(Addr addr, int &lat)
return blk;
}
LRUBlk*
LRU::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
LRUBlk *blk = sets[set].findBlk(tag);
lat = hitLatency;
if (blk != NULL) {
// move this block to head of the MRU list
sets[set].moveToHead(blk);
if (blk->whenReady > curTick
&& blk->whenReady - curTick > hitLatency) {
lat = blk->whenReady - curTick;
}
blk->refCount += 1;
}
return blk;
}
LRUBlk*
LRU::findBlock(Addr addr) const
@ -240,9 +219,8 @@ LRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
}
void
LRU::invalidateBlk(Addr addr)
LRU::invalidateBlk(LRU::BlkType *blk)
{
LRUBlk *blk = findBlock(addr);
if (blk) {
blk->status = 0;
blk->isTouched = false;

View file

@ -161,20 +161,10 @@ public:
bool probe(Addr addr) const;
/**
* Invalidate the block containing the given address.
* @param asid The address space ID.
* @param addr The address to invalidate.
* Invalidate the given block.
* @param blk The block to invalidate.
*/
void invalidateBlk(Addr addr);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
* @param pkt The request whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
LRUBlk* findBlock(PacketPtr &pkt, int &lat);
void invalidateBlk(BlkType *blk);
/**
* Finds the given address in the cache and update replacement data.

View file

@ -266,58 +266,6 @@ Split::probe(Addr addr) const
return success;
}
SplitBlk*
Split::findBlock(PacketPtr &pkt, int &lat)
{
Addr aligned = blkAlign(pkt->getAddr());
if (memHash.count(aligned)) {
memHash[aligned]++;
} else if (pkt->nic_pkt()) {
memHash[aligned] = 1;
}
SplitBlk *blk = lru->findBlock(pkt->getAddr(), lat);
if (blk) {
if (pkt->nic_pkt()) {
NR_CP_hits++;
} else {
CR_CP_hits++;
}
} else {
if (lifo && lifo_net) {
blk = lifo_net->findBlock(pkt->getAddr(), lat);
} else if (lru_net) {
blk = lru_net->findBlock(pkt->getAddr(), lat);
}
if (blk) {
if (pkt->nic_pkt()) {
NR_NP_hits++;
} else {
CR_NP_hits++;
}
}
}
if (blk) {
Tick latency = curTick - blk->ts;
if (blk->isNIC) {
if (!blk->isUsed && !pkt->nic_pkt()) {
useByCPUCycleDist.sample(latency);
nicUseByCPUCycleTotal += latency;
nicBlksUsedByCPU++;
}
}
blk->isUsed = true;
if (pkt->nic_pkt()) {
DPRINTF(Split, "found block in partition %d\n", blk->part);
}
}
return blk;
}
SplitBlk*
Split::findBlock(Addr addr, int &lat)
@ -403,14 +351,16 @@ Split::findReplacement(PacketPtr &pkt, PacketList &writebacks,
}
void
Split::invalidateBlk(Addr addr)
Split::invalidateBlk(Split::BlkType *blk)
{
SplitBlk *blk = lru->findBlock(addr);
if (!blk) {
fatal("FIXME!\n");
#if 0
if (lifo && lifo_net)
blk = lifo_net->findBlock(addr);
else if (lru_net)
blk = lru_net->findBlock(addr);
#endif
if (!blk)
return;

View file

@ -184,11 +184,10 @@ class Split : public BaseTags
bool probe(Addr addr) const;
/**
* Invalidate the block containing the given address.
* @param asid The address space ID.
* @param addr The address to invalidate.
* Invalidate the given block.
* @param blk The block to invalidate.
*/
void invalidateBlk(Addr addr);
void invalidateBlk(BlkType *blk);
/**
* Finds the given address in the cache and update replacement data.
@ -200,15 +199,6 @@ class Split : public BaseTags
*/
SplitBlk* findBlock(Addr addr, int &lat);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
* @param pkt The memory request whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
* @param addr The address to find.

View file

@ -254,31 +254,6 @@ SplitLIFO::findBlock(Addr addr, int &lat)
return blk;
}
SplitBlk*
SplitLIFO::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
SplitBlk *blk = sets[set].findBlk(tag);
if (blk) {
DPRINTF(Split, "Found LIFO blk %#x in set %d, with tag %#x\n",
addr, set, tag);
hits++;
if (twoQueue) {
blk->isUsed = true;
sets[set].moveToFirstIn(blk);
} else {
sets[set].moveToLastIn(blk);
}
}
lat = hitLatency;
return blk;
}
SplitBlk*
SplitLIFO::findBlock(Addr addr) const
@ -335,9 +310,8 @@ SplitLIFO::findReplacement(PacketPtr &pkt, PacketList &writebacks,
}
void
SplitLIFO::invalidateBlk(Addr addr)
SplitLIFO::invalidateBlk(SplitLIFO::BlkType *blk)
{
SplitBlk *blk = findBlock(addr);
if (blk) {
blk->status = 0;
blk->isTouched = false;

View file

@ -184,11 +184,10 @@ public:
bool probe( Addr addr) const;
/**
* Invalidate the block containing the given address.
* @param asid The address space ID.
* @param addr The address to invalidate.
* Invalidate the given block.
* @param blk The block to invalidate.
*/
void invalidateBlk(Addr addr);
void invalidateBlk(BlkType *blk);
/**
* Finds the given address in the cache and update replacement data.
@ -200,15 +199,6 @@ public:
*/
SplitBlk* findBlock(Addr addr, int &lat);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
* @param pkt The req whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
* @param addr The address to find.

View file

@ -202,27 +202,6 @@ SplitLRU::findBlock(Addr addr, int &lat)
return blk;
}
SplitBlk*
SplitLRU::findBlock(PacketPtr &pkt, int &lat)
{
Addr addr = pkt->getAddr();
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
SplitBlk *blk = sets[set].findBlk(tag);
lat = hitLatency;
if (blk != NULL) {
// move this block to head of the MRU list
sets[set].moveToHead(blk);
if (blk->whenReady > curTick && blk->whenReady - curTick > hitLatency){
lat = blk->whenReady - curTick;
}
blk->refCount += 1;
hits++;
}
return blk;
}
SplitBlk*
SplitLRU::findBlock(Addr addr) const
@ -261,9 +240,8 @@ SplitLRU::findReplacement(PacketPtr &pkt, PacketList &writebacks,
}
void
SplitLRU::invalidateBlk(Addr addr)
SplitLRU::invalidateBlk(SplitLRU::BlkType *blk)
{
SplitBlk *blk = findBlock(addr);
if (blk) {
blk->status = 0;
blk->isTouched = false;

View file

@ -167,11 +167,10 @@ public:
bool probe(Addr addr) const;
/**
* Invalidate the block containing the given address.
* @param asid The address space ID.
* @param addr The address to invalidate.
* Invalidate the given block.
* @param blk The block to invalidate.
*/
void invalidateBlk(Addr addr);
void invalidateBlk(BlkType *blk);
/**
* Finds the given address in the cache and update replacement data.
@ -183,15 +182,6 @@ public:
*/
SplitBlk* findBlock(Addr addr, int &lat);
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
* @param pkt The req whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
SplitBlk* findBlock(PacketPtr &pkt, int &lat);
/**
* Finds the given address in the cache, do not update replacement data.
* @param addr The address to find.