stats: Update stats to reflect ARM changes
This commit is contained in:
Andreas Sandberg
parent
1fac3a292a
commit
9c8710430e
28 changed files with 2105 additions and 2105 deletions
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@ -4,11 +4,11 @@ sim_seconds 2.847227 # Nu
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sim_ticks 2847227406000 # Number of ticks simulated
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final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 262523 # Simulator instruction rate (inst/s)
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host_op_rate 317894 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5870765699 # Simulator tick rate (ticks/s)
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host_mem_usage 664268 # Number of bytes of host memory used
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host_seconds 484.98 # Real time elapsed on the host
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host_inst_rate 166460 # Simulator instruction rate (inst/s)
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host_op_rate 201569 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3722516357 # Simulator tick rate (ticks/s)
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host_mem_usage 624360 # Number of bytes of host memory used
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host_seconds 764.87 # Real time elapsed on the host
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sim_insts 127319545 # Number of instructions simulated
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sim_ops 154173476 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -456,7 +456,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu
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system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -540,7 +540,7 @@ system.cpu0.itb.flush_tlb 66 # Nu
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system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.itb.flush_entries 2216 # Number of entries that have been flushed from TLB
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system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -1406,7 +1406,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu
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system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB
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system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB
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system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions
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system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch
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system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -1495,7 +1495,7 @@ system.cpu1.itb.flush_tlb 66 # Nu
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system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu1.itb.flush_entries 1166 # Number of entries that have been flushed from TLB
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system.cpu1.itb.flush_entries 1102 # Number of entries that have been flushed from TLB
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system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -4,11 +4,11 @@ sim_seconds 2.858505 # Nu
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sim_ticks 2858505242500 # Number of ticks simulated
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final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 258042 # Simulator instruction rate (inst/s)
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host_op_rate 311992 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6591883972 # Simulator tick rate (ticks/s)
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host_mem_usage 625700 # Number of bytes of host memory used
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host_seconds 433.64 # Real time elapsed on the host
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host_inst_rate 152549 # Simulator instruction rate (inst/s)
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host_op_rate 184443 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3896990443 # Simulator tick rate (ticks/s)
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host_mem_usage 585436 # Number of bytes of host memory used
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host_seconds 733.52 # Real time elapsed on the host
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sim_insts 111897168 # Number of instructions simulated
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sim_ops 135292215 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -418,7 +418,7 @@ system.cpu.dtb.flush_tlb 64 # Nu
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system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_entries 4286 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -498,7 +498,7 @@ system.cpu.itb.flush_tlb 64 # Nu
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system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 2992 # Number of entries that have been flushed from TLB
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system.cpu.itb.flush_entries 2928 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu
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sim_ticks 2832862976500 # Number of ticks simulated
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final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 118022 # Simulator instruction rate (inst/s)
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host_op_rate 143150 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2956132692 # Simulator tick rate (ticks/s)
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host_mem_usage 626728 # Number of bytes of host memory used
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host_seconds 958.30 # Real time elapsed on the host
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host_inst_rate 69451 # Simulator instruction rate (inst/s)
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host_op_rate 84238 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1739551926 # Simulator tick rate (ticks/s)
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host_mem_usage 585172 # Number of bytes of host memory used
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host_seconds 1628.50 # Real time elapsed on the host
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sim_insts 113100501 # Number of instructions simulated
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sim_ops 137180951 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -410,7 +410,7 @@ system.cpu.checker.dtb.flush_tlb 128 # Nu
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system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
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system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB
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system.cpu.checker.dtb.flush_entries 4219 # Number of entries that have been flushed from TLB
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system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
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system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -480,7 +480,7 @@ system.cpu.checker.itb.flush_tlb 128 # Nu
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system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
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system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB
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system.cpu.checker.itb.flush_entries 2912 # Number of entries that have been flushed from TLB
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system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -588,7 +588,7 @@ system.cpu.dtb.flush_tlb 128 # Nu
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system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -690,7 +690,7 @@ system.cpu.itb.flush_tlb 128 # Nu
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system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB
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system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -4,11 +4,11 @@ sim_seconds 2.825960 # Nu
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sim_ticks 2825959731500 # Number of ticks simulated
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final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 153141 # Simulator instruction rate (inst/s)
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host_op_rate 185771 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3602870624 # Simulator tick rate (ticks/s)
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host_mem_usage 666712 # Number of bytes of host memory used
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host_seconds 784.36 # Real time elapsed on the host
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host_inst_rate 99061 # Simulator instruction rate (inst/s)
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host_op_rate 120168 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2330545961 # Simulator tick rate (ticks/s)
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host_mem_usage 626024 # Number of bytes of host memory used
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host_seconds 1212.57 # Real time elapsed on the host
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sim_insts 120118276 # Number of instructions simulated
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sim_ops 145712235 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -485,7 +485,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu
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system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -584,7 +584,7 @@ system.cpu0.itb.flush_tlb 66 # Nu
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system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.itb.flush_entries 2345 # Number of entries that have been flushed from TLB
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system.cpu0.itb.flush_entries 2281 # Number of entries that have been flushed from TLB
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -1729,7 +1729,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu
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system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu1.dtb.flush_entries 2051 # Number of entries that have been flushed from TLB
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system.cpu1.dtb.flush_entries 1987 # Number of entries that have been flushed from TLB
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system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions
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system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch
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system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -1830,7 +1830,7 @@ system.cpu1.itb.flush_tlb 66 # Nu
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system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu1.itb.flush_entries 1194 # Number of entries that have been flushed from TLB
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system.cpu1.itb.flush_entries 1130 # Number of entries that have been flushed from TLB
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system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu
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sim_ticks 2832862976500 # Number of ticks simulated
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final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 159277 # Simulator instruction rate (inst/s)
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host_op_rate 193189 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 3989457396 # Simulator tick rate (ticks/s)
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host_mem_usage 626716 # Number of bytes of host memory used
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host_seconds 710.09 # Real time elapsed on the host
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host_inst_rate 93807 # Simulator instruction rate (inst/s)
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host_op_rate 113780 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2349621266 # Simulator tick rate (ticks/s)
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host_mem_usage 586720 # Number of bytes of host memory used
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host_seconds 1205.67 # Real time elapsed on the host
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sim_insts 113100501 # Number of instructions simulated
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sim_ops 137180951 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -444,7 +444,7 @@ system.cpu.dtb.flush_tlb 64 # Nu
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system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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@ -546,7 +546,7 @@ system.cpu.itb.flush_tlb 64 # Nu
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system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB
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system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 47.355903 # Nu
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sim_ticks 47355903328000 # Number of ticks simulated
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final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 277163 # Simulator instruction rate (inst/s)
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host_op_rate 325991 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 14856975599 # Simulator tick rate (ticks/s)
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host_mem_usage 813232 # Number of bytes of host memory used
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host_seconds 3187.45 # Real time elapsed on the host
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host_inst_rate 170836 # Simulator instruction rate (inst/s)
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host_op_rate 200933 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 9157476763 # Simulator tick rate (ticks/s)
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host_mem_usage 772600 # Number of bytes of host memory used
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host_seconds 5171.28 # Real time elapsed on the host
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sim_insts 883443630 # Number of instructions simulated
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sim_ops 1039082168 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -483,7 +483,7 @@ system.cpu0.dtb.flush_tlb 14 # Nu
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system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 39156 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -574,7 +574,7 @@ system.cpu0.itb.flush_tlb 14 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 28333 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1496,7 +1496,7 @@ system.cpu1.dtb.flush_tlb 14 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 35846 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1587,7 +1587,7 @@ system.cpu1.itb.flush_tlb 14 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 25383 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.660653 # Nu
|
|||
sim_ticks 51660652947000 # Number of ticks simulated
|
||||
final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 288085 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 338513 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 16013200726 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 724944 # Number of bytes of host memory used
|
||||
host_seconds 3226.13 # Real time elapsed on the host
|
||||
host_inst_rate 170651 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 200523 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 9485631865 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 683504 # Number of bytes of host memory used
|
||||
host_seconds 5446.20 # Real time elapsed on the host
|
||||
sim_insts 929398934 # Number of instructions simulated
|
||||
sim_ops 1092086880 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -438,7 +438,7 @@ system.cpu.dtb.flush_tlb 11 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 78930 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -524,7 +524,7 @@ system.cpu.itb.flush_tlb 11 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 56526 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu
|
|||
sim_ticks 51327139864000 # Number of ticks simulated
|
||||
final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 139208 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 163572 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8424230073 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 729304 # Number of bytes of host memory used
|
||||
host_seconds 6092.80 # Real time elapsed on the host
|
||||
host_inst_rate 87448 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 102753 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5291966495 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 687348 # Number of bytes of host memory used
|
||||
host_seconds 9699.07 # Real time elapsed on the host
|
||||
sim_insts 848164321 # Number of instructions simulated
|
||||
sim_ops 996610207 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -423,7 +423,7 @@ system.cpu.checker.dtb.flush_tlb 20 # Nu
|
|||
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
|
||||
system.cpu.checker.dtb.flush_entries 71788 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.dtb.flush_entries 71724 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.checker.dtb.prefetch_faults 6683 # Number of TLB faults due to prefetch
|
||||
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -493,7 +493,7 @@ system.cpu.checker.itb.flush_tlb 20 # Nu
|
|||
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
|
||||
system.cpu.checker.itb.flush_entries 51713 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.itb.flush_entries 51649 # Number of entries that have been flushed from TLB
|
||||
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -609,7 +609,7 @@ system.cpu.dtb.flush_tlb 20 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -718,7 +718,7 @@ system.cpu.itb.flush_tlb 20 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 47.384315 # Nu
|
|||
sim_ticks 47384315163000 # Number of ticks simulated
|
||||
final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 162093 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 190619 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8503081814 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 814268 # Number of bytes of host memory used
|
||||
host_seconds 5572.60 # Real time elapsed on the host
|
||||
host_inst_rate 151085 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 177673 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7925620115 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 773240 # Number of bytes of host memory used
|
||||
host_seconds 5978.63 # Real time elapsed on the host
|
||||
sim_insts 903281747 # Number of instructions simulated
|
||||
sim_ops 1062243320 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -471,7 +471,7 @@ system.cpu0.dtb.flush_tlb 14 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 35541 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 35477 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -582,7 +582,7 @@ system.cpu0.itb.flush_tlb 14 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 25342 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 25278 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1797,7 +1797,7 @@ system.cpu1.dtb.flush_tlb 14 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 40949 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 40885 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1905,7 +1905,7 @@ system.cpu1.itb.flush_tlb 14 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 29991 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 29927 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu
|
|||
sim_ticks 51327139864000 # Number of ticks simulated
|
||||
final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 184861 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 217215 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11186950873 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 729056 # Number of bytes of host memory used
|
||||
host_seconds 4588.13 # Real time elapsed on the host
|
||||
host_inst_rate 138298 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 162502 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8369157499 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 688884 # Number of bytes of host memory used
|
||||
host_seconds 6132.89 # Real time elapsed on the host
|
||||
sim_insts 848164321 # Number of instructions simulated
|
||||
sim_ops 996610207 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -465,7 +465,7 @@ system.cpu.dtb.flush_tlb 10 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -574,7 +574,7 @@ system.cpu.itb.flush_tlb 10 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
|
|||
sim_ticks 51111167216500 # Number of ticks simulated
|
||||
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1565564 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1839875 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 81467630636 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 722252 # Number of bytes of host memory used
|
||||
host_seconds 627.38 # Real time elapsed on the host
|
||||
host_inst_rate 974606 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1145373 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50715816566 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 678940 # Number of bytes of host memory used
|
||||
host_seconds 1007.80 # Real time elapsed on the host
|
||||
sim_insts 982203438 # Number of instructions simulated
|
||||
sim_ops 1154301153 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -138,7 +138,7 @@ system.cpu.dtb.flush_tlb 11 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -208,7 +208,7 @@ system.cpu.itb.flush_tlb 11 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 47.216815 # Nu
|
|||
sim_ticks 47216814802000 # Number of ticks simulated
|
||||
final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1563637 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1839381 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 75563871924 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 737620 # Number of bytes of host memory used
|
||||
host_seconds 624.86 # Real time elapsed on the host
|
||||
host_inst_rate 917426 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1079212 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44335256452 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 692848 # Number of bytes of host memory used
|
||||
host_seconds 1064.99 # Real time elapsed on the host
|
||||
sim_insts 977053655 # Number of instructions simulated
|
||||
sim_ops 1149354696 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -169,7 +169,7 @@ system.cpu0.dtb.flush_tlb 16 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 36369 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -239,7 +239,7 @@ system.cpu0.itb.flush_tlb 16 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 25117 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 25053 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -725,7 +725,7 @@ system.cpu1.dtb.flush_tlb 16 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 44858 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 44794 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -795,7 +795,7 @@ system.cpu1.itb.flush_tlb 16 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 31512 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 31448 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
|
|||
sim_ticks 51111167216500 # Number of ticks simulated
|
||||
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1675396 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1968952 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 87182982694 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 718784 # Number of bytes of host memory used
|
||||
host_seconds 586.25 # Real time elapsed on the host
|
||||
host_inst_rate 967952 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1137552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50369548013 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 676592 # Number of bytes of host memory used
|
||||
host_seconds 1014.72 # Real time elapsed on the host
|
||||
sim_insts 982203438 # Number of instructions simulated
|
||||
sim_ops 1154301153 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -138,7 +138,7 @@ system.cpu.dtb.flush_tlb 11 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -208,7 +208,7 @@ system.cpu.itb.flush_tlb 11 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 47.522770 # Nu
|
|||
sim_ticks 47522770414500 # Number of ticks simulated
|
||||
final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 967829 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1138446 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52174728436 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 796444 # Number of bytes of host memory used
|
||||
host_seconds 910.84 # Real time elapsed on the host
|
||||
host_inst_rate 594104 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 698838 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32027606991 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 752504 # Number of bytes of host memory used
|
||||
host_seconds 1483.81 # Real time elapsed on the host
|
||||
sim_insts 881535802 # Number of instructions simulated
|
||||
sim_ops 1036940641 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -477,7 +477,7 @@ system.cpu0.dtb.flush_tlb 14 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 37476 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 37412 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 4693 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -563,7 +563,7 @@ system.cpu0.itb.flush_tlb 14 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 26626 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 26562 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1478,7 +1478,7 @@ system.cpu1.dtb.flush_tlb 14 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 37178 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 37114 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1570,7 +1570,7 @@ system.cpu1.itb.flush_tlb 14 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 41069 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 25875 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 25811 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.759374 # Nu
|
|||
sim_ticks 51759374264500 # Number of ticks simulated
|
||||
final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1051370 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1235514 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 65021013988 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 718040 # Number of bytes of host memory used
|
||||
host_seconds 796.04 # Real time elapsed on the host
|
||||
host_inst_rate 622194 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 731170 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 38479042536 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 677104 # Number of bytes of host memory used
|
||||
host_seconds 1345.13 # Real time elapsed on the host
|
||||
sim_insts 836933434 # Number of instructions simulated
|
||||
sim_ops 983519389 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -432,7 +432,7 @@ system.cpu.dtb.flush_tlb 10 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 70937 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -520,7 +520,7 @@ system.cpu.itb.flush_tlb 10 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 50613 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111166 # Nu
|
|||
sim_ticks 51111166190000 # Number of ticks simulated
|
||||
final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1663860 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1955365 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 86501229007 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 721112 # Number of bytes of host memory used
|
||||
host_seconds 590.87 # Real time elapsed on the host
|
||||
host_inst_rate 942692 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1107850 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 49008962729 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679656 # Number of bytes of host memory used
|
||||
host_seconds 1042.89 # Real time elapsed on the host
|
||||
sim_insts 983128290 # Number of instructions simulated
|
||||
sim_ops 1155370468 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -156,7 +156,7 @@ system.cpu0.dtb.flush_tlb 51122 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 56806 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 56742 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -226,7 +226,7 @@ system.cpu0.itb.flush_tlb 51122 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 40500 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 40436 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -560,7 +560,7 @@ system.cpu1.dtb.flush_tlb 51111 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 56691 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 56630 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 4731 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -630,7 +630,7 @@ system.cpu1.itb.flush_tlb 51111 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 41078 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 41017 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.316243 # Nu
|
|||
sim_ticks 51316242679000 # Number of ticks simulated
|
||||
final_tick 51316242679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 414274 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 486791 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24763727262 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 734172 # Number of bytes of host memory used
|
||||
host_seconds 2072.23 # Real time elapsed on the host
|
||||
host_inst_rate 261245 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 306975 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15616250138 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 693224 # Number of bytes of host memory used
|
||||
host_seconds 3286.08 # Real time elapsed on the host
|
||||
sim_insts 858473131 # Number of instructions simulated
|
||||
sim_ops 1008744567 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -373,10 +373,10 @@ system.physmem_1.preEnergy 539141625 # En
|
|||
system.physmem_1.readEnergy 1669683600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 1531975680 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1172484635445 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29689595916750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34179777578340 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 667.615263 # Core power per rank (mW)
|
||||
system.physmem_1.actBackEnergy 1172482833105 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29689600432500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34179780291750 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 667.615252 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 48917806002648 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1693745040000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
|
|
@ -470,7 +470,7 @@ system.cpu0.dtb.flush_tlb 1192 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 41149 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 41085 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 2806 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -542,7 +542,7 @@ system.cpu0.itb.flush_tlb 1192 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 28999 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 28935 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1294,7 +1294,7 @@ system.cpu1.dtb.flush_tlb 1184 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 18131 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 18070 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1382,7 +1382,7 @@ system.cpu1.itb.flush_tlb 1184 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 13509 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 13448 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1555,7 +1555,7 @@ system.cpu2.dtb.flush_tlb 1184 # Nu
|
|||
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu2.dtb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID
|
||||
system.cpu2.dtb.flush_entries 22306 # Number of entries that have been flushed from TLB
|
||||
system.cpu2.dtb.flush_entries 22245 # Number of entries that have been flushed from TLB
|
||||
system.cpu2.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu2.dtb.prefetch_faults 2280 # Number of TLB faults due to prefetch
|
||||
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1644,7 +1644,7 @@ system.cpu2.itb.flush_tlb 1184 # Nu
|
|||
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu2.itb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID
|
||||
system.cpu2.itb.flush_entries 16608 # Number of entries that have been flushed from TLB
|
||||
system.cpu2.itb.flush_entries 16547 # Number of entries that have been flushed from TLB
|
||||
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1849,7 +1849,7 @@ system.cpu3.dtb.flush_tlb 1184 # Nu
|
|||
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu3.dtb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu3.dtb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID
|
||||
system.cpu3.dtb.flush_entries 29776 # Number of entries that have been flushed from TLB
|
||||
system.cpu3.dtb.flush_entries 29715 # Number of entries that have been flushed from TLB
|
||||
system.cpu3.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu3.dtb.prefetch_faults 5087 # Number of TLB faults due to prefetch
|
||||
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1958,7 +1958,7 @@ system.cpu3.itb.flush_tlb 1184 # Nu
|
|||
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu3.itb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu3.itb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID
|
||||
system.cpu3.itb.flush_entries 22881 # Number of entries that have been flushed from TLB
|
||||
system.cpu3.itb.flush_entries 22821 # Number of entries that have been flushed from TLB
|
||||
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.317219 # Nu
|
|||
sim_ticks 51317219225000 # Number of ticks simulated
|
||||
final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 203116 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 238662 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11427931870 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 741344 # Number of bytes of host memory used
|
||||
host_seconds 4490.51 # Real time elapsed on the host
|
||||
host_inst_rate 237803 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 279419 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 13379498708 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 700916 # Number of bytes of host memory used
|
||||
host_seconds 3835.51 # Real time elapsed on the host
|
||||
sim_insts 912094204 # Number of instructions simulated
|
||||
sim_ops 1071714405 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -485,7 +485,7 @@ system.cpu0.dtb.flush_tlb 1081 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 55450 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 55386 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -592,7 +592,7 @@ system.cpu0.itb.flush_tlb 1081 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 40899 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 40835 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1491,7 +1491,7 @@ system.cpu1.dtb.flush_tlb 1089 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 55426 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 55362 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1603,7 +1603,7 @@ system.cpu1.itb.flush_tlb 1089 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 40809 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 40745 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.821000 # Nu
|
|||
sim_ticks 51820999867500 # Number of ticks simulated
|
||||
final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1076689 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1265246 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 62402323103 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 722120 # Number of bytes of host memory used
|
||||
host_seconds 830.43 # Real time elapsed on the host
|
||||
host_inst_rate 622691 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 731741 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36089691928 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 680680 # Number of bytes of host memory used
|
||||
host_seconds 1435.89 # Real time elapsed on the host
|
||||
sim_insts 894119248 # Number of instructions simulated
|
||||
sim_ops 1050702892 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -457,7 +457,7 @@ system.cpu0.dtb.flush_tlb 51828 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 73288 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 73224 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -543,7 +543,7 @@ system.cpu0.itb.flush_tlb 51828 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 53811 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 53747 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1158,7 +1158,7 @@ system.cpu1.dtb.flush_tlb 51822 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 74029 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 73965 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1250,7 +1250,7 @@ system.cpu1.itb.flush_tlb 51822 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 53985 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 53921 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1481321 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1803271 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 28883760858 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 624788 # Number of bytes of host memory used
|
||||
host_seconds 96.38 # Real time elapsed on the host
|
||||
host_inst_rate 829938 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1010316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 16182659197 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581892 # Number of bytes of host memory used
|
||||
host_seconds 172.03 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -134,7 +134,7 @@ system.cpu.dtb.flush_tlb 64 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -204,7 +204,7 @@ system.cpu.itb.flush_tlb 64 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.802883 # Nu
|
|||
sim_ticks 2802882797500 # Number of ticks simulated
|
||||
final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1371763 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1671473 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26186322462 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 640448 # Number of bytes of host memory used
|
||||
host_seconds 107.04 # Real time elapsed on the host
|
||||
host_inst_rate 808897 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 985629 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15441476365 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 596572 # Number of bytes of host memory used
|
||||
host_seconds 181.52 # Real time elapsed on the host
|
||||
sim_insts 146828219 # Number of instructions simulated
|
||||
sim_ops 178907974 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -153,7 +153,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -223,7 +223,7 @@ system.cpu0.itb.flush_tlb 66 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -683,7 +683,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -753,7 +753,7 @@ system.cpu1.itb.flush_tlb 66 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1429089 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1739687 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27865307050 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 619548 # Number of bytes of host memory used
|
||||
host_seconds 99.90 # Real time elapsed on the host
|
||||
host_inst_rate 972221 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1183523 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 18956985191 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 578524 # Number of bytes of host memory used
|
||||
host_seconds 146.85 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -134,7 +134,7 @@ system.cpu.dtb.flush_tlb 64 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -204,7 +204,7 @@ system.cpu.itb.flush_tlb 64 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.869789 # Nu
|
|||
sim_ticks 2869788970000 # Number of ticks simulated
|
||||
final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 932940 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1128445 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 20351712140 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 661084 # Number of bytes of host memory used
|
||||
host_seconds 141.01 # Real time elapsed on the host
|
||||
host_inst_rate 540600 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 653886 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 11792964574 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 618088 # Number of bytes of host memory used
|
||||
host_seconds 243.35 # Real time elapsed on the host
|
||||
sim_insts 131553574 # Number of instructions simulated
|
||||
sim_ops 159121622 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -440,7 +440,7 @@ system.cpu0.dtb.flush_tlb 66 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 3392 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -526,7 +526,7 @@ system.cpu0.itb.flush_tlb 66 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1383,7 +1383,7 @@ system.cpu1.dtb.flush_tlb 66 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 1980 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1472,7 +1472,7 @@ system.cpu1.itb.flush_tlb 66 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu
|
|||
sim_ticks 2909586837500 # Number of ticks simulated
|
||||
final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 987334 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1190416 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 25545157236 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 619552 # Number of bytes of host memory used
|
||||
host_seconds 113.90 # Real time elapsed on the host
|
||||
host_inst_rate 567099 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 683745 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 14672489619 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 579808 # Number of bytes of host memory used
|
||||
host_seconds 198.30 # Real time elapsed on the host
|
||||
sim_insts 112457035 # Number of instructions simulated
|
||||
sim_ops 135588119 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -404,7 +404,7 @@ system.cpu.dtb.flush_tlb 64 # Nu
|
|||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 4208 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -484,7 +484,7 @@ system.cpu.itb.flush_tlb 64 # Nu
|
|||
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783854 # Nu
|
|||
sim_ticks 2783853866500 # Number of ticks simulated
|
||||
final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1399722 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1703936 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27292901384 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 623636 # Number of bytes of host memory used
|
||||
host_seconds 102.00 # Real time elapsed on the host
|
||||
host_inst_rate 812896 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 989570 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15850505887 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 582360 # Number of bytes of host memory used
|
||||
host_seconds 175.63 # Real time elapsed on the host
|
||||
sim_insts 142770436 # Number of instructions simulated
|
||||
sim_ops 173800089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -151,7 +151,7 @@ system.cpu0.dtb.flush_tlb 2813 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 3231 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 3167 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -221,7 +221,7 @@ system.cpu0.itb.flush_tlb 2813 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 1843 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -543,7 +543,7 @@ system.cpu1.dtb.flush_tlb 2817 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 3189 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 3135 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -613,7 +613,7 @@ system.cpu1.itb.flush_tlb 2817 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 1961 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.903880 # Nu
|
|||
sim_ticks 2903879904500 # Number of ticks simulated
|
||||
final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 952808 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1148802 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24600165137 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 624836 # Number of bytes of host memory used
|
||||
host_seconds 118.04 # Real time elapsed on the host
|
||||
host_inst_rate 551812 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 665321 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 14247014061 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 583128 # Number of bytes of host memory used
|
||||
host_seconds 203.82 # Real time elapsed on the host
|
||||
sim_insts 112472358 # Number of instructions simulated
|
||||
sim_ops 135608167 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -436,7 +436,7 @@ system.cpu0.dtb.flush_tlb 2937 # Nu
|
|||
system.cpu0.dtb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.dtb.flush_entries 4577 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.flush_entries 4513 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.dtb.prefetch_faults 883 # Number of TLB faults due to prefetch
|
||||
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -518,7 +518,7 @@ system.cpu0.itb.flush_tlb 2937 # Nu
|
|||
system.cpu0.itb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA
|
||||
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu0.itb.flush_entries 2718 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.flush_entries 2654 # Number of entries that have been flushed from TLB
|
||||
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1071,7 +1071,7 @@ system.cpu1.dtb.flush_tlb 2933 # Nu
|
|||
system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.dtb.flush_entries 4004 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.flush_entries 3948 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.dtb.prefetch_faults 895 # Number of TLB faults due to prefetch
|
||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
@ -1153,7 +1153,7 @@ system.cpu1.itb.flush_tlb 2933 # Nu
|
|||
system.cpu1.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA
|
||||
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu1.itb.flush_entries 2384 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.flush_entries 2325 # Number of entries that have been flushed from TLB
|
||||
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
|
|
|
|||
Loading…
Reference in a new issue