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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
Andreas Sandberg 9c8710430e stats: Update stats to reflect ARM changes
2016-06-21 16:42:04 +01:00

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---------- Begin Simulation Statistics ----------
sim_seconds 47.355903 # Number of seconds simulated
sim_ticks 47355903328000 # Number of ticks simulated
final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 170836 # Simulator instruction rate (inst/s)
host_op_rate 200933 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9157476763 # Simulator tick rate (ticks/s)
host_mem_usage 772600 # Number of bytes of host memory used
host_seconds 5171.28 # Real time elapsed on the host
sim_insts 883443630 # Number of instructions simulated
sim_ops 1039082168 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory
system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory
system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 977362 # Number of read requests accepted
system.physmem.writeReqs 1184351 # Number of write requests accepted
system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue
system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 54912 # Per bank write bursts
system.physmem.perBankRdBursts::1 56908 # Per bank write bursts
system.physmem.perBankRdBursts::2 51582 # Per bank write bursts
system.physmem.perBankRdBursts::3 63469 # Per bank write bursts
system.physmem.perBankRdBursts::4 61411 # Per bank write bursts
system.physmem.perBankRdBursts::5 61841 # Per bank write bursts
system.physmem.perBankRdBursts::6 57272 # Per bank write bursts
system.physmem.perBankRdBursts::7 62841 # Per bank write bursts
system.physmem.perBankRdBursts::8 51834 # Per bank write bursts
system.physmem.perBankRdBursts::9 112088 # Per bank write bursts
system.physmem.perBankRdBursts::10 55237 # Per bank write bursts
system.physmem.perBankRdBursts::11 58857 # Per bank write bursts
system.physmem.perBankRdBursts::12 56745 # Per bank write bursts
system.physmem.perBankRdBursts::13 58205 # Per bank write bursts
system.physmem.perBankRdBursts::14 53859 # Per bank write bursts
system.physmem.perBankRdBursts::15 59928 # Per bank write bursts
system.physmem.perBankWrBursts::0 69820 # Per bank write bursts
system.physmem.perBankWrBursts::1 73385 # Per bank write bursts
system.physmem.perBankWrBursts::2 70846 # Per bank write bursts
system.physmem.perBankWrBursts::3 76844 # Per bank write bursts
system.physmem.perBankWrBursts::4 76655 # Per bank write bursts
system.physmem.perBankWrBursts::5 78828 # Per bank write bursts
system.physmem.perBankWrBursts::6 72793 # Per bank write bursts
system.physmem.perBankWrBursts::7 76848 # Per bank write bursts
system.physmem.perBankWrBursts::8 69899 # Per bank write bursts
system.physmem.perBankWrBursts::9 74878 # Per bank write bursts
system.physmem.perBankWrBursts::10 69893 # Per bank write bursts
system.physmem.perBankWrBursts::11 73658 # Per bank write bursts
system.physmem.perBankWrBursts::12 73258 # Per bank write bursts
system.physmem.perBankWrBursts::13 76164 # Per bank write bursts
system.physmem.perBankWrBursts::14 72361 # Per bank write bursts
system.physmem.perBankWrBursts::15 75956 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 28 # Number of times write queue was full causing retry
system.physmem.totGap 47355901307500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 977332 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1181777 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads
system.physmem.totQLat 32578317305 # Total ticks spent queuing
system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers
system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing
system.physmem.readRowHits 734277 # Number of row buffer hits during reads
system.physmem.writeRowHits 451275 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes
system.physmem.avgGap 21906655.19 # Average gap between requests
system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.658673 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states
system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.651183 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states
system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 145452632 # Number of BP lookups
system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 298304 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 93899745 # DTB read hits
system.cpu0.dtb.read_misses 250404 # DTB read misses
system.cpu0.dtb.write_hits 82108561 # DTB write hits
system.cpu0.dtb.write_misses 47900 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 94150149 # DTB read accesses
system.cpu0.dtb.write_accesses 82156461 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 176008306 # DTB hits
system.cpu0.dtb.misses 298304 # DTB misses
system.cpu0.dtb.accesses 176306610 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 65048 # Table walker walks requested
system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 259203584 # ITB inst hits
system.cpu0.itb.inst_misses 65048 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses
system.cpu0.itb.hits 259203584 # DTB hits
system.cpu0.itb.misses 65048 # DTB misses
system.cpu0.itb.accesses 259268632 # DTB accesses
system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 1023758481 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 483101155 # Number of instructions committed
system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed
system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit
system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching
system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.cpi 2.119139 # CPI: cycles per instruction
system.cpu0.ipc 0.471890 # IPC: instructions per cycle
system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction
system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction
system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction
system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction
system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction
system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction
system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction
system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.op_class_0::total 567019823 # Class of committed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed
system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked
system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 6026209 # number of replacements
system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits
system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses
system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks
system.cpu0.dcache.writebacks::total 6026220 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits
system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 9817579 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits
system.cpu0.icache.overall_hits::total 249208397 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses
system.cpu0.icache.overall_misses::total 9818101 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 9817579 # number of writebacks
system.cpu0.icache.writebacks::total 9817579 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9818101 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 9818101 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 9818101 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 9818101 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 9818101 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 9818101 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 52299 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 52299 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94093068000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 94093068000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94093068000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 94093068000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94093068000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 94093068000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4837195500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 4837195500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037904 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.037904 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.037904 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9583.632110 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2829183 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 60.708141 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 787.823770 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.931229 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003513 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003705 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048085 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.986532 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1356 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14748 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 123 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 574 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 643 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1176 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 611 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 933174 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 933174 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9093916 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 9093916 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3073539 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 3073539 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216814 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 216814 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 561309 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167224 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 9093916 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 4006713 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 13829162 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 561309 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167224 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 9093916 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 4006713 # number of overall hits
system.cpu0.l2cache.overall_hits::total 13829162 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12299 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8468 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 20767 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256901 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 256901 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195411 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 195411 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 279617 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 279617 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 724184 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 724184 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1019232 # number of ReadSharedReq misses
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system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10301948000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5883144500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10301948000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027711 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 123875539 # Number of BP lookups
system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 255224 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 78594683 # DTB read hits
system.cpu1.dtb.read_misses 208094 # DTB read misses
system.cpu1.dtb.write_hits 69544419 # DTB write hits
system.cpu1.dtb.write_misses 47130 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 78802777 # DTB read accesses
system.cpu1.dtb.write_accesses 69591549 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 148139102 # DTB hits
system.cpu1.dtb.misses 255224 # DTB misses
system.cpu1.dtb.accesses 148394326 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 62177 # Table walker walks requested
system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 219337574 # ITB inst hits
system.cpu1.itb.inst_misses 62177 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses
system.cpu1.itb.hits 219337574 # DTB hits
system.cpu1.itb.misses 62177 # DTB misses
system.cpu1.itb.accesses 219399751 # DTB accesses
system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 838096745 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 400342475 # Number of instructions committed
system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed
system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit
system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching
system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.cpi 2.093449 # CPI: cycles per instruction
system.cpu1.ipc 0.477681 # IPC: instructions per cycle
system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction
system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction
system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction
system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction
system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction
system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction
system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction
system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.op_class_0::total 472062345 # Class of committed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed
system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked
system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 4810857 # number of replacements
system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits
system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses
system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks
system.cpu1.dcache.writebacks::total 4810864 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits
system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 8744967 # number of replacements
system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits
system.cpu1.icache.overall_hits::total 210419103 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 8745479 # number of overall misses
system.cpu1.icache.overall_misses::total 8745479 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88268174500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 88268174500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 88268174500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 88268174500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 88268174500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 88268174500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 219164582 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 219164582 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 219164582 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 219164582 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks
system.cpu1.icache.writebacks::total 8744967 # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2218428 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 44.102544 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.983954 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.763922 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003868 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002692 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048583 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.819065 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14164 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 771 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 263 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 434 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 789107 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 789107 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8072877 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 8072877 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2507088 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2507088 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 171056 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 171056 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 494400 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160613 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 8072877 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3296195 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 12024085 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 494400 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160613 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 8072877 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3296195 # number of overall hits
system.cpu1.l2cache.overall_hits::total 12024085 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11721 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8689 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 20410 # number of ReadReq misses
system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 220631 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 220631 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192879 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 192879 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 261966 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 261966 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 672602 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 672602 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 931427 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 931427 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242391 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 242391 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11721 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8689 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 672602 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1193393 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1886405 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11721 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8689 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 672602 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1193393 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1886405 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 429270500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 326619000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 755889500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1918862500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 1918862500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1442678000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1442678000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2273499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2273499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10385042497 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 10385042497 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22017991000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22017991000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30592821494 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 30592821494 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 352126000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 352126000 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 429270500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 326619000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22017991000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 40977863991 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 63751744491 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 429270500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 326619000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22017991000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 40977863991 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 63751744491 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 506121 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169302 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 675423 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3026489 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3026489 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 10527431 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 10527431 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 221065 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 221065 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192879 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 192879 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051073 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1051073 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8745479 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 8745479 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3438515 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3438515 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 413447 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 413447 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 506121 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169302 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 8745479 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4489588 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 13910490 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 506121 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169302 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 8745479 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4489588 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 13910490 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051322 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.030218 # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998037 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998037 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.249237 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.249237 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076909 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076909 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.270881 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.270881 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.586269 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.586269 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051322 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076909 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265813 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.135610 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051322 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076909 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265813 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.135610 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37589.941305 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 37035.252327 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8697.157244 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8697.157244 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7479.704893 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7479.704893 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 568374.750000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 568374.750000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39642.711256 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39642.711256 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32735.541970 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32735.541970 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32845.109165 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32845.109165 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1452.718954 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1452.718954 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 33795.364458 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 33795.364458 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches 43661 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1101410 # number of writebacks
system.cpu1.l2cache.writebacks::total 1101410 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4694 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 4694 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 558 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 558 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5252 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 5258 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5252 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 5258 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11720 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8687 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 20407 # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 709103 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 220631 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 220631 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192879 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192879 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257272 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 257272 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 672599 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 672599 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 930869 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 930869 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 242391 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 242391 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11720 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8687 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 672599 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1188141 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1881147 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11720 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8687 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 672599 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1188141 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2590250 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7034 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14314 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 274457000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 633384500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 25470013765 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4591069994 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4591069994 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3129353001 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3129353001 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2003499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2003499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8263742497 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8263742497 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17982320500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17982320500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24961268994 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24961268994 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6347282500 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6347282500 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 274457000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17982320500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33225011491 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 51840716491 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 274457000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17982320500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33225011491 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 77310730256 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7706000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 781601000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 789307000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7706000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 781601000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 789307000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.030214 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998037 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998037 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.244771 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.244771 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076908 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.270718 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270718 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.586269 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.586269 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40337 # Transaction distribution
system.iobus.trans_dist::ReadResp 40337 # Transaction distribution
system.iobus.trans_dist::WriteReq 136616 # Transaction distribution
system.iobus.trans_dist::WriteResp 136616 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115611 # number of replacements
system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040883 # Number of tag accesses
system.iocache.tags.data_accesses 1040883 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses
system.iocache.demand_misses::total 115654 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115614 # number of overall misses
system.iocache.overall_misses::total 115654 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106695 # number of writebacks
system.iocache.writebacks::total 106695 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1371243 # number of replacements
system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use
system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 79235647 # Number of tag accesses
system.l2c.tags.data_accesses 79235647 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits
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system.l2c.overall_avg_miss_latency::total 105053.554886 # average overall miss latency
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
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system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.312881 # mshr miss rate for UpgradeReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for ReadSharedReq accesses
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system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.415262 # mshr miss rate for InvalidateReq accesses
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system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for overall accesses
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21647.742077 # average UpgradeReq mshr miss latency
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system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 91033 # Transaction distribution
system.membus.trans_dist::ReadResp 892432 # Transaction distribution
system.membus.trans_dist::WriteReq 38505 # Transaction distribution
system.membus.trans_dist::WriteResp 38505 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution
system.membus.trans_dist::CleanEvict 252869 # Transaction distribution
system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution
system.membus.trans_dist::UpgradeResp 22 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 143945 # Transaction distribution
system.membus.trans_dist::ReadExResp 126263 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution
system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 608511 # Total snoops (count)
system.membus.snoop_fanout::samples 2484071 # Request fanout histogram
system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram
system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2484071 # Request fanout histogram
system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2830390 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
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