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regressions: update stats due to branch predictor changes

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The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
This commit is contained in:
Nilay Vaish 2013-01-24 12:29:00 -06:00
parent dbeabedaf0
commit 9bc132e473
408 changed files with 12174 additions and 11479 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

82
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem
boot_cpu_frequency=500 boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0 boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000 clock=1000
console=/gem5/dist/binaries/console console=/scratch/nilay/GEM5/system/binaries/console
init_param=0 init_param=0
kernel=/gem5/dist/binaries/vmlinux kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
pal=/gem5/dist/binaries/ts_osfpal pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh readfile=tests/halt.sh
symbolfile= symbolfile=
system_rev=1024 system_rev=1024
@ -46,22 +46,18 @@ slave=system.membus.master[0]
[system.cpu0] [system.cpu0]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb tracer children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu0.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -84,23 +80,15 @@ forwardComSize=5
fuPool=system.cpu0.fuPool fuPool=system.cpu0.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts interrupts=system.cpu0.interrupts
isa=system.cpu0.isa isa=system.cpu0.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu0.itb itb=system.cpu0.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -112,7 +100,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -141,6 +128,24 @@ workload=
dcache_port=system.cpu0.dcache.cpu_side dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu0.dcache] [system.cpu0.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -467,22 +472,18 @@ type=ExeTracer
[system.cpu1] [system.cpu1]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb tracer children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu1.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -505,23 +506,15 @@ forwardComSize=5
fuPool=system.cpu1.fuPool fuPool=system.cpu1.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts interrupts=system.cpu1.interrupts
isa=system.cpu1.isa isa=system.cpu1.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu1.itb itb=system.cpu1.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -533,7 +526,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -562,6 +554,24 @@ workload=
dcache_port=system.cpu1.dcache.cpu_side dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu1.dcache] [system.cpu1.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -903,7 +913,7 @@ table_size=65536
[system.disk0.image.child] [system.disk0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-latest.img image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true read_only=true
[system.disk2] [system.disk2]
@ -923,7 +933,7 @@ table_size=65536
[system.disk2.image.child] [system.disk2.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-bigswap2.img image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true read_only=true
[system.intrctrl] [system.intrctrl]
@ -1048,7 +1058,7 @@ system=system
[system.simple_disk.disk] [system.simple_disk.disk]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-latest.img image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true read_only=true
[system.terminal] [system.terminal]

14
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:09:21 gem5 compiled Jan 23 2013 13:29:14
gem5 started Jan 4 2013 21:41:13 gem5 started Jan 23 2013 13:29:25
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /gem5/dist/binaries/vmlinux info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 107840000 info: Launching CPU 1 @ 107825000
Exiting @ tick 1897857556000 because m5_exit instruction encountered Exiting @ tick 1901719660500 because m5_exit instruction encountered

44
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.901720 # Nu
sim_ticks 1901719660500 # Number of ticks simulated sim_ticks 1901719660500 # Number of ticks simulated
final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 128809 # Simulator instruction rate (inst/s) host_inst_rate 97307 # Simulator instruction rate (inst/s)
host_op_rate 128809 # Simulator op (including micro ops) rate (op/s) host_op_rate 97307 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4317556960 # Simulator tick rate (ticks/s) host_tick_rate 3261646555 # Simulator tick rate (ticks/s)
host_mem_usage 340604 # Number of bytes of host memory used host_mem_usage 383552 # Number of bytes of host memory used
host_seconds 440.46 # Real time elapsed on the host host_seconds 583.06 # Real time elapsed on the host
sim_insts 56735321 # Number of instructions simulated sim_insts 56735321 # Number of instructions simulated
sim_ops 56735321 # Number of ops (including micro ops) simulated sim_ops 56735321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory
@ -612,6 +612,15 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 12372868 # Number of BP lookups
system.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_acv 0 # ITB acv
@ -647,14 +656,6 @@ system.cpu0.itb.data_accesses 0 # DT
system.cpu0.numCycles 101814962 # number of cpu cycles simulated system.cpu0.numCycles 101814962 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 12372868 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 10433314 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 330387 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 8151024 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 5278103 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 784011 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 32544 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered
@ -1192,6 +1193,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 2617746 # Number of BP lookups
system.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 873996 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_acv 0 # ITB acv
@ -1227,14 +1237,6 @@ system.cpu1.itb.data_accesses 0 # DT
system.cpu1.numCycles 16039611 # number of cpu cycles simulated system.cpu1.numCycles 16039611 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 2617746 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 2161338 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 77903 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 1516620 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 873996 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 182212 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 8242 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered

47
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis
boot_cpu_frequency=500 boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0 boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000 clock=1000
console=/gem5/dist/binaries/console console=/scratch/nilay/GEM5/system/binaries/console
init_param=0 init_param=0
kernel=/gem5/dist/binaries/vmlinux kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
pal=/gem5/dist/binaries/ts_osfpal pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh readfile=tests/halt.sh
symbolfile= symbolfile=
system_rev=1024 system_rev=1024
@ -46,22 +46,18 @@ slave=system.membus.master[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -84,23 +80,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -112,7 +100,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -141,6 +128,24 @@ workload=
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -514,7 +519,7 @@ table_size=65536
[system.disk0.image.child] [system.disk0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-latest.img image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true read_only=true
[system.disk2] [system.disk2]
@ -534,7 +539,7 @@ table_size=65536
[system.disk2.image.child] [system.disk2.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-bigswap2.img image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true read_only=true
[system.intrctrl] [system.intrctrl]
@ -637,7 +642,7 @@ system=system
[system.simple_disk.disk] [system.simple_disk.disk]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-latest.img image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true read_only=true
[system.terminal] [system.terminal]

12
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:09:21 gem5 compiled Jan 23 2013 13:29:14
gem5 started Jan 4 2013 21:39:46 gem5 started Jan 23 2013 13:39:31
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /gem5/dist/binaries/vmlinux info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1854349611000 because m5_exit instruction encountered Exiting @ tick 1854344296500 because m5_exit instruction encountered

27
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.854344 # Nu
sim_ticks 1854344296500 # Number of ticks simulated sim_ticks 1854344296500 # Number of ticks simulated
final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131278 # Simulator instruction rate (inst/s) host_inst_rate 90928 # Simulator instruction rate (inst/s)
host_op_rate 131278 # Simulator op (including micro ops) rate (op/s) host_op_rate 90928 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4595190559 # Simulator tick rate (ticks/s) host_tick_rate 3182808238 # Simulator tick rate (ticks/s)
host_mem_usage 336376 # Number of bytes of host memory used host_mem_usage 379332 # Number of bytes of host memory used
host_seconds 403.54 # Real time elapsed on the host host_seconds 582.61 # Real time elapsed on the host
sim_insts 52976017 # Number of instructions simulated sim_insts 52976017 # Number of instructions simulated
sim_ops 52976017 # Number of ops (including micro ops) simulated sim_ops 52976017 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory
@ -300,6 +300,15 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.branchPred.lookups 13851594 # Number of BP lookups
system.cpu.branchPred.condPredicted 11614390 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 401305 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9533712 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5819078 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 61.036855 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 909714 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 39020 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -335,14 +344,6 @@ system.cpu.itb.data_accesses 0 # DT
system.cpu.numCycles 108725026 # number of cpu cycles simulated system.cpu.numCycles 108725026 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 13851594 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11614390 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 401305 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 9533712 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 5819078 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 909714 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 39020 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed
system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered

49
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
View file

@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus phy
boot_cpu_frequency=500 boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0 boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000 clock=1000
console=/arm/scratch/sysexplr/dist/binaries/console console=/scratch/nilay/GEM5/system/binaries/console
init_param=0 init_param=0
kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh readfile=tests/halt.sh
symbolfile= symbolfile=
system_rev=1024 system_rev=1024
@ -47,6 +47,7 @@ slave=system.membus.master[0]
[system.cpu0] [system.cpu0]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer children=dcache dtb icache interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
@ -141,6 +142,7 @@ type=ExeTracer
[system.cpu1] [system.cpu1]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dtb interrupts isa itb tracer children=dtb interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
@ -184,22 +186,18 @@ type=ExeTracer
[system.cpu2] [system.cpu2]
type=DerivO3CPU type=DerivO3CPU
children=dtb fuPool interrupts isa itb tracer children=branchPred dtb fuPool interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu2.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -222,23 +220,15 @@ forwardComSize=5
fuPool=system.cpu2.fuPool fuPool=system.cpu2.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu2.interrupts interrupts=system.cpu2.interrupts
isa=system.cpu2.isa isa=system.cpu2.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu2.itb itb=system.cpu2.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -250,7 +240,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -277,6 +266,24 @@ wbDepth=1
wbWidth=8 wbWidth=8
workload= workload=
[system.cpu2.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu2.dtb] [system.cpu2.dtb]
type=AlphaTLB type=AlphaTLB
size=64 size=64
@ -574,7 +581,7 @@ table_size=65536
[system.disk0.image.child] [system.disk0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true read_only=true
[system.disk2] [system.disk2]
@ -594,7 +601,7 @@ table_size=65536
[system.disk2.image.child] [system.disk2.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true read_only=true
[system.intrctrl] [system.intrctrl]
@ -719,7 +726,7 @@ system=system
[system.simple_disk.disk] [system.simple_disk.disk]
type=RawDiskImage type=RawDiskImage
image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true read_only=true
[system.terminal] [system.terminal]

234
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 11 2012 16:31:37 gem5 compiled Jan 23 2013 13:29:14
gem5 started Dec 11 2012 16:31:53 gem5 started Jan 23 2013 13:29:38
gem5 executing on e103721-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Switching CPUs... Switching CPUs...
@ -54,163 +56,166 @@ Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 10452679000. Starting simulation... info: Entering event queue @ 10452679000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 10452683500. Starting simulation... info: Entering event queue @ 10452682000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 11452683500. Starting simulation... info: Entering event queue @ 11452682000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 12452683500. Starting simulation... info: Entering event queue @ 12452682000. Starting simulation...
info: Entering event queue @ 12452693500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 12452684500. Starting simulation... info: Entering event queue @ 12452696000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 13452684500. Starting simulation... info: Entering event queue @ 13452696000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 13452690000. Starting simulation... info: Entering event queue @ 13452709500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 14452690000. Starting simulation... info: Entering event queue @ 14452709500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 15452690000. Starting simulation... info: Entering event queue @ 15452709500. Starting simulation...
info: Entering event queue @ 15452713500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 15452691000. Starting simulation... info: Entering event queue @ 15452714500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 16452691000. Starting simulation... info: Entering event queue @ 16452714500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 16452704500. Starting simulation... info: Entering event queue @ 16452717000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 17452704500. Starting simulation... info: Entering event queue @ 17452717000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 18452704500. Starting simulation... info: Entering event queue @ 18452717000. Starting simulation...
info: Entering event queue @ 18452728500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 18452705500. Starting simulation... info: Entering event queue @ 18452732000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 19452705500. Starting simulation... info: Entering event queue @ 19452732000. Starting simulation...
info: Entering event queue @ 19452711000. Starting simulation... info: Entering event queue @ 19452741000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 19452715500. Starting simulation... info: Entering event queue @ 19452745500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 20452715500. Starting simulation... info: Entering event queue @ 20452745500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 21452715500. Starting simulation... info: Entering event queue @ 21452745500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 21452716000. Starting simulation... info: Entering event queue @ 21452746000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 22452716000. Starting simulation... info: Entering event queue @ 22452746000. Starting simulation...
info: Entering event queue @ 22452727500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 22452733000. Starting simulation... info: Entering event queue @ 22452748000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 23452733000. Starting simulation... info: Entering event queue @ 23452748000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 24452733000. Starting simulation... info: Entering event queue @ 24452748000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 24452734000. Starting simulation... info: Entering event queue @ 24452750000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 25452734000. Starting simulation... info: Entering event queue @ 25452750000. Starting simulation...
info: Entering event queue @ 25452773000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 25452745500. Starting simulation... info: Entering event queue @ 25452778500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 26452745500. Starting simulation... info: Entering event queue @ 26452778500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 27452745500. Starting simulation... info: Entering event queue @ 27452778500. Starting simulation...
info: Entering event queue @ 27452782500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 27452746500. Starting simulation... info: Entering event queue @ 27452786000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 28452746500. Starting simulation... info: Entering event queue @ 28452786000. Starting simulation...
info: Entering event queue @ 28452758500. Starting simulation... info: Entering event queue @ 28452802500. Starting simulation...
info: Entering event queue @ 28452769000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 28452773500. Starting simulation... info: Entering event queue @ 28452808000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 29452773500. Starting simulation... info: Entering event queue @ 29452808000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 30452773500. Starting simulation... info: Entering event queue @ 30452808000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 30452992500. Starting simulation... info: Entering event queue @ 30452820500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 31452992500. Starting simulation... info: Entering event queue @ 31452820500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 31452995500. Starting simulation... info: Entering event queue @ 31452823500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 32452995500. Starting simulation... info: Entering event queue @ 32452823500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 33452995500. Starting simulation... info: Entering event queue @ 33452823500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 33452996500. Starting simulation... info: Entering event queue @ 33452824500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 34452996500. Starting simulation... info: Entering event queue @ 34452824500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 34452999500. Starting simulation... info: Entering event queue @ 34452827500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 35452999500. Starting simulation... info: Entering event queue @ 35452827500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 36452999500. Starting simulation... info: Entering event queue @ 36452827500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 36453000500. Starting simulation... info: Entering event queue @ 36452828500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 37453000500. Starting simulation... info: Entering event queue @ 37452828500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 37453003500. Starting simulation... info: Entering event queue @ 37452831500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 38453003500. Starting simulation... info: Entering event queue @ 38452831500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 39453003500. Starting simulation... info: Entering event queue @ 39452831500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 39453004500. Starting simulation... info: Entering event queue @ 39452832500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 40453004500. Starting simulation... info: Entering event queue @ 40452832500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 40453007500. Starting simulation... info: Entering event queue @ 40452835500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 41453007500. Starting simulation... info: Entering event queue @ 41452835500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 42453007500. Starting simulation... info: Entering event queue @ 42452835500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 42453008500. Starting simulation... info: Entering event queue @ 42452836500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 43453008500. Starting simulation... info: Entering event queue @ 43452836500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 43945335500. Starting simulation... info: Entering event queue @ 43945335500. Starting simulation...
Switching CPUs... Switching CPUs...
@ -1083,18 +1088,18 @@ Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 304757835500. Starting simulation... info: Entering event queue @ 304757835500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 304758059500. Starting simulation... info: Entering event queue @ 304758051500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 305758059500. Starting simulation... info: Entering event queue @ 305758051500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
switching cpus switching cpus
info: Entering event queue @ 306758059500. Starting simulation... info: Entering event queue @ 306758051500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 307758059500. Starting simulation... info: Entering event queue @ 307758051500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 308593773000. Starting simulation... info: Entering event queue @ 308593773000. Starting simulation...
Switching CPUs... Switching CPUs...
@ -2151,18 +2156,18 @@ Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 624093773500. Starting simulation... info: Entering event queue @ 624093773500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 624216549000. Starting simulation... info: Entering event queue @ 624218766000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 625216549000. Starting simulation... info: Entering event queue @ 625218766000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
switching cpus switching cpus
info: Entering event queue @ 626216549000. Starting simulation... info: Entering event queue @ 626218766000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 627216549000. Starting simulation... info: Entering event queue @ 627218766000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 627929709000. Starting simulation... info: Entering event queue @ 627929709000. Starting simulation...
Switching CPUs... Switching CPUs...
@ -3931,49 +3936,49 @@ Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 1157273460500. Starting simulation... info: Entering event queue @ 1157273460500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1157273461500. Starting simulation... info: Entering event queue @ 1157273461000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1158273461500. Starting simulation... info: Entering event queue @ 1158273461000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1159361690000. Starting simulation... info: Entering event queue @ 1159361004000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1160361690000. Starting simulation... info: Entering event queue @ 1160361004000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
switching cpus switching cpus
info: Entering event queue @ 1161361690000. Starting simulation... info: Entering event queue @ 1161361004000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1162361690000. Starting simulation... info: Entering event queue @ 1162361004000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1162361693000. Starting simulation... info: Entering event queue @ 1162361007000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1163361693000. Starting simulation... info: Entering event queue @ 1163361007000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
switching cpus switching cpus
info: Entering event queue @ 1164361693000. Starting simulation... info: Entering event queue @ 1164361007000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1165361693000. Starting simulation... info: Entering event queue @ 1165361007000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1165361696000. Starting simulation... info: Entering event queue @ 1165361010000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1166361696000. Starting simulation... info: Entering event queue @ 1166361010000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
switching cpus switching cpus
info: Entering event queue @ 1167361696000. Starting simulation... info: Entering event queue @ 1167361010000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1168361696000. Starting simulation... info: Entering event queue @ 1168361010000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1168945335500. Starting simulation... info: Entering event queue @ 1168945335500. Starting simulation...
Switching CPUs... Switching CPUs...
@ -5934,12 +5939,11 @@ switching cpus
info: Entering event queue @ 1755882835500. Starting simulation... info: Entering event queue @ 1755882835500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 1756882835500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1756882836500. Starting simulation... info: Entering event queue @ 1756882835500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1757882836500. Starting simulation... info: Entering event queue @ 1757882835500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1758789085500. Starting simulation... info: Entering event queue @ 1758789085500. Starting simulation...
Switching CPUs... Switching CPUs...
@ -5976,10 +5980,10 @@ Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 1768601585500. Starting simulation... info: Entering event queue @ 1768601585500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1768601586500. Starting simulation... info: Entering event queue @ 1768601735500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1769601586500. Starting simulation... info: Entering event queue @ 1769601735500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1770507835500. Starting simulation... info: Entering event queue @ 1770507835500. Starting simulation...
Switching CPUs... Switching CPUs...
@ -6007,18 +6011,18 @@ Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1777414085500. Starting simulation... info: Entering event queue @ 1777414085500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1777414489000. Starting simulation... info: Entering event queue @ 1777414674000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1778414489000. Starting simulation... info: Entering event queue @ 1778414674000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
switching cpus switching cpus
info: Entering event queue @ 1779414489000. Starting simulation... info: Entering event queue @ 1779414674000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1780414489000. Starting simulation... info: Entering event queue @ 1780414674000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1781250023000. Starting simulation... info: Entering event queue @ 1781250023000. Starting simulation...
Switching CPUs... Switching CPUs...
@ -6154,33 +6158,32 @@ Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1819406274000. Starting simulation... info: Entering event queue @ 1819406274000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1819406280500. Starting simulation... info: Entering event queue @ 1819406403500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1820406280500. Starting simulation... info: Entering event queue @ 1820406403500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 1821406280500. Starting simulation... info: Entering event queue @ 1821406403500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1821406281500. Starting simulation... info: Entering event queue @ 1821406404500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1822406281500. Starting simulation... info: Entering event queue @ 1822406404500. Starting simulation...
info: Entering event queue @ 1822406288500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1822406293000. Starting simulation... info: Entering event queue @ 1822406407500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1823406293000. Starting simulation... info: Entering event queue @ 1823406407500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
switching cpus switching cpus
info: Entering event queue @ 1824406293000. Starting simulation... info: Entering event queue @ 1824406407500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1825406293000. Starting simulation... info: Entering event queue @ 1825406407500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1826171898000. Starting simulation... info: Entering event queue @ 1826171898000. Starting simulation...
Switching CPUs... Switching CPUs...
@ -6194,22 +6197,21 @@ info: Entering event queue @ 1828171898000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1829171898000. Starting simulation... info: Entering event queue @ 1829171898000. Starting simulation...
info: Entering event queue @ 1829171911500. Starting simulation... info: Entering event queue @ 1829171913500. Starting simulation...
info: Entering event queue @ 1829171916500. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1829171921000. Starting simulation... info: Entering event queue @ 1829171918000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1830171921000. Starting simulation... info: Entering event queue @ 1830171918000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 1831171921000. Starting simulation... info: Entering event queue @ 1831171918000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1831171922000. Starting simulation... info: Entering event queue @ 1831171920000. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1832171922000. Starting simulation... info: Entering event queue @ 1832171920000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1833007835500. Starting simulation... info: Entering event queue @ 1833007835500. Starting simulation...
Switching CPUs... Switching CPUs...
@ -6232,14 +6234,16 @@ info: Entering event queue @ 1837914085500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: DerivO3CPU Next CPU: DerivO3CPU
info: Entering event queue @ 1838914085500. Starting simulation... info: Entering event queue @ 1838914085500. Starting simulation...
info: Entering event queue @ 1838914092000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1838914086500. Starting simulation... info: Entering event queue @ 1838914095500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: AtomicSimpleCPU Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1839914086500. Starting simulation... info: Entering event queue @ 1839914095500. Starting simulation...
info: Entering event queue @ 1839914105000. Starting simulation...
switching cpus switching cpus
info: Entering event queue @ 1839914091000. Starting simulation... info: Entering event queue @ 1839914109500. Starting simulation...
Switching CPUs... Switching CPUs...
Next CPU: TimingSimpleCPU Next CPU: TimingSimpleCPU
switching cpus switching cpus
info: Entering event queue @ 1840914091000. Starting simulation... info: Entering event queue @ 1840914109500. Starting simulation...

27
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.841687 # Nu
sim_ticks 1841687115500 # Number of ticks simulated sim_ticks 1841687115500 # Number of ticks simulated
final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 299654 # Simulator instruction rate (inst/s) host_inst_rate 216690 # Simulator instruction rate (inst/s)
host_op_rate 299654 # Simulator op (including micro ops) rate (op/s) host_op_rate 216690 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 8001020229 # Simulator tick rate (ticks/s) host_tick_rate 5785819991 # Simulator tick rate (ticks/s)
host_mem_usage 317816 # Number of bytes of host memory used host_mem_usage 360768 # Number of bytes of host memory used
host_seconds 230.18 # Real time elapsed on the host host_seconds 318.31 # Real time elapsed on the host
sim_insts 68974794 # Number of instructions simulated sim_insts 68974794 # Number of instructions simulated
sim_ops 68974794 # Number of ops (including micro ops) simulated sim_ops 68974794 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory
@ -1229,6 +1229,15 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed system.cpu1.kern.swap_context 0 # number of times the context was actually changed
system.cpu2.branchPred.lookups 8367198 # Number of BP lookups
system.cpu2.branchPred.condPredicted 7675066 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 129021 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 6898028 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 5713360 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 82.825990 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 286292 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 15213 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_acv 0 # ITB acv
@ -1264,14 +1273,6 @@ system.cpu2.itb.data_accesses 0 # DT
system.cpu2.numCycles 30553382 # number of cpu cycles simulated system.cpu2.numCycles 30553382 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.BPredUnit.lookups 8367198 # Number of BP lookups
system.cpu2.BPredUnit.condPredicted 7675066 # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect 129021 # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups 6898028 # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits 5713360 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS 286292 # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect 15213 # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered

44
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256 atags_addr=256
boot_loader=/gem5/dist/binaries/boot.arm boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000 clock=1000
dtb_filename= dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504 flags_addr=268435504
gic_cpu_addr=520093952 gic_cpu_addr=520093952
init_param=0 init_param=0
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem memories=system.realview.nvmem system.physmem
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
readfile=tests/halt.sh readfile=tests/halt.sh
@ -65,27 +65,23 @@ table_size=65536
[system.cf0.image.child] [system.cf0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-arm-ael.img image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true read_only=true
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=system.cpu.checker checker=system.cpu.checker
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -108,23 +104,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -136,7 +124,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -165,9 +152,28 @@ workload=
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.checker] [system.cpu.checker]
type=O3Checker type=O3Checker
children=dtb isa itb tracer children=dtb isa itb tracer
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0

32
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
View file

@ -10,23 +10,23 @@ warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr icimvau' unimplemented
warn: 5947838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 warn: 5659150500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
warn: 5955222500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 warn: 5667223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
warn: 5964126500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 warn: 5701468500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
warn: 6000836500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 warn: 5716197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
warn: 6016396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: 6234360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported warn: LCD dual screen mode not supported
warn: 51807341500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: 51492621000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr bpiallis' unimplemented
warn: 2473965329500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 warn: 2473679746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
warn: 2487749656500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 warn: 2487454314500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2488961741500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 warn: 2488664454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
warn: 2510016165000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 warn: 2509713816500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2510533208500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 warn: 2510230497500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
warn: 2516263747000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 warn: 2515951942000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
warn: 2516773890500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 warn: 2516461974500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
warn: 2517336143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 warn: 2517022987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
warn: 2517337246000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 warn: 2517024145000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
warn: 2517887293500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 warn: 2517574344000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
hack: be nice to actually delete the event here hack: be nice to actually delete the event here

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:17:24 gem5 compiled Jan 23 2013 19:43:25
gem5 started Jan 5 2013 01:50:21 gem5 started Jan 23 2013 21:57:44
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000 info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2523517846500 because m5_exit instruction encountered Exiting @ tick 2523204701000 because m5_exit instruction encountered

27
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.523205 # Nu
sim_ticks 2523204701000 # Number of ticks simulated sim_ticks 2523204701000 # Number of ticks simulated
final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 55288 # Simulator instruction rate (inst/s) host_inst_rate 41110 # Simulator instruction rate (inst/s)
host_op_rate 71140 # Simulator op (including micro ops) rate (op/s) host_op_rate 52896 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2313219719 # Simulator tick rate (ticks/s) host_tick_rate 1720016966 # Simulator tick rate (ticks/s)
host_mem_usage 409988 # Number of bytes of host memory used host_mem_usage 452892 # Number of bytes of host memory used
host_seconds 1090.78 # Real time elapsed on the host host_seconds 1466.97 # Real time elapsed on the host
sim_insts 60306320 # Number of instructions simulated sim_insts 60306320 # Number of instructions simulated
sim_ops 77597310 # Number of ops (including micro ops) simulated sim_ops 77597310 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
@ -225,6 +225,15 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.branchPred.lookups 14400111 # Number of BP lookups
system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 14986991 # DTB read hits system.cpu.checker.dtb.read_hits 14986991 # DTB read hits
@ -315,14 +324,6 @@ system.cpu.itb.accesses 11542101 # DT
system.cpu.numCycles 469830472 # number of cpu cycles simulated system.cpu.numCycles 469830472 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered

78
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256 atags_addr=256
boot_loader=/gem5/dist/binaries/boot.arm boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000 clock=1000
dtb_filename= dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504 flags_addr=268435504
gic_cpu_addr=520093952 gic_cpu_addr=520093952
init_param=0 init_param=0
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem memories=system.realview.nvmem system.physmem
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
readfile=tests/halt.sh readfile=tests/halt.sh
@ -65,27 +65,23 @@ table_size=65536
[system.cf0.image.child] [system.cf0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-arm-ael.img image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true read_only=true
[system.cpu0] [system.cpu0]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb tracer children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu0.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -108,23 +104,15 @@ forwardComSize=5
fuPool=system.cpu0.fuPool fuPool=system.cpu0.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts interrupts=system.cpu0.interrupts
isa=system.cpu0.isa isa=system.cpu0.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu0.itb itb=system.cpu0.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -136,7 +124,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -165,6 +152,24 @@ workload=
dcache_port=system.cpu0.dcache.cpu_side dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu0.dcache] [system.cpu0.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -523,22 +528,18 @@ type=ExeTracer
[system.cpu1] [system.cpu1]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb tracer children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu1.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -561,23 +562,15 @@ forwardComSize=5
fuPool=system.cpu1.fuPool fuPool=system.cpu1.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts interrupts=system.cpu1.interrupts
isa=system.cpu1.isa isa=system.cpu1.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu1.itb itb=system.cpu1.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -589,7 +582,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -618,6 +610,24 @@ workload=
dcache_port=system.cpu1.dcache.cpu_side dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu1.dcache] [system.cpu1.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:17:24 gem5 compiled Jan 23 2013 19:43:25
gem5 started Jan 5 2013 02:00:26 gem5 started Jan 23 2013 22:02:35
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000 info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2603185215000 because m5_exit instruction encountered Exiting @ tick 1092968826500 because m5_exit instruction encountered

44
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.092969 # Nu
sim_ticks 1092968826500 # Number of ticks simulated sim_ticks 1092968826500 # Number of ticks simulated
final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 64747 # Simulator instruction rate (inst/s) host_inst_rate 49884 # Simulator instruction rate (inst/s)
host_op_rate 83356 # Simulator op (including micro ops) rate (op/s) host_op_rate 64220 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1148881552 # Simulator tick rate (ticks/s) host_tick_rate 885142778 # Simulator tick rate (ticks/s)
host_mem_usage 415112 # Number of bytes of host memory used host_mem_usage 458008 # Number of bytes of host memory used
host_seconds 951.33 # Real time elapsed on the host host_seconds 1234.79 # Real time elapsed on the host
sim_insts 61595972 # Number of instructions simulated sim_insts 61595972 # Number of instructions simulated
sim_ops 79298956 # Number of ops (including micro ops) simulated sim_ops 79298956 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
@ -663,6 +663,15 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 6012491 # Number of BP lookups
system.cpu0.branchPred.condPredicted 4585363 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 296577 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 3765620 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 2919015 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 77.517514 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 674578 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 28863 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 8918270 # DTB read hits system.cpu0.dtb.read_hits 8918270 # DTB read hits
@ -708,14 +717,6 @@ system.cpu0.itb.accesses 4231537 # DT
system.cpu0.numCycles 67785734 # number of cpu cycles simulated system.cpu0.numCycles 67785734 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 6012491 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 4585363 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 296577 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 3765620 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 2919015 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 674578 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 28863 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered
@ -1233,6 +1234,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 8781590 # Number of BP lookups
system.cpu1.branchPred.condPredicted 7165099 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 410272 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 5784510 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 4949628 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 85.566937 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 773605 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 42847 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 42721233 # DTB read hits system.cpu1.dtb.read_hits 42721233 # DTB read hits
@ -1278,14 +1288,6 @@ system.cpu1.itb.accesses 7589581 # DT
system.cpu1.numCycles 406854445 # number of cpu cycles simulated system.cpu1.numCycles 406854445 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 8781590 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 7165099 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 410272 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 5784510 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 4949628 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 773605 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 42847 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered

43
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256 atags_addr=256
boot_loader=/gem5/dist/binaries/boot.arm boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000 clock=1000
dtb_filename= dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504 flags_addr=268435504
gic_cpu_addr=520093952 gic_cpu_addr=520093952
init_param=0 init_param=0
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem memories=system.realview.nvmem system.physmem
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
readfile=tests/halt.sh readfile=tests/halt.sh
@ -65,27 +65,23 @@ table_size=65536
[system.cf0.image.child] [system.cf0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-arm-ael.img image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true read_only=true
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -108,23 +104,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -136,7 +124,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -165,6 +152,24 @@ workload=
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615

12
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:17:24 gem5 compiled Jan 23 2013 19:43:25
gem5 started Jan 5 2013 01:42:51 gem5 started Jan 23 2013 21:42:21
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000 info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2523517846500 because m5_exit instruction encountered Exiting @ tick 2523204701000 because m5_exit instruction encountered

27
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.523205 # Nu
sim_ticks 2523204701000 # Number of ticks simulated sim_ticks 2523204701000 # Number of ticks simulated
final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 64094 # Simulator instruction rate (inst/s) host_inst_rate 50114 # Simulator instruction rate (inst/s)
host_op_rate 82471 # Simulator op (including micro ops) rate (op/s) host_op_rate 64483 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2681679652 # Simulator tick rate (ticks/s) host_tick_rate 2096764175 # Simulator tick rate (ticks/s)
host_mem_usage 409992 # Number of bytes of host memory used host_mem_usage 452888 # Number of bytes of host memory used
host_seconds 940.90 # Real time elapsed on the host host_seconds 1203.38 # Real time elapsed on the host
sim_insts 60306320 # Number of instructions simulated sim_insts 60306320 # Number of instructions simulated
sim_ops 77597310 # Number of ops (including micro ops) simulated sim_ops 77597310 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
@ -225,6 +225,15 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.branchPred.lookups 14400111 # Number of BP lookups
system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 51212683 # DTB read hits system.cpu.dtb.read_hits 51212683 # DTB read hits
@ -270,14 +279,6 @@ system.cpu.itb.accesses 11542101 # DT
system.cpu.numCycles 469830472 # number of cpu cycles simulated system.cpu.numCycles 469830472 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered

45
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256 atags_addr=256
boot_loader=/gem5/dist/binaries/boot.arm boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000 clock=1000
dtb_filename= dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504 flags_addr=268435504
gic_cpu_addr=520093952 gic_cpu_addr=520093952
init_param=0 init_param=0
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=atomic mem_mode=atomic
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.realview.nvmem system.physmem memories=system.physmem system.realview.nvmem
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
readfile=tests/halt.sh readfile=tests/halt.sh
@ -65,12 +65,13 @@ table_size=65536
[system.cf0.image.child] [system.cf0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-arm-ael.img image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true read_only=true
[system.cpu0] [system.cpu0]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer children=dcache dtb icache interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
@ -197,6 +198,7 @@ type=ExeTracer
[system.cpu1] [system.cpu1]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dtb interrupts isa itb tracer children=dtb interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
@ -270,22 +272,18 @@ type=ExeTracer
[system.cpu2] [system.cpu2]
type=DerivO3CPU type=DerivO3CPU
children=dtb fuPool interrupts isa itb tracer children=branchPred dtb fuPool interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu2.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -308,23 +306,15 @@ forwardComSize=5
fuPool=system.cpu2.fuPool fuPool=system.cpu2.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu2.interrupts interrupts=system.cpu2.interrupts
isa=system.cpu2.isa isa=system.cpu2.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu2.itb itb=system.cpu2.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -336,7 +326,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -363,6 +352,24 @@ wbDepth=1
wbWidth=8 wbWidth=8
workload= workload=
[system.cpu2.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu2.dtb] [system.cpu2.dtb]
type=ArmTLB type=ArmTLB
children=walker children=walker

3240
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
View file

File diff suppressed because it is too large Load diff

27
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.401290 # Nu
sim_ticks 2401290348000 # Number of ticks simulated sim_ticks 2401290348000 # Number of ticks simulated
final_tick 2401290348000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2401290348000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 196762 # Simulator instruction rate (inst/s) host_inst_rate 145439 # Simulator instruction rate (inst/s)
host_op_rate 252717 # Simulator op (including micro ops) rate (op/s) host_op_rate 186799 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7831753482 # Simulator tick rate (ticks/s) host_tick_rate 5788935854 # Simulator tick rate (ticks/s)
host_mem_usage 401668 # Number of bytes of host memory used host_mem_usage 444568 # Number of bytes of host memory used
host_seconds 306.61 # Real time elapsed on the host host_seconds 414.81 # Real time elapsed on the host
sim_insts 60329082 # Number of instructions simulated sim_insts 60329082 # Number of instructions simulated
sim_ops 77485321 # Number of ops (including micro ops) simulated sim_ops 77485321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
@ -1192,6 +1192,15 @@ system.cpu1.not_idle_fraction 1.049701 # Pe
system.cpu1.idle_fraction -0.049701 # Percentage of idle cycles system.cpu1.idle_fraction -0.049701 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 4714679 # Number of BP lookups
system.cpu2.branchPred.condPredicted 3830081 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 228509 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 3129435 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 2502665 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 79.971784 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 416919 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 22256 # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 11094758 # DTB read hits system.cpu2.dtb.read_hits 11094758 # DTB read hits
@ -1237,14 +1246,6 @@ system.cpu2.itb.accesses 3976256 # DT
system.cpu2.numCycles 88220053 # number of cpu cycles simulated system.cpu2.numCycles 88220053 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.BPredUnit.lookups 4714679 # Number of BP lookups
system.cpu2.BPredUnit.condPredicted 3830081 # Number of conditional branches predicted
system.cpu2.BPredUnit.condIncorrect 228509 # Number of conditional branches incorrect
system.cpu2.BPredUnit.BTBLookups 3129435 # Number of BTB lookups
system.cpu2.BPredUnit.BTBHits 2502665 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.BPredUnit.usedRAS 416919 # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect 22256 # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles 9444272 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.icacheStallCycles 9444272 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 32171210 # Number of instructions fetch has processed system.cpu2.fetch.Insts 32171210 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 4714679 # Number of branches that fetch encountered system.cpu2.fetch.Branches 4714679 # Number of branches that fetch encountered

78
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256 atags_addr=256
boot_loader=/gem5/dist/binaries/boot.arm boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000 clock=1000
dtb_filename= dtb_filename=
@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504 flags_addr=268435504
gic_cpu_addr=520093952 gic_cpu_addr=520093952
init_param=0 init_param=0
kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727
memories=system.realview.nvmem system.physmem memories=system.physmem system.realview.nvmem
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
readfile=tests/halt.sh readfile=tests/halt.sh
@ -65,27 +65,23 @@ table_size=65536
[system.cf0.image.child] [system.cf0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-arm-ael.img image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true read_only=true
[system.cpu0] [system.cpu0]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb tracer children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu0.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -108,23 +104,15 @@ forwardComSize=5
fuPool=system.cpu0.fuPool fuPool=system.cpu0.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu0.interrupts interrupts=system.cpu0.interrupts
isa=system.cpu0.isa isa=system.cpu0.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu0.itb itb=system.cpu0.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -136,7 +124,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -165,6 +152,24 @@ workload=
dcache_port=system.cpu0.dcache.cpu_side dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu0.dcache] [system.cpu0.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -523,22 +528,18 @@ type=ExeTracer
[system.cpu1] [system.cpu1]
type=DerivO3CPU type=DerivO3CPU
children=dtb fuPool interrupts isa itb tracer children=branchPred dtb fuPool interrupts isa itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu1.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -561,23 +562,15 @@ forwardComSize=5
fuPool=system.cpu1.fuPool fuPool=system.cpu1.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu1.interrupts interrupts=system.cpu1.interrupts
isa=system.cpu1.isa isa=system.cpu1.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu1.itb itb=system.cpu1.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -589,7 +582,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -616,6 +608,24 @@ wbDepth=1
wbWidth=8 wbWidth=8
workload= workload=
[system.cpu1.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu1.dtb] [system.cpu1.dtb]
type=ArmTLB type=ArmTLB
children=walker children=walker

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
View file

@ -14,5 +14,3 @@ warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr bpiallis' unimplemented
warn: User mode does not have SPSR
warn: User mode does not have SPSR

2157
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
View file

File diff suppressed because it is too large Load diff

44
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.540276 # Nu
sim_ticks 2540275734000 # Number of ticks simulated sim_ticks 2540275734000 # Number of ticks simulated
final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 63914 # Simulator instruction rate (inst/s) host_inst_rate 50621 # Simulator instruction rate (inst/s)
host_op_rate 82240 # Simulator op (including micro ops) rate (op/s) host_op_rate 65136 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2691970222 # Simulator tick rate (ticks/s) host_tick_rate 2132095179 # Simulator tick rate (ticks/s)
host_mem_usage 413060 # Number of bytes of host memory used host_mem_usage 455960 # Number of bytes of host memory used
host_seconds 943.65 # Real time elapsed on the host host_seconds 1191.45 # Real time elapsed on the host
sim_insts 60312498 # Number of instructions simulated sim_insts 60312498 # Number of instructions simulated
sim_ops 77605759 # Number of ops (including micro ops) simulated sim_ops 77605759 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
@ -685,6 +685,15 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 6894641 # Number of BP lookups
system.cpu0.branchPred.condPredicted 5490275 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 340467 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4496048 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 3641169 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 80.985990 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 672237 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 35025 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 25321176 # DTB read hits system.cpu0.dtb.read_hits 25321176 # DTB read hits
@ -730,14 +739,6 @@ system.cpu0.itb.accesses 5406787 # DT
system.cpu0.numCycles 232916834 # number of cpu cycles simulated system.cpu0.numCycles 232916834 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 6894641 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 5490275 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 340467 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 4496048 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 3641169 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 672237 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 35025 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered
@ -1372,6 +1373,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 7461261 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5924878 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 387688 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4864845 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3916001 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 80.495905 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 732677 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 39651 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 25842433 # DTB read hits system.cpu1.dtb.read_hits 25842433 # DTB read hits
@ -1417,14 +1427,6 @@ system.cpu1.itb.accesses 5870588 # DT
system.cpu1.numCycles 238328292 # number of cpu cycles simulated system.cpu1.numCycles 238328292 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 7461261 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 5924878 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 387688 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 4864845 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 3916001 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 732677 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 39651 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256 atags_addr=256
boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000 clock=1000
dtb_filename= dtb_filename=
@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false
flags_addr=268435504 flags_addr=268435504
gic_cpu_addr=520093952 gic_cpu_addr=520093952
init_param=0 init_param=0
kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455 load_addr_mask=268435455
machine_type=RealView_PBX machine_type=RealView_PBX
mem_mode=timing mem_mode=timing
@ -27,8 +27,6 @@ mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem memories=system.physmem system.realview.nvmem
multi_proc=true multi_proc=true
num_work_ids=16 num_work_ids=16
panic_on_oops=true
panic_on_panic=true
readfile=tests/halt.sh readfile=tests/halt.sh
symbolfile= symbolfile=
work_begin_ckpt_count=0 work_begin_ckpt_count=0
@ -67,12 +65,13 @@ table_size=65536
[system.cf0.image.child] [system.cf0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true read_only=true
[system.cpu0] [system.cpu0]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer children=dcache dtb icache interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
@ -195,6 +194,7 @@ type=ExeTracer
[system.cpu1] [system.cpu1]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dtb interrupts isa itb tracer children=dtb interrupts isa itb tracer
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
View file

@ -1,12 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 11 2012 16:28:23 gem5 compiled Jan 23 2013 19:43:25
gem5 started Dec 11 2012 16:28:35 gem5 started Jan 23 2013 22:22:22
gem5 executing on e103721-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000 info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Switching CPUs... Switching CPUs...

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.609477 # Nu
sim_ticks 2609476867000 # Number of ticks simulated sim_ticks 2609476867000 # Number of ticks simulated
final_tick 2609476867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2609476867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 293996 # Simulator instruction rate (inst/s) host_inst_rate 397155 # Simulator instruction rate (inst/s)
host_op_rate 374108 # Simulator op (including micro ops) rate (op/s) host_op_rate 505377 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12742678359 # Simulator tick rate (ticks/s) host_tick_rate 17213891867 # Simulator tick rate (ticks/s)
host_mem_usage 397908 # Number of bytes of host memory used host_mem_usage 448796 # Number of bytes of host memory used
host_seconds 204.78 # Real time elapsed on the host host_seconds 151.59 # Real time elapsed on the host
sim_insts 60205243 # Number of instructions simulated sim_insts 60205243 # Number of instructions simulated
sim_ops 76610733 # Number of ops (including micro ops) simulated sim_ops 76610733 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory

41
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -16,7 +16,7 @@ e820_table=system.e820_table
init_param=0 init_param=0
intel_mp_pointer=system.intel_mp_pointer intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table intel_mp_table=system.intel_mp_table
kernel=/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615 load_addr_mask=18446744073709551615
mem_mode=timing mem_mode=timing
mem_ranges=0:134217727 mem_ranges=0:134217727
@ -73,22 +73,18 @@ slave=system.membus.master[1]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer children=branchPred dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -111,23 +107,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -139,7 +127,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -168,6 +155,24 @@ workload=
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -1268,7 +1273,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child] [system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-x86.img image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true read_only=true
[system.pc.south_bridge.ide.disks1] [system.pc.south_bridge.ide.disks1]
@ -1288,7 +1293,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child] [system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage type=RawDiskImage
image_file=/gem5/dist/disks/linux-bigswap2.img image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true read_only=true
[system.pc.south_bridge.int_lines0] [system.pc.south_bridge.int_lines0]

12
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,13 +1,15 @@
Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:20:54 gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 4 2013 23:13:25 gem5 started Jan 23 2013 19:14:30
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5136797077000 because m5_exit instruction encountered Exiting @ tick 5136817990000 because m5_exit instruction encountered

27
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 5.136818 # Nu
sim_ticks 5136817990000 # Number of ticks simulated sim_ticks 5136817990000 # Number of ticks simulated
final_tick 5136817990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 5136817990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 178524 # Simulator instruction rate (inst/s) host_inst_rate 121455 # Simulator instruction rate (inst/s)
host_op_rate 352888 # Simulator op (including micro ops) rate (op/s) host_op_rate 240079 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2247974016 # Simulator tick rate (ticks/s) host_tick_rate 1529355788 # Simulator tick rate (ticks/s)
host_mem_usage 798352 # Number of bytes of host memory used host_mem_usage 804152 # Number of bytes of host memory used
host_seconds 2285.09 # Real time elapsed on the host host_seconds 3358.81 # Real time elapsed on the host
sim_insts 407944006 # Number of instructions simulated sim_insts 407944006 # Number of instructions simulated
sim_ops 806380994 # Number of ops (including micro ops) simulated sim_ops 806380994 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2472512 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 2472512 # Number of bytes read from this memory
@ -308,17 +308,18 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.branchPred.lookups 86252881 # Number of BP lookups
system.cpu.branchPred.condPredicted 86252881 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1115345 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 81384938 # Number of BTB lookups
system.cpu.branchPred.BTBHits 79240101 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 97.364577 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.numCycles 447901761 # number of cpu cycles simulated system.cpu.numCycles 447901761 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 86252881 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 86252881 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1115345 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 81384938 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 79240101 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 27570299 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 27570299 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 426189548 # Number of instructions fetch has processed system.cpu.fetch.Insts 426189548 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86252881 # Number of branches that fetch encountered system.cpu.fetch.Branches 86252881 # Number of branches that fetch encountered

4
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
View file

@ -23,7 +23,7 @@ Built 1 zonelists. Total pages: 30458
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0 Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes) PID hash table entries: 512 (order: 9, 4096 bytes)
time.c: Detected 2000.001 MHz processor. time.c: Detected 2000.008 MHz processor.
Console: colour dummy device 80x25 Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0] console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes) Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@ -39,7 +39,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126] ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts. Using local APIC timer interrupts.
result 7812531 result 7812557
Detected 7.812 MHz APIC timer. Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16 NET: Registered protocol family 16
PCI: Using configuration type 1 PCI: Using configuration type 1

57
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=InOrderCPU type=InOrderCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
activity=0 activity=0
branchPred=system.cpu.branchPred
cachePorts=2 cachePorts=2
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
div16Latency=1 div16Latency=1
div16RepeatRate=1 div16RepeatRate=1
div24Latency=1 div24Latency=1
@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4 fetchBuffSize=4
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1 multLatency=1
multRepeatRate=1 multRepeatRate=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
stageTracing=false stageTracing=false
stageWidth=4 stageWidth=4
switched_out=false
system=system system=system
threadModel=SMT threadModel=SMT
tracer=system.cpu.tracer tracer=system.cpu.tracer
@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -95,21 +101,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -126,21 +127,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -163,21 +159,16 @@ assoc=8
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=20 hit_latency=20
is_top_level=false is_top_level=false
max_miss_count=0 max_miss_count=0
mshrs=20 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20 response_latency=20
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=12 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]
@ -204,7 +195,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

8
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:02:14 gem5 compiled Jan 23 2013 13:29:14
gem5 started Oct 30 2012 11:21:21 gem5 started Jan 23 2013 14:19:12
gem5 executing on u200540-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

27
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.269661 # Nu
sim_ticks 269661304500 # Number of ticks simulated sim_ticks 269661304500 # Number of ticks simulated
final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 125304 # Simulator instruction rate (inst/s) host_inst_rate 98682 # Simulator instruction rate (inst/s)
host_op_rate 125304 # Simulator op (including micro ops) rate (op/s) host_op_rate 98682 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 56142087 # Simulator tick rate (ticks/s) host_tick_rate 44214559 # Simulator tick rate (ticks/s)
host_mem_usage 214336 # Number of bytes of host memory used host_mem_usage 273520 # Number of bytes of host memory used
host_seconds 4803.19 # Real time elapsed on the host host_seconds 6098.93 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
@ -192,6 +192,15 @@ system.physmem.writeRowHits 51 # Nu
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
system.physmem.avgGap 9874807.84 # Average gap between requests system.physmem.avgGap 9874807.84 # Average gap between requests
system.cpu.branchPred.lookups 86405274 # Number of BP lookups
system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups
system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 539322610 # number of cpu cycles simulated system.cpu.numCycles 539322610 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File

57
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1 decodeToFetchDelay=1
decodeToRenameDelay=1 decodeToRenameDelay=1
decodeWidth=8 decodeWidth=8
defer_registration=false
dispatchWidth=8 dispatchWidth=8
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100 smtROBThreshold=100
squashWidth=8 squashWidth=8
store_set_clear_period=250000 store_set_clear_period=250000
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
trapLatency=13 trapLatency=13
@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -132,21 +138,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -426,21 +427,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -463,21 +459,16 @@ assoc=8
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=20 hit_latency=20
is_top_level=false is_top_level=false
max_miss_count=0 max_miss_count=0
mshrs=20 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20 response_latency=20
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=12 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]
@ -504,7 +495,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

8
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 30 2012 11:02:14 gem5 compiled Jan 23 2013 13:29:14
gem5 started Oct 30 2012 11:21:56 gem5 started Jan 23 2013 14:43:44
gem5 executing on u200540-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

27
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.133779 # Nu
sim_ticks 133778696500 # Number of ticks simulated sim_ticks 133778696500 # Number of ticks simulated
final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 208111 # Simulator instruction rate (inst/s) host_inst_rate 160169 # Simulator instruction rate (inst/s)
host_op_rate 208111 # Simulator op (including micro ops) rate (op/s) host_op_rate 160169 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49227708 # Simulator tick rate (ticks/s) host_tick_rate 37887208 # Simulator tick rate (ticks/s)
host_mem_usage 215496 # Number of bytes of host memory used host_mem_usage 273648 # Number of bytes of host memory used
host_seconds 2717.55 # Real time elapsed on the host host_seconds 3530.97 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory
@ -192,6 +192,15 @@ system.physmem.writeRowHits 53 # Nu
system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes
system.physmem.avgGap 4852854.06 # Average gap between requests system.physmem.avgGap 4852854.06 # Average gap between requests
system.cpu.branchPred.lookups 76440222 # Number of BP lookups
system.cpu.branchPred.condPredicted 70864810 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2706098 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 43060392 # Number of BTB lookups
system.cpu.branchPred.BTBHits 41933015 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 97.381870 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1604413 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_acv 0 # ITB acv
@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 267557394 # number of cpu cycles simulated system.cpu.numCycles 267557394 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed
system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered

21
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -42,17 +44,18 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts] [system.cpu.interrupts]
type=AlphaInterrupts type=AlphaInterrupts
[system.cpu.isa]
type=AlphaISA
[system.cpu.itb] [system.cpu.itb]
type=AlphaTLB type=AlphaTLB
size=48 size=48
@ -82,7 +88,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -99,14 +105,15 @@ block_size=64
clock=1000 clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=64 width=8
master=system.physmem.port[0] master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false conf_table_reported=false
file=
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0

8
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11 gem5 compiled Jan 23 2013 13:29:14
gem5 started Jun 4 2012 14:03:38 gem5 started Jan 23 2013 13:29:25
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

10
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.300931 # Nu
sim_ticks 300930958000 # Number of ticks simulated sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3871430 # Simulator instruction rate (inst/s) host_inst_rate 2641824 # Simulator instruction rate (inst/s)
host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s) host_op_rate 2641824 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1935730316 # Simulator tick rate (ticks/s) host_tick_rate 1320922836 # Simulator tick rate (ticks/s)
host_mem_usage 206040 # Number of bytes of host memory used host_mem_usage 264040 # Number of bytes of host memory used
host_seconds 155.46 # Real time elapsed on the host host_seconds 227.82 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory

68
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
workload=system.cpu.workload workload=system.cpu.workload
@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
is_top_level=true is_top_level=true
latency=1000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
is_top_level=true is_top_level=true
latency=1000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts] [system.cpu.interrupts]
type=AlphaInterrupts type=AlphaInterrupts
[system.cpu.isa]
type=AlphaISA
[system.cpu.itb] [system.cpu.itb]
type=AlphaTLB type=AlphaTLB
size=48 size=48
@ -120,23 +120,20 @@ size=48
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=8
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=20
is_top_level=false is_top_level=false
latency=10000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=20
repl=Null
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]
@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus] [system.cpu.toL2Bus]
type=CoherentBus type=CoherentBus
block_size=64 block_size=64
clock=1000 clock=500
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=8 width=32
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -158,12 +155,12 @@ type=ExeTracer
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess
cmd=gzip input.log 1 cmd=gzip input.log 1
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
egid=100 egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -181,13 +178,14 @@ clock=1000
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=8 width=8
master=system.physmem.port[0] master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false conf_table_reported=false
file=
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0

12
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -1,10 +1,12 @@
Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56 gem5 compiled Jan 23 2013 13:29:14
gem5 started Jul 2 2012 09:11:02 gem5 started Jan 23 2013 14:50:54
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page. info: Increasing stack size by one page.
@ -39,4 +41,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 764109115000 because target called exit() Exiting @ tick 762403375000 because target called exit()

210
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.762403 # Nu
sim_ticks 762403375000 # Number of ticks simulated sim_ticks 762403375000 # Number of ticks simulated
final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2059312 # Simulator instruction rate (inst/s) host_inst_rate 1151537 # Simulator instruction rate (inst/s)
host_op_rate 2059312 # Simulator op (including micro ops) rate (op/s) host_op_rate 1151537 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2608636387 # Simulator tick rate (ticks/s) host_tick_rate 1458711281 # Simulator tick rate (ticks/s)
host_mem_usage 217100 # Number of bytes of host memory used host_mem_usage 272496 # Number of bytes of host memory used
host_seconds 292.26 # Real time elapsed on the host host_seconds 522.66 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
@ -167,106 +167,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52367.295597
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1028 # number of replacements system.cpu.l2cache.replacements 1028 # number of replacements
system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks.
@ -405,5 +305,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.277139
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

37
tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -522,7 +527,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/gem5/dist/cpu2000/binaries/arm/linux/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

10
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:17:24 gem5 compiled Jan 23 2013 19:43:25
gem5 started Jan 4 2013 23:34:09 gem5 started Jan 23 2013 19:48:55
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -38,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 164568389500 because target called exit() Exiting @ tick 164543008000 because target called exit()

27
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.164543 # Nu
sim_ticks 164543008000 # Number of ticks simulated sim_ticks 164543008000 # Number of ticks simulated
final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 153982 # Simulator instruction rate (inst/s) host_inst_rate 116480 # Simulator instruction rate (inst/s)
host_op_rate 162709 # Simulator op (including micro ops) rate (op/s) host_op_rate 123082 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44446364 # Simulator tick rate (ticks/s) host_tick_rate 33621508 # Simulator tick rate (ticks/s)
host_mem_usage 244392 # Number of bytes of host memory used host_mem_usage 289348 # Number of bytes of host memory used
host_seconds 3702.06 # Real time elapsed on the host host_seconds 4893.98 # Real time elapsed on the host
sim_insts 570051585 # Number of instructions simulated sim_insts 570051585 # Number of instructions simulated
sim_ops 602359791 # Number of ops (including micro ops) simulated sim_ops 602359791 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory
@ -192,6 +192,15 @@ system.physmem.writeRowHits 1096 # Nu
system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes
system.physmem.avgGap 5511958.73 # Average gap between requests system.physmem.avgGap 5511958.73 # Average gap between requests
system.cpu.branchPred.lookups 85130885 # Number of BP lookups
system.cpu.branchPred.condPredicted 79914937 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2339051 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 47115734 # Number of BTB lookups
system.cpu.branchPred.BTBHits 46860934 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.459204 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1427305 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 879 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
@ -238,14 +247,6 @@ system.cpu.workload.num_syscalls 48 # Nu
system.cpu.numCycles 329086017 # number of cpu cycles simulated system.cpu.numCycles 329086017 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 85130885 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 79914937 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2339051 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 47115734 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 46860934 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1427305 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 879 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered

34
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
View file

@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1 clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -43,6 +44,7 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -53,6 +55,7 @@ profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker] [system.cpu.dtb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.membus.slave[4] port=system.membus.slave[4]
@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts] [system.cpu.interrupts]
type=ArmInterrupts type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb] [system.cpu.itb]
type=ArmTLB type=ArmTLB
children=walker children=walker
@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker] [system.cpu.itb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.membus.slave[3] port=system.membus.slave[3]
@ -100,7 +120,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clock=1 clock=1000
conf_table_reported=false conf_table_reported=false
in_addr_map=true in_addr_map=true
latency=30000 latency=30000

8
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simout
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00 gem5 compiled Jan 23 2013 19:43:25
gem5 started Sep 21 2012 12:41:05 gem5 started Jan 23 2013 19:49:37
gem5 executing on u200540-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

10
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu
sim_ticks 301191365000 # Number of ticks simulated sim_ticks 301191365000 # Number of ticks simulated
final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2514683 # Simulator instruction rate (inst/s) host_inst_rate 1714897 # Simulator instruction rate (inst/s)
host_op_rate 2657205 # Simulator op (including micro ops) rate (op/s) host_op_rate 1812090 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1328652667 # Simulator tick rate (ticks/s) host_tick_rate 906079333 # Simulator tick rate (ticks/s)
host_mem_usage 218896 # Number of bytes of host memory used host_mem_usage 278712 # Number of bytes of host memory used
host_seconds 226.69 # Real time elapsed on the host host_seconds 332.41 # Real time elapsed on the host
sim_insts 570051636 # Number of instructions simulated sim_insts 570051636 # Number of instructions simulated
sim_ops 602359842 # Number of ops (including micro ops) simulated sim_ops 602359842 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory

87
tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
View file

@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1 clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1 numThreads=1
profile=0 profile=0
progress_interval=0 progress_interval=0
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
workload=system.cpu.workload workload=system.cpu.workload
@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=1 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
hit_latency=1000
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
response_latency=1000
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker] [system.cpu.dtb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.cpu.toL2Bus.slave[3] port=system.cpu.toL2Bus.slave[3]
@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=1 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
hit_latency=1000
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
response_latency=1000
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts] [system.cpu.interrupts]
type=ArmInterrupts type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb] [system.cpu.itb]
type=ArmTLB type=ArmTLB
children=walker children=walker
@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker] [system.cpu.itb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.cpu.toL2Bus.slave[2] port=system.cpu.toL2Bus.slave[2]
@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=8
block_size=64 block_size=64
clock=1 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=20
hit_latency=10000
is_top_level=false is_top_level=false
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=20
repl=Null
response_latency=10000
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]
@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus] [system.cpu.toL2Bus]
type=CoherentBus type=CoherentBus
block_size=64 block_size=64
clock=1000 clock=500
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=8 width=32
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -187,7 +192,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clock=1 clock=1000
conf_table_reported=false conf_table_reported=false
in_addr_map=true in_addr_map=true
latency=30000 latency=30000

10
tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00 gem5 compiled Jan 23 2013 19:43:25
gem5 started Sep 21 2012 12:37:42 gem5 started Jan 23 2013 19:54:17
gem5 executing on u200540-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -38,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 795270546000 because target called exit() Exiting @ tick 793670137000 because target called exit()

226
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.793670 # Nu
sim_ticks 793670137000 # Number of ticks simulated sim_ticks 793670137000 # Number of ticks simulated
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 897110 # Simulator instruction rate (inst/s) host_inst_rate 904187 # Simulator instruction rate (inst/s)
host_op_rate 947381 # Simulator op (including micro ops) rate (op/s) host_op_rate 954854 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1252348386 # Simulator tick rate (ticks/s) host_tick_rate 1262227313 # Simulator tick rate (ticks/s)
host_mem_usage 231392 # Number of bytes of host memory used host_mem_usage 287296 # Number of bytes of host memory used
host_seconds 633.75 # Real time elapsed on the host host_seconds 628.79 # Real time elapsed on the host
sim_insts 568539335 # Number of instructions simulated sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated sim_ops 600398272 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
system.cpu.dcache.writebacks::total 418626 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2512 # number of replacements system.cpu.l2cache.replacements 2512 # number of replacements
system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks.
@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
system.cpu.dcache.writebacks::total 418626 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

37
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -490,7 +495,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

8
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:16:54 gem5 compiled Jan 23 2013 15:49:24
gem5 started Jan 4 2013 22:00:02 gem5 started Jan 23 2013 15:52:06
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

27
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.387280 # Nu
sim_ticks 387279743500 # Number of ticks simulated sim_ticks 387279743500 # Number of ticks simulated
final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 70741 # Simulator instruction rate (inst/s) host_inst_rate 131929 # Simulator instruction rate (inst/s)
host_op_rate 70964 # Simulator op (including micro ops) rate (op/s) host_op_rate 132344 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19552386 # Simulator tick rate (ticks/s) host_tick_rate 36464205 # Simulator tick rate (ticks/s)
host_mem_usage 225936 # Number of bytes of host memory used host_mem_usage 283820 # Number of bytes of host memory used
host_seconds 19807.29 # Real time elapsed on the host host_seconds 10620.82 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory
@ -192,18 +192,19 @@ system.physmem.writeRowHits 1098 # Nu
system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes
system.physmem.avgGap 12929580.19 # Average gap between requests system.physmem.avgGap 12929580.19 # Average gap between requests
system.cpu.branchPred.lookups 97757265 # Number of BP lookups
system.cpu.branchPred.condPredicted 88048400 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 3615880 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 65812942 # Number of BTB lookups
system.cpu.branchPred.BTBHits 65493412 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.514488 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1346 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 774559488 # number of cpu cycles simulated system.cpu.numCycles 774559488 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 97757265 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 88048400 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3615880 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 65812942 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 65493412 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1346 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed
system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered

17
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -42,17 +44,18 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts] [system.cpu.interrupts]
type=SparcInterrupts type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb] [system.cpu.itb]
type=SparcTLB type=SparcTLB
size=64 size=64
@ -82,7 +88,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -105,8 +111,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false conf_table_reported=false
file=
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0

8
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 17:04:37 gem5 compiled Jan 23 2013 15:49:24
gem5 started Aug 13 2012 18:13:47 gem5 started Jan 23 2013 16:12:25
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

10
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.744764 # Nu
sim_ticks 744764112500 # Number of ticks simulated sim_ticks 744764112500 # Number of ticks simulated
final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3155762 # Simulator instruction rate (inst/s) host_inst_rate 2243211 # Simulator instruction rate (inst/s)
host_op_rate 3165144 # Simulator op (including micro ops) rate (op/s) host_op_rate 2249879 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1582576951 # Simulator tick rate (ticks/s) host_tick_rate 1124943447 # Simulator tick rate (ticks/s)
host_mem_usage 222108 # Number of bytes of host memory used host_mem_usage 273192 # Number of bytes of host memory used
host_seconds 470.60 # Real time elapsed on the host host_seconds 662.05 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory

64
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
workload=system.cpu.workload workload=system.cpu.workload
@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
is_top_level=true is_top_level=true
latency=1000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
is_top_level=true is_top_level=true
latency=1000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts] [system.cpu.interrupts]
type=SparcInterrupts type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb] [system.cpu.itb]
type=SparcTLB type=SparcTLB
size=64 size=64
@ -120,23 +120,20 @@ size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=8
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=20
is_top_level=false is_top_level=false
latency=10000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=20
repl=Null
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]
@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus] [system.cpu.toL2Bus]
type=CoherentBus type=CoherentBus
block_size=64 block_size=64
clock=1000 clock=500
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=8 width=32
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -163,7 +160,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864
@ -186,8 +183,9 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false conf_table_reported=false
file=
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0

10
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 17:04:37 gem5 compiled Jan 23 2013 15:49:24
gem5 started Aug 13 2012 18:13:49 gem5 started Jan 23 2013 15:49:34
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -38,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 2063177737000 because target called exit() Exiting @ tick 2061066313000 because target called exit()

250
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.061066 # Nu
sim_ticks 2061066313000 # Number of ticks simulated sim_ticks 2061066313000 # Number of ticks simulated
final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 632829 # Simulator instruction rate (inst/s) host_inst_rate 1083437 # Simulator instruction rate (inst/s)
host_op_rate 634711 # Simulator op (including micro ops) rate (op/s) host_op_rate 1086658 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 878254717 # Simulator tick rate (ticks/s) host_tick_rate 1503618533 # Simulator tick rate (ticks/s)
host_mem_usage 225052 # Number of bytes of host memory used host_mem_usage 281644 # Number of bytes of host memory used
host_seconds 2346.78 # Real time elapsed on the host host_seconds 1370.74 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
@ -135,126 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits
system.cpu.dcache.overall_hits::total 568906445 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
system.cpu.dcache.writebacks::total 435341 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2539 # number of replacements system.cpu.l2cache.replacements 2539 # number of replacements
system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use
system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks.
@ -393,5 +273,125 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits
system.cpu.dcache.overall_hits::total 568906445 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
system.cpu.dcache.writebacks::total 435341 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

37
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -514,7 +519,7 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100 gid=100
input=cin input=cin
max_stack_size=67108864 max_stack_size=67108864

8
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:20:54 gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 4 2013 22:11:32 gem5 started Jan 23 2013 18:48:34
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

27
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.607446 # Nu
sim_ticks 607445544000 # Number of ticks simulated sim_ticks 607445544000 # Number of ticks simulated
final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 35384 # Simulator instruction rate (inst/s) host_inst_rate 56942 # Simulator instruction rate (inst/s)
host_op_rate 65197 # Simulator op (including micro ops) rate (op/s) host_op_rate 104918 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 24424271 # Simulator tick rate (ticks/s) host_tick_rate 39304494 # Simulator tick rate (ticks/s)
host_mem_usage 239876 # Number of bytes of host memory used host_mem_usage 295872 # Number of bytes of host memory used
host_seconds 24870.57 # Real time elapsed on the host host_seconds 15454.86 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory
@ -192,18 +192,19 @@ system.physmem.writeRowHits 1084 # Nu
system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes
system.physmem.avgGap 20320661.36 # Average gap between requests system.physmem.avgGap 20320661.36 # Average gap between requests
system.cpu.branchPred.lookups 158385701 # Number of BP lookups
system.cpu.branchPred.condPredicted 158385701 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 26390414 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 84292336 # Number of BTB lookups
system.cpu.branchPred.BTBHits 84079165 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.747105 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1214891089 # number of cpu cycles simulated system.cpu.numCycles 1214891089 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 158385701 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 158385701 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 26390414 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 84292336 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 84079165 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed
system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered

10
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
View file

@ -15,6 +15,7 @@ init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -43,6 +44,7 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -53,6 +55,7 @@ profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2] int_slave=system.membus.master[2]
pio=system.membus.master[1] pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb] [system.cpu.itb]
type=X86TLB type=X86TLB
children=walker children=walker

4
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomi
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18 gem5 compiled Jan 23 2013 16:30:44
gem5 started Dec 30 2012 00:35:29 gem5 started Jan 23 2013 18:52:14
gem5 executing on ribera.cs.wisc.edu gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

10
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu
sim_ticks 963992671500 # Number of ticks simulated sim_ticks 963992671500 # Number of ticks simulated
final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 908989 # Simulator instruction rate (inst/s) host_inst_rate 911190 # Simulator instruction rate (inst/s)
host_op_rate 1674860 # Simulator op (including micro ops) rate (op/s) host_op_rate 1678916 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 995719480 # Simulator tick rate (ticks/s) host_tick_rate 998130396 # Simulator tick rate (ticks/s)
host_mem_usage 267620 # Number of bytes of host memory used host_mem_usage 284224 # Number of bytes of host memory used
host_seconds 968.14 # Real time elapsed on the host host_seconds 965.80 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory

27
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1 numThreads=1
profile=0 profile=0
progress_interval=0 progress_interval=0
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
workload=system.cpu.workload workload=system.cpu.workload
@ -63,21 +66,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -102,21 +100,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2] int_slave=system.membus.master[2]
pio=system.membus.master[1] pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb] [system.cpu.itb]
type=X86TLB type=X86TLB
children=walker children=walker
@ -152,21 +148,16 @@ assoc=8
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=20 hit_latency=20
is_top_level=false is_top_level=false
max_miss_count=0 max_miss_count=0
mshrs=20 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20 response_latency=20
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=12 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]

4
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18 gem5 compiled Jan 23 2013 16:30:44
gem5 started Dec 30 2012 00:35:29 gem5 started Jan 23 2013 18:22:44
gem5 executing on ribera.cs.wisc.edu gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

210
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.800193 # Nu
sim_ticks 1800193397000 # Number of ticks simulated sim_ticks 1800193397000 # Number of ticks simulated
final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 477976 # Simulator instruction rate (inst/s) host_inst_rate 575805 # Simulator instruction rate (inst/s)
host_op_rate 880696 # Simulator op (including micro ops) rate (op/s) host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 977754272 # Simulator tick rate (ticks/s) host_tick_rate 1177876462 # Simulator tick rate (ticks/s)
host_mem_usage 276196 # Number of bytes of host memory used host_mem_usage 292800 # Number of bytes of host memory used
host_seconds 1841.15 # Real time elapsed on the host host_seconds 1528.34 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
@ -135,106 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks
system.cpu.dcache.writebacks::total 422980 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2532 # number of replacements system.cpu.l2cache.replacements 2532 # number of replacements
system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use
system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
@ -370,5 +270,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks
system.cpu.dcache.writebacks::total 422980 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

39
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -522,9 +527,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/gem5/dist/cpu2000/binaries/arm/linux/mcf executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100 gid=100
input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

10
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:17:24 gem5 compiled Jan 23 2013 19:43:25
gem5 started Jan 4 2013 23:47:37 gem5 started Jan 23 2013 19:55:20
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -23,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 26786364500 because target called exit() Exiting @ tick 26773408500 because target called exit()

27
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.026773 # Nu
sim_ticks 26773408500 # Number of ticks simulated sim_ticks 26773408500 # Number of ticks simulated
final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 153523 # Simulator instruction rate (inst/s) host_inst_rate 111467 # Simulator instruction rate (inst/s)
host_op_rate 154625 # Simulator op (including micro ops) rate (op/s) host_op_rate 112267 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45373007 # Simulator tick rate (ticks/s) host_tick_rate 32943427 # Simulator tick rate (ticks/s)
host_mem_usage 376436 # Number of bytes of host memory used host_mem_usage 421388 # Number of bytes of host memory used
host_seconds 590.07 # Real time elapsed on the host host_seconds 812.71 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated sim_ops 91240351 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 1726302.76 # Average gap between requests system.physmem.avgGap 1726302.76 # Average gap between requests
system.cpu.branchPred.lookups 26672080 # Number of BP lookups
system.cpu.branchPred.condPredicted 21992542 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 842598 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11362388 # Number of BTB lookups
system.cpu.branchPred.BTBHits 11268059 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.169814 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 70167 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_hits 0 # DTB read hits
@ -231,14 +240,6 @@ system.cpu.workload.num_syscalls 442 # Nu
system.cpu.numCycles 53546818 # number of cpu cycles simulated system.cpu.numCycles 53546818 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 26672080 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 21992542 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 842598 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 11362388 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 11268059 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 70167 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed
system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered

36
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1 clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -43,6 +44,7 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -53,6 +55,7 @@ profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker] [system.cpu.dtb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.membus.slave[4] port=system.membus.slave[4]
@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts] [system.cpu.interrupts]
type=ArmInterrupts type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb] [system.cpu.itb]
type=ArmTLB type=ArmTLB
children=walker children=walker
@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker] [system.cpu.itb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.membus.slave[3] port=system.membus.slave[3]
@ -100,9 +120,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100 gid=100
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100
@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clock=1 clock=1000
conf_table_reported=false conf_table_reported=false
in_addr_map=true in_addr_map=true
latency=30000 latency=30000

8
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simout
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00 gem5 compiled Jan 23 2013 19:43:25
gem5 started Sep 21 2012 14:03:25 gem5 started Jan 23 2013 20:04:57
gem5 executing on u200540-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

10
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu
sim_ticks 54240661000 # Number of ticks simulated sim_ticks 54240661000 # Number of ticks simulated
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2374877 # Simulator instruction rate (inst/s) host_inst_rate 1585065 # Simulator instruction rate (inst/s)
host_op_rate 2391929 # Simulator op (including micro ops) rate (op/s) host_op_rate 1596445 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1421759359 # Simulator tick rate (ticks/s) host_tick_rate 948925064 # Simulator tick rate (ticks/s)
host_mem_usage 351688 # Number of bytes of host memory used host_mem_usage 411788 # Number of bytes of host memory used
host_seconds 38.15 # Real time elapsed on the host host_seconds 57.16 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated sim_insts 90602407 # Number of instructions simulated
sim_ops 91252960 # Number of ops (including micro ops) simulated sim_ops 91252960 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory

89
tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1 clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1 numThreads=1
profile=0 profile=0
progress_interval=0 progress_interval=0
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
workload=system.cpu.workload workload=system.cpu.workload
@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=1 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
hit_latency=1000
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
response_latency=1000
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker] [system.cpu.dtb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.cpu.toL2Bus.slave[3] port=system.cpu.toL2Bus.slave[3]
@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=1 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
hit_latency=1000
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
response_latency=1000
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts] [system.cpu.interrupts]
type=ArmInterrupts type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb] [system.cpu.itb]
type=ArmTLB type=ArmTLB
children=walker children=walker
@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker] [system.cpu.itb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.cpu.toL2Bus.slave[2] port=system.cpu.toL2Bus.slave[2]
@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=8
block_size=64 block_size=64
clock=1 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=20
hit_latency=10000
is_top_level=false is_top_level=false
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=20
repl=Null
response_latency=10000
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]
@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus] [system.cpu.toL2Bus]
type=CoherentBus type=CoherentBus
block_size=64 block_size=64
clock=1000 clock=500
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=8 width=32
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@ -187,9 +192,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100 gid=100
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100
@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clock=1 clock=1000
conf_table_reported=false conf_table_reported=false
in_addr_map=true in_addr_map=true
latency=30000 latency=30000

10
tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00 gem5 compiled Jan 23 2013 19:43:25
gem5 started Sep 21 2012 12:45:02 gem5 started Jan 23 2013 20:06:05
gem5 executing on u200540-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -23,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 148267705000 because target called exit() Exiting @ tick 147135976000 because target called exit()

226
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
sim_ticks 147135976000 # Number of ticks simulated sim_ticks 147135976000 # Number of ticks simulated
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1200528 # Simulator instruction rate (inst/s) host_inst_rate 836188 # Simulator instruction rate (inst/s)
host_op_rate 1209136 # Simulator op (including micro ops) rate (op/s) host_op_rate 842183 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1950176496 # Simulator tick rate (ticks/s) host_tick_rate 1358330065 # Simulator tick rate (ticks/s)
host_mem_usage 364464 # Number of bytes of host memory used host_mem_usage 420368 # Number of bytes of host memory used
host_seconds 75.45 # Real time elapsed on the host host_seconds 108.32 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
@ -170,114 +170,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
system.cpu.dcache.writebacks::total 942334 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks.
@ -414,5 +306,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
system.cpu.dcache.writebacks::total 942334 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

19
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -42,17 +44,18 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts] [system.cpu.interrupts]
type=SparcInterrupts type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb] [system.cpu.itb]
type=SparcTLB type=SparcTLB
size=64 size=64
@ -82,9 +88,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100 gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100
@ -105,8 +111,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false conf_table_reported=false
file=
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0

8
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 17:04:37 gem5 compiled Jan 23 2013 15:49:24
gem5 started Aug 13 2012 18:13:50 gem5 started Jan 23 2013 16:10:07
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

10
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu
sim_ticks 122215823500 # Number of ticks simulated sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2900370 # Simulator instruction rate (inst/s) host_inst_rate 2097981 # Simulator instruction rate (inst/s)
host_op_rate 2900489 # Simulator op (including micro ops) rate (op/s) host_op_rate 2098068 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1453791405 # Simulator tick rate (ticks/s) host_tick_rate 1051599524 # Simulator tick rate (ticks/s)
host_mem_usage 355144 # Number of bytes of host memory used host_mem_usage 405208 # Number of bytes of host memory used
host_seconds 84.07 # Real time elapsed on the host host_seconds 116.22 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory

66
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
max_loads_any_thread=0 max_loads_any_thread=0
numThreads=1 numThreads=1
phase=0
profile=0 profile=0
progress_interval=0 progress_interval=0
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
workload=system.cpu.workload workload=system.cpu.workload
@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
is_top_level=true is_top_level=true
latency=1000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=2
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=2
is_top_level=true is_top_level=true
latency=1000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=2
repl=Null
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts] [system.cpu.interrupts]
type=SparcInterrupts type=SparcInterrupts
[system.cpu.isa]
type=SparcISA
[system.cpu.itb] [system.cpu.itb]
type=SparcTLB type=SparcTLB
size=64 size=64
@ -120,23 +120,20 @@ size=64
[system.cpu.l2cache] [system.cpu.l2cache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
assoc=2 assoc=8
block_size=64 block_size=64
clock=500
forward_snoops=true forward_snoops=true
hash_delay=1 hit_latency=20
is_top_level=false is_top_level=false
latency=10000
max_miss_count=0 max_miss_count=0
mshrs=10 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false response_latency=20
repl=Null
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=5 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]
@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus] [system.cpu.toL2Bus]
type=CoherentBus type=CoherentBus
block_size=64 block_size=64
clock=1000 clock=500
header_cycles=1 header_cycles=1
use_default_range=false use_default_range=false
width=8 width=32
master=system.cpu.l2cache.cpu_side master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@ -163,9 +160,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100 gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100
@ -186,8 +183,9 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false conf_table_reported=false
file=
in_addr_map=true in_addr_map=true
latency=30000 latency=30000
latency_var=0 latency_var=0

10
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 13 2012 17:04:37 gem5 compiled Jan 23 2013 15:49:24
gem5 started Aug 13 2012 18:15:25 gem5 started Jan 23 2013 16:04:08
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -23,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 362481563000 because target called exit() Exiting @ tick 361488530000 because target called exit()

250
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu
sim_ticks 361488530000 # Number of ticks simulated sim_ticks 361488530000 # Number of ticks simulated
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1414417 # Simulator instruction rate (inst/s) host_inst_rate 1027753 # Simulator instruction rate (inst/s)
host_op_rate 1414475 # Simulator op (including micro ops) rate (op/s) host_op_rate 1027796 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2096975339 # Simulator tick rate (ticks/s) host_tick_rate 1523718944 # Simulator tick rate (ticks/s)
host_mem_usage 357072 # Number of bytes of host memory used host_mem_usage 413792 # Number of bytes of host memory used
host_seconds 172.39 # Real time elapsed on the host host_seconds 237.24 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
@ -128,126 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
system.cpu.dcache.writebacks::total 935266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks.
@ -384,5 +264,125 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
system.cpu.dcache.writebacks::total 935266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

39
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -514,9 +519,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/gem5/dist/cpu2000/binaries/x86/linux/mcf executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100 gid=100
input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

8
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 4 2013 21:20:54 gem5 compiled Jan 23 2013 16:30:44
gem5 started Jan 4 2013 22:18:55 gem5 started Jan 23 2013 16:36:34
gem5 executing on u200540 gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

27
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.065983 # Nu
sim_ticks 65982862500 # Number of ticks simulated sim_ticks 65982862500 # Number of ticks simulated
final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 123083 # Simulator instruction rate (inst/s) host_inst_rate 72483 # Simulator instruction rate (inst/s)
host_op_rate 216729 # Simulator op (including micro ops) rate (op/s) host_op_rate 127630 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51404636 # Simulator tick rate (ticks/s) host_tick_rate 30271870 # Simulator tick rate (ticks/s)
host_mem_usage 379576 # Number of bytes of host memory used host_mem_usage 430980 # Number of bytes of host memory used
host_seconds 1283.60 # Real time elapsed on the host host_seconds 2179.68 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated sim_insts 157988547 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
@ -192,18 +192,19 @@ system.physmem.writeRowHits 45 # Nu
system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
system.physmem.avgGap 2155034.39 # Average gap between requests system.physmem.avgGap 2155034.39 # Average gap between requests
system.cpu.branchPred.lookups 34537566 # Number of BP lookups
system.cpu.branchPred.condPredicted 34537566 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 909846 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 24744786 # Number of BTB lookups
system.cpu.branchPred.BTBHits 24642661 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 99.587287 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 131965726 # number of cpu cycles simulated system.cpu.numCycles 131965726 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 34537566 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 34537566 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 909846 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 24744786 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 24642661 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed
system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered

10
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -15,6 +15,7 @@ init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -43,6 +44,7 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -53,6 +55,7 @@ profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2] int_slave=system.membus.master[2]
pio=system.membus.master[1] pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb] [system.cpu.itb]
type=X86TLB type=X86TLB
children=walker children=walker

4
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18 gem5 compiled Jan 23 2013 16:30:44
gem5 started Dec 30 2012 00:45:38 gem5 started Jan 23 2013 18:49:17
gem5 executing on ribera.cs.wisc.edu gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

10
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
sim_ticks 168950039500 # Number of ticks simulated sim_ticks 168950039500 # Number of ticks simulated
final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 911205 # Simulator instruction rate (inst/s) host_inst_rate 951900 # Simulator instruction rate (inst/s)
host_op_rate 1604486 # Simulator op (including micro ops) rate (op/s) host_op_rate 1676143 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 974425819 # Simulator tick rate (ticks/s) host_tick_rate 1017943887 # Simulator tick rate (ticks/s)
host_mem_usage 402856 # Number of bytes of host memory used host_mem_usage 420484 # Number of bytes of host memory used
host_seconds 173.38 # Real time elapsed on the host host_seconds 165.97 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated sim_insts 157988548 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory

27
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -14,7 +14,8 @@ clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=timing
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=TimingSimpleCPU type=TimingSimpleCPU
children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1 numThreads=1
profile=0 profile=0
progress_interval=0 progress_interval=0
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
workload=system.cpu.workload workload=system.cpu.workload
@ -63,21 +66,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=262144 size=262144
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.dcache_port cpu_side=system.cpu.dcache_port
@ -102,21 +100,16 @@ assoc=2
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=2 hit_latency=2
is_top_level=true is_top_level=true
max_miss_count=0 max_miss_count=0
mshrs=4 mshrs=4
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=2 response_latency=2
size=131072 size=131072
subblock_size=0
system=system system=system
tgts_per_mshr=20 tgts_per_mshr=20
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.icache_port cpu_side=system.cpu.icache_port
@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2] int_slave=system.membus.master[2]
pio=system.membus.master[1] pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb] [system.cpu.itb]
type=X86TLB type=X86TLB
children=walker children=walker
@ -152,21 +148,16 @@ assoc=8
block_size=64 block_size=64
clock=500 clock=500
forward_snoops=true forward_snoops=true
hash_delay=1
hit_latency=20 hit_latency=20
is_top_level=false is_top_level=false
max_miss_count=0 max_miss_count=0
mshrs=20 mshrs=20
prefetch_on_access=false prefetch_on_access=false
prefetcher=Null prefetcher=Null
prioritizeRequests=false
repl=Null
response_latency=20 response_latency=20
size=2097152 size=2097152
subblock_size=0
system=system system=system
tgts_per_mshr=12 tgts_per_mshr=12
trace_addr=0
two_queue=false two_queue=false
write_buffers=8 write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0] cpu_side=system.cpu.toL2Bus.master[0]

4
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 30 2012 00:35:18 gem5 compiled Jan 23 2013 16:30:44
gem5 started Dec 30 2012 00:35:30 gem5 started Jan 23 2013 16:31:05
gem5 executing on ribera.cs.wisc.edu gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second

210
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
sim_ticks 365989064000 # Number of ticks simulated sim_ticks 365989064000 # Number of ticks simulated
final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 426513 # Simulator instruction rate (inst/s) host_inst_rate 496442 # Simulator instruction rate (inst/s)
host_op_rate 751021 # Simulator op (including micro ops) rate (op/s) host_op_rate 874155 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 988040650 # Simulator tick rate (ticks/s) host_tick_rate 1150035399 # Simulator tick rate (ticks/s)
host_mem_usage 411308 # Number of bytes of host memory used host_mem_usage 428932 # Number of bytes of host memory used
host_seconds 370.42 # Real time elapsed on the host host_seconds 318.24 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated sim_insts 157988548 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
@ -135,106 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
system.cpu.dcache.writebacks::total 2062484 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 318 # number of replacements system.cpu.l2cache.replacements 318 # number of replacements
system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
@ -373,5 +273,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
system.cpu.dcache.writebacks::total 2062484 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

39
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=DerivO3CPU type=DerivO3CPU
children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024 LFSTSize=1024
LQEntries=32 LQEntries=32
LSQCheckLoads=true LSQCheckLoads=true
LSQDepCheckShift=4 LSQDepCheckShift=4
RASSize=16
SQEntries=32 SQEntries=32
SSITSize=1024 SSITSize=1024
activity=0 activity=0
backComSize=5 backComSize=5
branchPred=system.cpu.branchPred
cachePorts=200 cachePorts=200
checker=Null checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500 clock=500
commitToDecodeDelay=1 commitToDecodeDelay=1
commitToFetchDelay=1 commitToFetchDelay=1
@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool fuPool=system.cpu.fuPool
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1 iewToCommitDelay=1
iewToDecodeDelay=1 iewToDecodeDelay=1
iewToFetchDelay=1 iewToFetchDelay=1
iewToRenameDelay=1 iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa isa=system.cpu.isa
issueToExecuteDelay=1 issueToExecuteDelay=1
issueWidth=8 issueWidth=8
itb=system.cpu.itb itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
max_loads_all_threads=0 max_loads_all_threads=0
@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192 numROBEntries=192
numRobs=1 numRobs=1
numThreads=1 numThreads=1
predType=tournament
profile=0 profile=0
progress_interval=0 progress_interval=0
renameToDecodeDelay=1 renameToDecodeDelay=1
@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache] [system.cpu.dcache]
type=BaseCache type=BaseCache
addr_ranges=0:18446744073709551615 addr_ranges=0:18446744073709551615
@ -522,9 +527,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/gem5/dist/cpu2000/binaries/arm/linux/parser executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100 gid=100
input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100

36
tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
View file

@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System type=System
children=cpu membus physmem children=cpu membus physmem
boot_osflags=a boot_osflags=a
clock=1 clock=1000
init_param=0 init_param=0
kernel= kernel=
load_addr_mask=1099511627775 load_addr_mask=1099511627775
mem_mode=atomic mem_mode=atomic
mem_ranges=
memories=system.physmem memories=system.physmem
num_work_ids=16 num_work_ids=16
readfile= readfile=
@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu] [system.cpu]
type=AtomicSimpleCPU type=AtomicSimpleCPU
children=dtb interrupts itb tracer workload children=dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null checker=Null
clock=500 clock=500
cpu_id=0 cpu_id=0
defer_registration=false
do_checkpoint_insts=true do_checkpoint_insts=true
do_quiesce=true do_quiesce=true
do_statistics_insts=true do_statistics_insts=true
@ -43,6 +44,7 @@ fastmem=false
function_trace=false function_trace=false
function_trace_start=0 function_trace_start=0
interrupts=system.cpu.interrupts interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb itb=system.cpu.itb
max_insts_all_threads=0 max_insts_all_threads=0
max_insts_any_thread=0 max_insts_any_thread=0
@ -53,6 +55,7 @@ profile=0
progress_interval=0 progress_interval=0
simulate_data_stalls=false simulate_data_stalls=false
simulate_inst_stalls=false simulate_inst_stalls=false
switched_out=false
system=system system=system
tracer=system.cpu.tracer tracer=system.cpu.tracer
width=1 width=1
@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker] [system.cpu.dtb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.membus.slave[4] port=system.membus.slave[4]
@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts] [system.cpu.interrupts]
type=ArmInterrupts type=ArmInterrupts
[system.cpu.isa]
type=ArmISA
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=3
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=4027589137
id_pfr0=49
id_pfr1=1
midr=890224640
[system.cpu.itb] [system.cpu.itb]
type=ArmTLB type=ArmTLB
children=walker children=walker
@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker] [system.cpu.itb.walker]
type=ArmTableWalker type=ArmTableWalker
clock=1 clock=500
num_squash_per_cycle=2 num_squash_per_cycle=2
sys=system sys=system
port=system.membus.slave[3] port=system.membus.slave[3]
@ -100,9 +120,9 @@ egid=100
env= env=
errout=cerr errout=cerr
euid=100 euid=100
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100 gid=100
input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864 max_stack_size=67108864
output=cout output=cout
pid=100 pid=100
@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem] [system.physmem]
type=SimpleMemory type=SimpleMemory
bandwidth=73.000000 bandwidth=73.000000
clock=1 clock=1000
conf_table_reported=false conf_table_reported=false
in_addr_map=true in_addr_map=true
latency=30000 latency=30000

8
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
View file

@ -1,9 +1,11 @@
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 21 2012 11:19:00 gem5 compiled Jan 23 2013 19:43:25
gem5 started Sep 21 2012 11:53:48 gem5 started Jan 23 2013 20:09:03
gem5 executing on u200540-lin gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...

10
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu
sim_ticks 290498967000 # Number of ticks simulated sim_ticks 290498967000 # Number of ticks simulated
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2312706 # Simulator instruction rate (inst/s) host_inst_rate 1613323 # Simulator instruction rate (inst/s)
host_op_rate 2606651 # Simulator op (including micro ops) rate (op/s) host_op_rate 1818377 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1326219887 # Simulator tick rate (ticks/s) host_tick_rate 925159382 # Simulator tick rate (ticks/s)
host_mem_usage 222284 # Number of bytes of host memory used host_mem_usage 282068 # Number of bytes of host memory used
host_seconds 219.04 # Real time elapsed on the host host_seconds 314.00 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated sim_insts 506581607 # Number of instructions simulated
sim_ops 570968167 # Number of ops (including micro ops) simulated sim_ops 570968167 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory

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