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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
Nilay Vaish 9bc132e473 regressions: update stats due to branch predictor changes 
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
2013-01-24 12:29:00 -06:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.540276 # Number of seconds simulated
sim_ticks 2540275734000 # Number of ticks simulated
final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50621 # Simulator instruction rate (inst/s)
host_op_rate 65136 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2132095179 # Simulator tick rate (ticks/s)
host_mem_usage 455960 # Number of bytes of host memory used
host_seconds 1191.45 # Real time elapsed on the host
sim_insts 60312498 # Number of instructions simulated
sim_ops 77605759 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 405568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 3860688 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 395008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 5229152 # Number of bytes read from this memory
system.physmem.bytes_read::total 131004144 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 405568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 395008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3783168 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1412956 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1603284 # Number of bytes written to this memory
system.physmem.bytes_written::total 6799408 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6337 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 60357 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 23 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6172 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 81713 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15293445 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59112 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 353239 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 400821 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813172 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47676135 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 605 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 159655 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1519791 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 579 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 155498 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 2058498 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51570836 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 159655 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 155498 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 315153 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1489275 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 556222 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 631146 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2676642 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1489275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47676135 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 159655 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2076012 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 579 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 155498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2689643 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54247478 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15293445 # Total number of read requests seen
system.physmem.writeReqs 813172 # Total number of write requests seen
system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 978780480 # Total number of bytes read from memory
system.physmem.bytesWritten 52043008 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131004144 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6799408 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 955910 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 956214 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 955714 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 955761 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 955656 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 955538 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 955410 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 955590 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956063 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 955922 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955987 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955944 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 956042 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 955918 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 956046 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 955719 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50108 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50359 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 50035 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50823 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50679 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50829 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51147 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 51119 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51116 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51361 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51167 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51295 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51031 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 693675 # Number of times wr buffer was full causing retry
system.physmem.totGap 2540274436500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 44 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 154585 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 1447735 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 59112 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 1057043 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 992576 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 949780 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 984222 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2774561 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2777593 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 5475568 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 36103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 30071 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29941 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 29875 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 57717 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 31668 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 59387 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 5361 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1880 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 3638 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3819 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4603 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35332 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35325 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35257 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 31872 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 31784 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 31663 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 31466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 31190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 30972 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 30814 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 30644 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 30396 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 295222941913 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 372544627913 # Sum of mem lat for all requests
system.physmem.totBusLat 61173736000 # Total cycles spent in databus access
system.physmem.totBankLat 16147950000 # Total cycles spent in bank access
system.physmem.avgQLat 19303.90 # Average queueing delay per request
system.physmem.avgBankLat 1055.87 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 24359.78 # Average memory access latency
system.physmem.avgRdBW 385.30 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.49 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.57 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.54 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 1.11 # Average write queue length over time
system.physmem.readRowHits 15250779 # Number of row buffer hits during reads
system.physmem.writeRowHits 786181 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.68 # Row buffer hit rate for writes
system.physmem.avgGap 157716.20 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 64355 # number of replacements
system.l2c.tagsinuse 51419.267755 # Cycle average of tags in use
system.l2c.total_refs 1938049 # Total number of references to valid blocks.
system.l2c.sampled_refs 129745 # Sample count of references to valid blocks.
system.l2c.avg_refs 14.937369 # Average number of references to valid blocks.
system.l2c.warmup_cycle 2504164034000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 36931.020579 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 16.606352 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000348 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4513.419817 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 3324.401102 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 19.072216 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker 0.003905 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 3703.882826 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 2910.860610 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.563523 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000253 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.068869 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.050726 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000291 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.056517 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.044416 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.784596 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 45285 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 6882 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 457711 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 190308 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 52226 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7603 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 514110 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 196973 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1471098 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 608285 # number of Writeback hits
system.l2c.Writeback_hits::total 608285 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 19 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 36 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 56083 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 56920 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113003 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 45285 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 6882 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 457711 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 246391 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 52226 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 7603 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 514110 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 253893 # number of demand (read+write) hits
system.l2c.demand_hits::total 1584101 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 45285 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 6882 # number of overall hits
system.l2c.overall_hits::cpu0.inst 457711 # number of overall hits
system.l2c.overall_hits::cpu0.data 246391 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 52226 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 7603 # number of overall hits
system.l2c.overall_hits::cpu1.inst 514110 # number of overall hits
system.l2c.overall_hits::cpu1.data 253893 # number of overall hits
system.l2c.overall_hits::total 1584101 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 24 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 6225 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6013 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 23 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6180 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4688 # number of ReadReq misses
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system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1246542 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56002 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 248969104 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3181351038 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6028429669 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1489045 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 247133124 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2348091812 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1246542 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56002 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 248969104 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3181351038 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6028429669 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4312653 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83367317530 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83605453007 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166977083190 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 6167057731 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8185447208 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 14352504939 # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76004 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76004 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4312653 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 89534375261 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91790900215 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 181329588129 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.030440 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023133 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.015447 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987445 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987990 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.987738 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.142857 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.495879 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578133 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.540961 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.198791 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.089778 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.198791 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.089778 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41387.654116 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42592.949196 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40941.666580 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10046.393474 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.465517 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 38080.687217 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 38237.204887 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 38172.367057 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 6894641 # Number of BP lookups
system.cpu0.branchPred.condPredicted 5490275 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 340467 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4496048 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 3641169 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 80.985990 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 672237 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 35025 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 25321176 # DTB read hits
system.cpu0.dtb.read_misses 39544 # DTB read misses
system.cpu0.dtb.write_hits 5538222 # DTB write hits
system.cpu0.dtb.write_misses 9025 # DTB write misses
system.cpu0.dtb.flush_tlb 256 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 7899 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1433 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 25360720 # DTB read accesses
system.cpu0.dtb.write_accesses 5547247 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 30859398 # DTB hits
system.cpu0.dtb.misses 48569 # DTB misses
system.cpu0.dtb.accesses 30907967 # DTB accesses
system.cpu0.itb.inst_hits 5399990 # ITB inst hits
system.cpu0.itb.inst_misses 6797 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 256 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2645 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1504 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 5406787 # ITB inst accesses
system.cpu0.itb.hits 5399990 # DTB hits
system.cpu0.itb.misses 6797 # DTB misses
system.cpu0.itb.accesses 5406787 # DTB accesses
system.cpu0.numCycles 232916834 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4313406 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 9542116 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2097502 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 81571 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 47928082 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 983 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 1918 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 48764 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 90424 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 5397887 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 280481 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3116 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 73293713 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.724548 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.073228 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 63759289 86.99% 86.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 642563 0.88% 87.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 816896 1.11% 88.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 1076628 1.47% 90.45% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1030388 1.41% 91.86% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 525946 0.72% 92.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 1160801 1.58% 94.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 367124 0.50% 94.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3914078 5.34% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 73293713 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.029601 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.183647 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 15070134 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 47635747 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 8687716 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 522868 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1375117 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 927671 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 82962 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 50805033 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 279607 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1375117 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 15858431 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 18747322 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 25731690 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 8353206 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3225899 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 48905504 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 13838 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 630791 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2093496 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 12811 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 50688794 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 222549147 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 222507399 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 41748 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 38461100 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 12227693 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 386484 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 344770 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 6389877 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 9452191 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6279292 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 988040 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1320602 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 45692134 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 977389 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 60037368 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 85152 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 8499333 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 20279389 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 254746 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 73293713 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.819134 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.521823 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 51609317 70.41% 70.41% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 6835660 9.33% 79.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3457344 4.72% 84.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2997093 4.09% 88.55% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 6031042 8.23% 96.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1346418 1.84% 98.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 738853 1.01% 99.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 217523 0.30% 99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 60463 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 73293713 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 26194 0.60% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 3 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4172771 94.90% 95.50% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 194561 0.32% 0.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 28037950 46.70% 47.02% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 44753 0.07% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 838 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 25907736 43.15% 90.25% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5851514 9.75% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 60037368 # Type of FU issued
system.cpu0.iq.rate 0.257763 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 4397050 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.073239 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 197888427 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 55177485 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 41654501 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 10625 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 5737 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 4733 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 64234192 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 5665 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 298497 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1811405 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3010 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 725021 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 17048224 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 266574 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1375117 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 14032156 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 223286 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 46775692 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 94480 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 9452191 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6279292 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 703336 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 50186 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 4000 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 14875 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 165277 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 131199 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 296476 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 59245437 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 25661722 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 791931 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 106169 # number of nop insts executed
system.cpu0.iew.exec_refs 31462090 # number of memory reference insts executed
system.cpu0.iew.exec_branches 5561458 # Number of branches executed
system.cpu0.iew.exec_stores 5800368 # Number of stores executed
system.cpu0.iew.exec_rate 0.254363 # Inst execution rate
system.cpu0.iew.wb_sent 58848296 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 41659234 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 23213315 # num instructions producing a value
system.cpu0.iew.wb_consumers 42468919 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.178859 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.546595 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 8329034 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 722643 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 258629 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 71918596 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.527800 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.514238 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 58433692 81.25% 81.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6549576 9.11% 90.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 1938281 2.70% 93.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1064527 1.48% 94.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 992329 1.38% 95.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 495986 0.69% 96.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 654165 0.91% 97.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 355670 0.49% 98.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1434370 1.99% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 71918596 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 29885048 # Number of instructions committed
system.cpu0.commit.committedOps 37958605 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 13195057 # Number of memory references committed
system.cpu0.commit.loads 7640786 # Number of loads committed
system.cpu0.commit.membars 194107 # Number of memory barriers committed
system.cpu0.commit.branches 4848128 # Number of branches committed
system.cpu0.commit.fp_insts 4699 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 33604858 # Number of committed integer instructions.
system.cpu0.commit.function_calls 476381 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1434370 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 115883530 # The number of ROB reads
system.cpu0.rob.rob_writes 93994803 # The number of ROB writes
system.cpu0.timesIdled 855495 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 159623121 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 2324012553 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 29813564 # Number of Instructions Simulated
system.cpu0.committedOps 37887121 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 29813564 # Number of Instructions Simulated
system.cpu0.cpi 7.812445 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 7.812445 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.128001 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.128001 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 268137987 # number of integer regfile reads
system.cpu0.int_regfile_writes 42752144 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22081 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19566 # number of floating regfile writes
system.cpu0.misc_regfile_reads 14602892 # number of misc regfile reads
system.cpu0.misc_regfile_writes 394034 # number of misc regfile writes
system.cpu0.icache.replacements 984960 # number of replacements
system.cpu0.icache.tagsinuse 511.605628 # Cycle average of tags in use
system.cpu0.icache.total_refs 10192469 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 985472 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 10.342728 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6475146000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 192.391014 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 319.214614 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.375764 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.623466 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999230 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 4895846 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 5296623 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 10192469 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 4895846 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 5296623 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 10192469 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 4895846 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 5296623 # number of overall hits
system.cpu0.icache.overall_hits::total 10192469 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 501920 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 563999 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1065919 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 501920 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 563999 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1065919 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 501920 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 563999 # number of overall misses
system.cpu0.icache.overall_misses::total 1065919 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6726188495 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7525770495 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14251958990 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6726188495 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 7525770495 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14251958990 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6726188495 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 7525770495 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14251958990 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5397766 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 5860622 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 11258388 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 5397766 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 5860622 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 11258388 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 5397766 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 5860622 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 11258388 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092987 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.096235 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.094678 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092987 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.096235 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.094678 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092987 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.096235 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.094678 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13400.917467 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13343.588366 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13370.583496 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13370.583496 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13370.583496 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 5202 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 775 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 345 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.078261 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 775 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37396 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 43020 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 80416 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 37396 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 43020 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 80416 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 37396 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 43020 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 80416 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 464524 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 520979 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 985503 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 464524 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 520979 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 985503 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 464524 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 520979 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 985503 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5488905495 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 6129367496 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11618272991 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5488905495 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 6129367496 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11618272991 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5488905495 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 6129367496 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11618272991 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6767000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6767000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6767000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 6767000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087535 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.087535 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.087535 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11789.180744 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 643643 # number of replacements
system.cpu0.dcache.tagsinuse 511.994132 # Cycle average of tags in use
system.cpu0.dcache.total_refs 21553843 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 644155 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 33.460647 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 36157000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 257.044618 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 254.949514 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.502040 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.497948 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu1.data 7127763 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13796118 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3513738 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 7263848 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119013 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 124173 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 243186 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120748 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 126887 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247635 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10182093 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10877873 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 10182093 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10877873 # number of overall hits
system.cpu0.dcache.overall_hits::total 21059966 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu1.data 347013 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 745885 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1308679 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 2959373 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5990 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 7586 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses
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system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
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system.cpu0.dcache.overall_misses::cpu1.data 1997707 # number of overall misses
system.cpu0.dcache.overall_misses::total 3705258 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::total 11148168500 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 114339524155 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81001000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 104468000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 185469000 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 103000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 193000 # number of StoreCondReq miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu1.data 72660386320 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 125487692655 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 52827306335 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 72660386320 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 125487692655 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7067227 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 7474776 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 14542003 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4822417 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5400804 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10223221 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125003 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131759 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 256762 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120754 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 126894 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247648 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11889644 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 24765224 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11889644 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 12875580 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24765224 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056440 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.046425 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.051292 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.271374 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.305639 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.289476 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047919 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.057575 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052874 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000050 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000055 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143617 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155155 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.149615 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143617 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.155155 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.149615 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14655.528591 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15280.374222 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14946.229647 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35900.038386 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40805.805207 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38636.401750 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13522.704508 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13771.157395 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13661.535062 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14714.285714 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14846.153846 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30937.469121 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36371.893536 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33867.464197 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30937.469121 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36371.893536 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33867.464197 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 37449 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 14136 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3410 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 266 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.982111 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 53.142857 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 608285 # number of writebacks
system.cpu0.dcache.writebacks::total 608285 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 207823 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 152147 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 359970 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1196124 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1514247 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 2710371 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 670 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 732 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1402 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1403947 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1666394 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 3070341 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.overall_mshr_hits::total 3070341 # number of overall MSHR hits
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system.cpu0.dcache.WriteReq_mshr_misses::total 249002 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5320 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6854 # number of LoadLockedReq MSHR misses
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system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 62428500 # number of LoadLockedReq MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7422009940 # number of overall MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91055617500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91310638500 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13444453545 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 24249605201 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101860769156 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104755092045 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206615861201 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027033 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026070 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026538 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023340 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025264 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042559 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052019 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047414 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000055 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025637 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.025637 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13553.062303 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13309.243275 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13429.947009 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31858.540118 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35387.300124 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33792.214211 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11734.680451 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11935.658010 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.831444 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12846.153846 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 7461261 # Number of BP lookups
system.cpu1.branchPred.condPredicted 5924878 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 387688 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 4864845 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 3916001 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 80.495905 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 732677 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 39651 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 25842433 # DTB read hits
system.cpu1.dtb.read_misses 46174 # DTB read misses
system.cpu1.dtb.write_hits 6180963 # DTB write hits
system.cpu1.dtb.write_misses 11315 # DTB write misses
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 8574 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 1449 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 622 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25888607 # DTB read accesses
system.cpu1.dtb.write_accesses 6192278 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 32023396 # DTB hits
system.cpu1.dtb.misses 57489 # DTB misses
system.cpu1.dtb.accesses 32080885 # DTB accesses
system.cpu1.itb.inst_hits 5862958 # ITB inst hits
system.cpu1.itb.inst_misses 7630 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2762 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 1655 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 5870588 # ITB inst accesses
system.cpu1.itb.hits 5862958 # DTB hits
system.cpu1.itb.misses 7630 # DTB misses
system.cpu1.itb.accesses 5870588 # DTB accesses
system.cpu1.numCycles 238328292 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 4648678 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 10301295 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 2449187 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 90048 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 49530341 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 1725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 2013 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 58322 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 105488 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 5860623 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 343915 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3550 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 77436496 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.743507 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.098927 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 67142740 86.71% 86.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 670388 0.87% 87.57% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 904116 1.17% 88.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1146258 1.48% 90.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1035072 1.34% 91.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 585216 0.76% 92.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1324002 1.71% 94.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 382858 0.49% 94.52% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 4245846 5.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 77436496 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.031307 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.191852 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 16603606 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 49335429 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 9407116 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 490405 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1597859 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1045633 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 93792 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 54840588 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 310696 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1597859 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17482170 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 19064051 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 27065673 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8938575 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 3286155 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 52466184 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 7798 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 497565 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 2245284 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 18515 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 54189093 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 239808372 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 239759506 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 48866 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 39935280 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 14253813 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 446450 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 393915 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6702948 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 10122887 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6990261 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 974914 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1217289 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 48733638 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1005144 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 62551860 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 96432 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 9690546 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 24103101 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 245099 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 77436496 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.807783 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.518787 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 54919142 70.92% 70.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 7063904 9.12% 80.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 3691282 4.77% 84.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 2953327 3.81% 88.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 6235094 8.05% 96.68% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1492250 1.93% 98.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 791283 1.02% 99.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 225625 0.29% 99.92% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 64589 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 77436496 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 27571 0.62% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 1 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4198494 94.58% 95.20% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 213042 4.80% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 169105 0.27% 0.27% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 29343777 46.91% 47.18% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 48983 0.08% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1277 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 26498919 42.36% 89.62% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6489779 10.38% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 62551860 # Type of FU issued
system.cpu1.iq.rate 0.262461 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4439108 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.070967 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 207120715 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 59438377 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 43832825 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 12343 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 6735 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5565 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 66815352 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 6511 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 325479 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2107508 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3797 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 16351 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 811464 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 17060218 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 341441 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1597859 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 14264833 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 247482 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 49856426 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 107204 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 10122887 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6990261 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 704284 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 59901 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 3604 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 16351 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 190247 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 149600 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 339847 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 61552998 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 26188496 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 998862 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 117644 # number of nop insts executed
system.cpu1.iew.exec_refs 32619530 # number of memory reference insts executed
system.cpu1.iew.exec_branches 5900270 # Number of branches executed
system.cpu1.iew.exec_stores 6431034 # Number of stores executed
system.cpu1.iew.exec_rate 0.258270 # Inst execution rate
system.cpu1.iew.wb_sent 61059596 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 43838390 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 23681235 # num instructions producing a value
system.cpu1.iew.wb_consumers 43694541 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.183941 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.541972 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 9661212 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 760045 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 295282 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 75838637 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.524766 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.504226 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 61579117 81.20% 81.20% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 7021291 9.26% 90.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 2015124 2.66% 93.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1085811 1.43% 94.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1003078 1.32% 95.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 577963 0.76% 96.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 742657 0.98% 97.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 378274 0.50% 98.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1435322 1.89% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 75838637 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 30577831 # Number of instructions committed
system.cpu1.commit.committedOps 39797535 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 14194176 # Number of memory references committed
system.cpu1.commit.loads 8015379 # Number of loads committed
system.cpu1.commit.membars 209589 # Number of memory barriers committed
system.cpu1.commit.branches 5113967 # Number of branches committed
system.cpu1.commit.fp_insts 5513 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 35255841 # Number of committed integer instructions.
system.cpu1.commit.function_calls 515004 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1435322 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 122900984 # The number of ROB reads
system.cpu1.rob.rob_writes 100566633 # The number of ROB writes
system.cpu1.timesIdled 901138 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 160891796 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 2255172449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 30498934 # Number of Instructions Simulated
system.cpu1.committedOps 39718638 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 30498934 # Number of Instructions Simulated
system.cpu1.cpi 7.814315 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 7.814315 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.127970 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.127970 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 279110946 # number of integer regfile reads
system.cpu1.int_regfile_writes 44685160 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22658 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19886 # number of floating regfile writes
system.cpu1.misc_regfile_reads 15820673 # number of misc regfile reads
system.cpu1.misc_regfile_writes 438571 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1125362728944 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1125362728944 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 83058 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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