stats: changes to due to recent set of patches
This commit is contained in:
Nilay Vaish
parent
0c8e025c3b
commit
99fb8f8140
115 changed files with 1300 additions and 1199 deletions
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@ -645,7 +645,6 @@ system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Cl
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system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction
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system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.rob.rob_reads 165216916 # The number of ROB reads
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system.cpu0.rob.rob_writes 117798939 # The number of ROB writes
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system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -1241,7 +1240,6 @@ system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Cl
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system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction
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system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu1.rob.rob_reads 23176968 # The number of ROB reads
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system.cpu1.rob.rob_writes 20704388 # The number of ROB writes
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system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -633,7 +633,6 @@ system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
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system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 177593269 # The number of ROB reads
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system.cpu.rob.rob_writes 130137832 # The number of ROB writes
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system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -1317,7 +1317,6 @@ system.cpu2.commit.op_class_0::IprAccess 303954 0.94% 100.00% # Cl
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system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction
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system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached
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system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu2.rob.rob_reads 62726939 # The number of ROB reads
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system.cpu2.rob.rob_writes 70507401 # The number of ROB writes
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system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -964,7 +964,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction
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system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 375672050 # The number of ROB reads
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system.cpu.rob.rob_writes 292972268 # The number of ROB writes
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system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -865,7 +865,6 @@ system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu0.commit.op_class_0::total 120715819 # Class of committed instruction
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system.cpu0.commit.bw_lim_events 1448193 # number cycles where commit BW limit reached
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.rob.rob_reads 292184577 # The number of ROB reads
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system.cpu0.rob.rob_writes 263546817 # The number of ROB writes
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system.cpu0.timesIdled 122559 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -2077,7 +2076,6 @@ system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu1.commit.op_class_0::total 25443224 # Class of committed instruction
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system.cpu1.commit.bw_lim_events 442982 # number cycles where commit BW limit reached
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu1.rob.rob_reads 68115809 # The number of ROB reads
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system.cpu1.rob.rob_writes 56808236 # The number of ROB writes
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system.cpu1.timesIdled 67589 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -825,7 +825,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction
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system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 375672050 # The number of ROB reads
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system.cpu.rob.rob_writes 292972268 # The number of ROB writes
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system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -1725,7 +1725,6 @@ system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu2.commit.op_class_0::total 47174544 # Class of committed instruction
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system.cpu2.commit.bw_lim_events 1230130 # number cycles where commit BW limit reached
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system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu2.rob.rob_reads 112818862 # The number of ROB reads
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system.cpu2.rob.rob_writes 112362949 # The number of ROB writes
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system.cpu2.timesIdled 279332 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -851,7 +851,6 @@ system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu0.commit.op_class_0::total 68988407 # Class of committed instruction
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system.cpu0.commit.bw_lim_events 1718944 # number cycles where commit BW limit reached
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.rob.rob_reads 167372763 # The number of ROB reads
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system.cpu0.rob.rob_writes 163072923 # The number of ROB writes
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system.cpu0.timesIdled 393865 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -1778,7 +1777,6 @@ system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction
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system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu1.rob.rob_reads 173729023 # The number of ROB reads
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system.cpu1.rob.rob_writes 171875858 # The number of ROB writes
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system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -975,7 +975,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction
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system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 2555711925 # The number of ROB reads
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system.cpu.rob.rob_writes 2125474325 # The number of ROB writes
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system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -848,7 +848,6 @@ system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction
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system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads
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system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes
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system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -2097,7 +2096,6 @@ system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction
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system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads
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system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes
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system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -836,7 +836,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction
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system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 2555711925 # The number of ROB reads
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system.cpu.rob.rob_writes 2125474325 # The number of ROB writes
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system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -1816,7 +1816,6 @@ system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu2.commit.op_class_0::total 387615464 # Class of committed instruction
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system.cpu2.commit.bw_lim_events 16778864 # number cycles where commit BW limit reached
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system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu2.rob.rob_reads 862595097 # The number of ROB reads
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system.cpu2.rob.rob_writes 905518660 # The number of ROB writes
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system.cpu2.timesIdled 2960768 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -873,7 +873,6 @@ system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu0.commit.op_class_0::total 532162399 # Class of committed instruction
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system.cpu0.commit.bw_lim_events 22726868 # number cycles where commit BW limit reached
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.rob.rob_reads 1220262369 # The number of ROB reads
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system.cpu0.rob.rob_writes 1241914021 # The number of ROB writes
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system.cpu0.timesIdled 4040058 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -1848,7 +1847,6 @@ system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu1.commit.op_class_0::total 535141123 # Class of committed instruction
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system.cpu1.commit.bw_lim_events 22907771 # number cycles where commit BW limit reached
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu1.rob.rob_reads 1220174232 # The number of ROB reads
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system.cpu1.rob.rob_writes 1248183780 # The number of ROB writes
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system.cpu1.timesIdled 4134360 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -597,7 +597,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction
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system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 1270729806 # The number of ROB reads
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system.cpu.rob.rob_writes 1664729387 # The number of ROB writes
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system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -1103,7 +1103,6 @@ system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu2.commit.op_class_0::total 270578300 # Class of committed instruction
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system.cpu2.commit.bw_lim_events 2129956 # number cycles where commit BW limit reached
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system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu2.rob.rob_reads 431186663 # The number of ROB reads
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system.cpu2.rob.rob_writes 561693850 # The number of ROB writes
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system.cpu2.timesIdled 124283 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -676,7 +676,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
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system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 217986125 # The number of ROB reads
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system.cpu.rob.rob_writes 219581178 # The number of ROB writes
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system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -557,7 +557,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
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system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 419820689 # The number of ROB reads
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system.cpu.rob.rob_writes 657620446 # The number of ROB writes
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system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -686,7 +686,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
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system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 1093653497 # The number of ROB reads
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system.cpu.rob.rob_writes 1334601058 # The number of ROB writes
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system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -579,7 +579,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
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system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 2867051516 # The number of ROB reads
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system.cpu.rob.rob_writes 4304473794 # The number of ROB writes
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system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -572,7 +572,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
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system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 543683043 # The number of ROB reads
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system.cpu.rob.rob_writes 885930772 # The number of ROB writes
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system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -655,7 +655,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction
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system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 561599370 # The number of ROB reads
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system.cpu.rob.rob_writes 705507733 # The number of ROB writes
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system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -595,7 +595,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction
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system.cpu.commit.bw_lim_events 50554341 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 1905392712 # The number of ROB reads
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system.cpu.rob.rob_writes 3017093514 # The number of ROB writes
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system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself
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@ -692,7 +692,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
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system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction
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system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.rob.rob_reads 1891410858 # The number of ROB reads
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system.cpu.rob.rob_writes 2343104087 # The number of ROB writes
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system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -601,7 +601,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 133590014 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 196617452 # The number of ROB writes
|
||||
system.cpu.timesIdled 47547 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -687,7 +687,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 158240550 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 195514428 # The number of ROB writes
|
||||
system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -621,7 +621,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 3840325519 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 5790523687 # The number of ROB writes
|
||||
system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -703,7 +703,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 3367926925 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 3883468057 # The number of ROB writes
|
||||
system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -572,7 +572,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 157112780 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 252206838 # The number of ROB writes
|
||||
system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -656,7 +656,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 406304779 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 513839131 # The number of ROB writes
|
||||
system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -539,7 +539,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 615300578 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 699132843 # The number of ROB writes
|
||||
system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
|
|
@ -394,9 +395,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
|
@ -478,11 +481,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -543,11 +549,14 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
|
|
@ -227,8 +228,11 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -310,9 +314,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
|
@ -358,11 +364,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
|
|
@ -386,9 +387,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
|
@ -470,11 +473,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -524,7 +530,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -599,11 +605,14 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
|
|
@ -223,8 +224,11 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -306,9 +310,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.tsunami.pciconfig.pio
|
||||
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
|
||||
|
|
@ -354,11 +360,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
|
@ -408,7 +417,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM
|
|||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -177,6 +178,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.dtb
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -194,7 +196,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -288,6 +289,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.itb
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -305,7 +307,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -389,13 +390,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu0.l2cache.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -481,6 +485,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -498,7 +503,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -592,6 +596,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -609,7 +614,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -693,13 +697,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu1.l2cache.cpu_side
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -730,9 +737,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -814,11 +823,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -1515,11 +1527,14 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM
|
|||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -177,6 +178,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -194,7 +196,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -288,6 +289,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -305,7 +307,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -364,13 +365,16 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -401,9 +405,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -449,11 +455,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM
|
|||
mem_mode=timing
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -173,6 +174,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.dtb
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -190,7 +192,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -284,6 +285,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.itb
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -301,7 +303,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -385,13 +386,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu0.l2cache.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -473,6 +477,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -490,7 +495,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -584,6 +588,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -601,7 +606,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -685,13 +689,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu1.l2cache.cpu_side
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -722,9 +729,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -806,11 +815,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -860,7 +872,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -1571,11 +1583,14 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM
|
|||
mem_mode=timing
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -173,6 +174,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -190,7 +192,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -284,6 +285,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -301,7 +303,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -360,13 +361,16 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -397,9 +401,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -445,11 +451,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
|
@ -499,7 +508,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM
|
|||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -177,6 +178,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.dtb
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -194,7 +196,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -288,6 +289,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.itb
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -305,7 +307,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -370,6 +371,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -439,6 +441,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -502,9 +505,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -586,11 +591,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -1287,13 +1295,16 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
|
|||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -177,6 +178,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.dtb
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -194,7 +196,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -288,6 +289,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.itb
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -305,7 +307,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -389,13 +390,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu0.l2cache.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -481,6 +485,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -498,7 +503,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -592,6 +596,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -609,7 +614,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -693,13 +697,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu1.l2cache.cpu_side
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -730,9 +737,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -814,11 +823,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -1515,11 +1527,14 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
|
|||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -177,6 +178,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -194,7 +196,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -288,6 +289,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -305,7 +307,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -364,13 +365,16 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -401,9 +405,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -449,11 +455,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
|
|||
mem_mode=timing
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -173,6 +174,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.dtb
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -190,7 +192,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -284,6 +285,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.itb
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -301,7 +303,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu0.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -385,13 +386,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu0.l2cache.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -473,6 +477,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -490,7 +495,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -584,6 +588,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -601,7 +606,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu1.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -685,13 +689,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu1.l2cache.cpu_side
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -722,9 +729,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -806,11 +815,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -860,7 +872,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -1571,11 +1583,14 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ machine_type=VExpress_EMM64
|
|||
mem_mode=timing
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
|
|
@ -173,6 +174,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -190,7 +192,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -284,6 +285,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -301,7 +303,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -360,13 +361,16 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -397,9 +401,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -445,11 +451,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
||||
|
|
@ -499,7 +508,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
boot_release_addr=65528
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
|
|
@ -30,20 +30,21 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
machine_type=VExpress_EMM64
|
||||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.realview.nvmem system.physmem system.realview.vram
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
mmap_using_noreserve=false
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -86,7 +87,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -142,6 +143,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -176,6 +178,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.dtb
|
||||
|
||||
[system.cpu0.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -193,7 +196,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -218,6 +220,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -286,6 +289,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu0.itb
|
||||
|
||||
[system.cpu0.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -303,7 +307,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -368,6 +371,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.dtb
|
||||
|
||||
[system.cpu1.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -437,6 +441,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu1.itb
|
||||
|
||||
[system.cpu1.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -500,9 +505,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=system.realview.pciconfig.pio
|
||||
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
|
||||
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
|
||||
|
|
@ -513,6 +520,7 @@ children=tags
|
|||
addr_ranges=2147483648:2415919103
|
||||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
|
|
@ -548,6 +556,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -582,11 +591,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
|
||||
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
|
||||
|
|
@ -1283,13 +1295,16 @@ port=3456
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
|
||||
|
||||
[system.vncserver]
|
||||
type=VncServer
|
||||
|
|
|
|||
|
|
@ -20,15 +20,16 @@ eventq_index=0
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
smbios_table=system.smbios_table
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -362,8 +363,11 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -818,9 +822,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.pc.pciconfig.pio
|
||||
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
|
||||
|
|
@ -866,11 +872,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
|
||||
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
|
||||
|
|
@ -1208,7 +1217,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1231,7 +1240,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
|||
|
|
@ -20,15 +20,16 @@ eventq_index=0
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=18446744073709551615
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:134217727
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
|
||||
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
||||
smbios_table=system.smbios_table
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
@ -358,8 +359,11 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -814,9 +818,11 @@ sys=system
|
|||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.pc.pciconfig.pio
|
||||
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
|
||||
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
|
||||
|
|
@ -862,11 +868,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=system.membus.badaddr_responder.pio
|
||||
master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
|
||||
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
|
||||
|
|
@ -1204,7 +1213,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1227,7 +1236,7 @@ table_size=65536
|
|||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
@ -1442,7 +1451,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=drivesys.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-server.rcS
|
||||
|
|
@ -191,9 +192,11 @@ slave=drivesys.iobus.master[29]
|
|||
type=NoncoherentXBar
|
||||
clk_domain=drivesys.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=drivesys.tsunami.pciconfig.pio
|
||||
master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave
|
||||
slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
|
||||
|
|
@ -203,11 +206,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=drivesys.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=drivesys
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=drivesys.membus.badaddr_responder.pio
|
||||
master=drivesys.bridge.slave drivesys.physmem.port
|
||||
slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
|
||||
|
|
@ -379,7 +385,7 @@ dma_read_factor=0
|
|||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
eventq_index=0
|
||||
hardware_address=00:90:00:00:00:02
|
||||
hardware_address=00:90:00:00:00:01
|
||||
intr_delay=10000000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
|
|
@ -944,6 +950,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=0:134217727
|
||||
memories=testsys.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
|
||||
readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-stream-client.rcS
|
||||
|
|
@ -1120,9 +1127,11 @@ slave=testsys.iobus.master[29]
|
|||
type=NoncoherentXBar
|
||||
clk_domain=testsys.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
response_latency=2
|
||||
use_default_range=true
|
||||
width=8
|
||||
width=16
|
||||
default=testsys.tsunami.pciconfig.pio
|
||||
master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave
|
||||
slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
|
||||
|
|
@ -1132,11 +1141,14 @@ type=CoherentXBar
|
|||
children=badaddr_responder
|
||||
clk_domain=testsys.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=testsys
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
default=testsys.membus.badaddr_responder.pio
|
||||
master=testsys.bridge.slave testsys.physmem.port
|
||||
slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
|
||||
|
|
@ -1308,7 +1320,7 @@ dma_read_factor=0
|
|||
dma_write_delay=0
|
||||
dma_write_factor=0
|
||||
eventq_index=0
|
||||
hardware_address=00:90:00:00:00:01
|
||||
hardware_address=00:90:00:00:00:02
|
||||
intr_delay=10000000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -638,8 +639,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -693,11 +697,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -728,7 +735,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -587,8 +588,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -642,11 +646,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -677,7 +684,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -569,7 +569,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 25491 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 27316 # The number of ROB writes
|
||||
system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -107,6 +108,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -115,6 +117,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -144,11 +147,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -336,7 +340,6 @@ unit_filter=8
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -506,7 +509,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -321,7 +325,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -490,7 +493,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -338,7 +342,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -510,7 +513,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -360,7 +364,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -464,7 +467,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -305,7 +309,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -409,7 +412,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -207,8 +208,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -262,11 +266,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -638,8 +639,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -693,11 +697,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -728,7 +735,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -587,8 +588,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -642,11 +646,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -677,7 +684,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -569,7 +569,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 11659 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 10686 # The number of ROB writes
|
||||
system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -107,6 +108,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -115,6 +117,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -144,11 +147,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -336,7 +340,6 @@ unit_filter=8
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -506,7 +509,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -321,7 +325,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -490,7 +493,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -338,7 +342,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -510,7 +513,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -360,7 +364,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -464,7 +467,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -111,6 +112,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -119,6 +121,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -163,7 +166,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -216,6 +219,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -305,7 +309,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -409,7 +412,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -82,6 +83,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -122,6 +124,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -171,6 +174,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -204,8 +208,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -220,6 +227,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -228,6 +236,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -257,11 +266,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -167,6 +168,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -184,7 +186,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -661,6 +662,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -678,7 +680,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -737,13 +738,16 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -792,11 +796,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -827,7 +834,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -191,6 +192,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.checker.dtb
|
||||
|
||||
[system.cpu.checker.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -208,7 +210,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[9]
|
||||
|
||||
[system.cpu.checker.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -225,7 +226,7 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[7]
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.checker.isa]
|
||||
type=ArmISA
|
||||
|
|
@ -254,6 +255,7 @@ id_mmfr3=34611729
|
|||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.checker.istage2_mmu]
|
||||
|
|
@ -261,6 +263,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.checker.itb
|
||||
|
||||
[system.cpu.checker.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -278,7 +281,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[8]
|
||||
|
||||
[system.cpu.checker.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -295,7 +297,7 @@ eventq_index=0
|
|||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[6]
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.checker.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -307,6 +309,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -341,6 +344,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -358,7 +362,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -690,6 +693,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -750,6 +754,7 @@ id_mmfr3=34611729
|
|||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
|
|
@ -757,6 +762,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -774,7 +780,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -799,6 +804,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -832,13 +838,16 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -848,6 +857,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -856,6 +866,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -885,11 +896,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -920,7 +934,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -929,6 +943,7 @@ clk_domain=system.clk_domain
|
|||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
|
|
|
|||
|
|
@ -773,7 +773,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5377 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 22770 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21679 # The number of ROB writes
|
||||
system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -157,6 +158,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -191,6 +193,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -208,7 +211,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -498,6 +500,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=1
|
||||
|
|
@ -558,6 +561,7 @@ id_mmfr3=34611729
|
|||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
|
|
@ -565,6 +569,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -582,7 +587,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -607,6 +611,7 @@ children=prefetcher tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=12
|
||||
|
|
@ -628,19 +633,27 @@ mem_side=system.membus.slave[1]
|
|||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
cache_snoop=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cross_pages=false
|
||||
data_accesses_only=false
|
||||
degree=8
|
||||
eventq_index=0
|
||||
inst_tagged=true
|
||||
latency=1
|
||||
on_miss_only=false
|
||||
on_prefetch=true
|
||||
on_read_only=false
|
||||
serial_squash=false
|
||||
size=100
|
||||
max_conf=7
|
||||
min_conf=0
|
||||
on_data=true
|
||||
on_inst=true
|
||||
on_miss=false
|
||||
on_read=true
|
||||
on_write=true
|
||||
queue_filter=true
|
||||
queue_size=32
|
||||
queue_squash=true
|
||||
start_conf=4
|
||||
sys=system
|
||||
table_assoc=4
|
||||
table_sets=16
|
||||
tag_prefetch=true
|
||||
thresh_conf=4
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
|
|
@ -657,13 +670,16 @@ size=1048576
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -673,6 +689,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -681,6 +698,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -710,11 +728,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -745,7 +766,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -754,6 +775,7 @@ clk_domain=system.clk_domain
|
|||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
|
|
|
|||
|
|
@ -655,7 +655,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5377 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 22696 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 16433 # The number of ROB writes
|
||||
system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -122,6 +123,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.checker.dtb
|
||||
|
||||
[system.cpu.checker.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -183,6 +185,7 @@ id_mmfr3=34611729
|
|||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.checker.istage2_mmu]
|
||||
|
|
@ -190,6 +193,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.checker.itb
|
||||
|
||||
[system.cpu.checker.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -233,6 +237,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -250,7 +255,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[6]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -300,6 +304,7 @@ id_mmfr3=34611729
|
|||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
|
|
@ -307,6 +312,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -324,7 +330,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[5]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -351,6 +356,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -359,6 +365,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -388,13 +395,16 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -87,6 +88,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -104,7 +106,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[6]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -154,6 +155,7 @@ id_mmfr3=34611729
|
|||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
|
|
@ -161,6 +163,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -178,7 +181,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.membus.slave[5]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -205,6 +207,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -213,6 +216,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -242,13 +246,16 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -84,6 +85,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -118,6 +120,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
|
|
@ -135,7 +138,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -160,6 +162,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -220,6 +223,7 @@ id_mmfr3=34611729
|
|||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
|
|
@ -227,6 +231,7 @@ type=ArmStage2MMU
|
|||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
|
|
@ -244,7 +249,6 @@ eventq_index=0
|
|||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
|
|
@ -269,6 +273,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -302,13 +307,16 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
|
@ -318,6 +326,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -326,6 +335,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -355,11 +365,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -155,6 +156,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -502,6 +504,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -553,6 +556,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -586,8 +590,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -602,6 +609,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -610,6 +618,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -639,11 +648,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -674,7 +686,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -683,6 +695,7 @@ clk_domain=system.clk_domain
|
|||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
|
|
|
|||
|
|
@ -555,7 +555,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 23990 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21831 # The number of ROB writes
|
||||
system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -109,6 +110,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -117,6 +119,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -146,11 +149,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -113,6 +114,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -121,6 +123,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -165,7 +168,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -218,6 +221,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -307,7 +311,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -411,7 +414,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -82,6 +83,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -122,6 +124,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -173,6 +176,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -206,8 +210,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -222,6 +229,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -230,6 +238,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -259,11 +268,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -156,6 +157,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -503,6 +505,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -551,6 +554,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -584,8 +588,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -600,6 +607,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -608,6 +616,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -637,11 +646,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -672,7 +684,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -681,6 +693,7 @@ clk_domain=system.clk_domain
|
|||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
|
|
|
|||
|
|
@ -556,7 +556,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 22278 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21482 # The number of ROB writes
|
||||
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -107,6 +108,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -115,6 +117,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -144,11 +147,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -106,6 +107,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -114,6 +116,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -143,11 +146,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -110,6 +111,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -118,6 +120,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -162,7 +165,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -215,6 +218,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -304,7 +308,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -408,7 +411,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -82,6 +83,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -122,6 +124,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -170,6 +173,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -203,8 +207,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -219,6 +226,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -227,6 +235,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -256,11 +265,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -620,8 +621,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -675,11 +679,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
|
|
@ -710,7 +717,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
|
|||
|
|
@ -536,7 +536,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 43058 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 44876 # The number of ROB writes
|
||||
system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -179,11 +180,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.mem_ctrls
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -198,7 +199,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -251,6 +252,7 @@ port=system.ruby.dir_cntrl0.memory
|
|||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
|
||||
access_backing_store=false
|
||||
all_instructions=false
|
||||
block_size_bytes=64
|
||||
clk_domain=system.ruby.clk_domain
|
||||
|
|
@ -340,7 +342,6 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -445,7 +446,6 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -240,8 +241,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -295,11 +299,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -155,6 +156,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -502,6 +504,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -556,6 +559,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -589,8 +593,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -605,6 +612,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -613,6 +621,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -626,6 +635,7 @@ useArchPT=false
|
|||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -634,6 +644,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -663,11 +674,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -698,7 +712,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -707,6 +721,7 @@ clk_domain=system.clk_domain
|
|||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
|
|
|
|||
|
|
@ -708,9 +708,6 @@ system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% #
|
|||
system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
|
||||
system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 325 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 130940 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 58397 # The number of ROB writes
|
||||
system.cpu.timesIdled 389 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -155,6 +156,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -502,6 +504,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -550,6 +553,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -583,8 +587,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -599,6 +606,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=insttest
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -607,6 +615,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -636,11 +645,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
@ -671,7 +683,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -680,6 +692,7 @@ clk_domain=system.clk_domain
|
|||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
|
|
|
|||
|
|
@ -533,7 +533,6 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 54715 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 52974 # The number of ROB writes
|
||||
system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -106,6 +107,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=insttest
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -114,6 +116,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -143,11 +146,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -82,6 +83,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -122,6 +124,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -170,6 +173,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -203,8 +207,11 @@ size=2097152
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
|
|
@ -219,6 +226,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=insttest
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -227,6 +235,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -256,11 +265,14 @@ transition_latency=100000000
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -2150,11 +2151,14 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side
|
||||
|
||||
|
|
@ -2185,7 +2189,7 @@ IDD62=0.000000
|
|||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
|
|
@ -2239,11 +2243,14 @@ port=system.membus.master[0]
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||||
|
||||
|
|
|
|||
|
|
@ -563,7 +563,6 @@ system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction
|
||||
system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached
|
||||
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu0.rob.rob_reads 649458 # The number of ROB reads
|
||||
system.cpu0.rob.rob_writes 931043 # The number of ROB writes
|
||||
system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
@ -1087,7 +1086,6 @@ system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction
|
||||
system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached
|
||||
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu1.rob.rob_reads 417798 # The number of ROB reads
|
||||
system.cpu1.rob.rob_writes 534614 # The number of ROB writes
|
||||
system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
@ -1607,7 +1605,6 @@ system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction
|
||||
system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached
|
||||
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu2.rob.rob_reads 416888 # The number of ROB reads
|
||||
system.cpu2.rob.rob_writes 525783 # The number of ROB writes
|
||||
system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
@ -2128,7 +2125,6 @@ system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction
|
||||
system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached
|
||||
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu3.rob.rob_reads 408052 # The number of ROB reads
|
||||
system.cpu3.rob.rob_writes 507784 # The number of ROB writes
|
||||
system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ load_offset=0
|
|||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -86,6 +87,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -126,6 +128,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -176,6 +179,7 @@ eventq_index=0
|
|||
type=LiveProcess
|
||||
cmd=test_atomic 4
|
||||
cwd=
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -184,6 +188,7 @@ eventq_index=0
|
|||
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
|
||||
gid=100
|
||||
input=cin
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -236,6 +241,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -276,6 +282,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -365,6 +372,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -405,6 +413,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -494,6 +503,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -534,6 +544,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
|
|
@ -602,6 +613,7 @@ children=tags
|
|||
addr_ranges=0:18446744073709551615
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
|
|
@ -635,11 +647,14 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.l2c.mem_side
|
||||
|
||||
|
|
@ -660,11 +675,14 @@ port=system.membus.master[0]
|
|||
type=CoherentXBar
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
header_cycles=1
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
response_latency=1
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=8
|
||||
width=32
|
||||
master=system.l2c.cpu_side
|
||||
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue