1067 lines
121 KiB
Plaintext
1067 lines
121 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.672882 # Number of seconds simulated
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sim_ticks 672881519500 # Number of ticks simulated
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final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 171066 # Simulator instruction rate (inst/s)
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host_op_rate 171066 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 66304234 # Simulator tick rate (ticks/s)
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host_mem_usage 296744 # Number of bytes of host memory used
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host_seconds 10148.39 # Real time elapsed on the host
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sim_insts 1736043781 # Number of instructions simulated
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sim_ops 1736043781 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 62400 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 125964544 # Number of bytes read from this memory
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system.physmem.bytes_read::total 126026944 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 62400 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 62400 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 65296192 # Number of bytes written to this memory
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system.physmem.bytes_written::total 65296192 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 975 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1968196 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1969171 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1020253 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1020253 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 92735 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 187201670 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 187294405 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 92735 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 92735 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 97039657 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 97039657 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 97039657 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 92735 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 187201670 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 284334062 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1969171 # Number of read requests accepted
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system.physmem.writeReqs 1020253 # Number of write requests accepted
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system.physmem.readBursts 1969171 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1020253 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 125945600 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue
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system.physmem.bytesWritten 65294336 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 126026944 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 65296192 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 119102 # Per bank write bursts
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system.physmem.perBankRdBursts::1 114505 # Per bank write bursts
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system.physmem.perBankRdBursts::2 116613 # Per bank write bursts
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system.physmem.perBankRdBursts::3 118153 # Per bank write bursts
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system.physmem.perBankRdBursts::4 118234 # Per bank write bursts
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system.physmem.perBankRdBursts::5 117885 # Per bank write bursts
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system.physmem.perBankRdBursts::6 120369 # Per bank write bursts
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system.physmem.perBankRdBursts::7 125035 # Per bank write bursts
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system.physmem.perBankRdBursts::8 127648 # Per bank write bursts
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system.physmem.perBankRdBursts::9 130593 # Per bank write bursts
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system.physmem.perBankRdBursts::10 129299 # Per bank write bursts
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system.physmem.perBankRdBursts::11 130947 # Per bank write bursts
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system.physmem.perBankRdBursts::12 126747 # Per bank write bursts
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system.physmem.perBankRdBursts::13 125863 # Per bank write bursts
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system.physmem.perBankRdBursts::14 123089 # Per bank write bursts
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system.physmem.perBankRdBursts::15 123818 # Per bank write bursts
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system.physmem.perBankWrBursts::0 61291 # Per bank write bursts
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system.physmem.perBankWrBursts::1 61585 # Per bank write bursts
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system.physmem.perBankWrBursts::2 60661 # Per bank write bursts
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system.physmem.perBankWrBursts::3 61360 # Per bank write bursts
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system.physmem.perBankWrBursts::4 61790 # Per bank write bursts
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system.physmem.perBankWrBursts::5 63221 # Per bank write bursts
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system.physmem.perBankWrBursts::6 64275 # Per bank write bursts
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system.physmem.perBankWrBursts::7 65726 # Per bank write bursts
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system.physmem.perBankWrBursts::8 65508 # Per bank write bursts
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system.physmem.perBankWrBursts::9 65914 # Per bank write bursts
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system.physmem.perBankWrBursts::10 65448 # Per bank write bursts
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system.physmem.perBankWrBursts::11 65777 # Per bank write bursts
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system.physmem.perBankWrBursts::12 64328 # Per bank write bursts
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system.physmem.perBankWrBursts::13 64347 # Per bank write bursts
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system.physmem.perBankWrBursts::14 64660 # Per bank write bursts
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system.physmem.perBankWrBursts::15 64333 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 672881423000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1969171 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1020253 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1621016 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 243733 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 72507 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 30617 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 26054 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 27728 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 49537 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 56799 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 59190 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 60318 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 60638 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 60909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 61008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 61063 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 61159 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 61512 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 62241 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 62489 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 64414 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 63055 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 61830 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 60052 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 173 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1777587 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 107.583217 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 82.835342 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 136.553801 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 1382839 77.79% 77.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 271264 15.26% 93.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 53815 3.03% 96.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 21128 1.19% 97.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 12924 0.73% 98.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 6598 0.37% 98.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 5024 0.28% 98.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 3881 0.22% 98.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 20114 1.13% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1777587 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 59878 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 32.821905 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 161.087941 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 59840 99.94% 99.94% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 59878 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 59878 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.038378 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.996376 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.234472 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 31771 53.06% 53.06% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 1453 2.43% 55.49% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 20992 35.06% 90.54% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 4585 7.66% 98.20% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 809 1.35% 99.55% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 191 0.32% 99.87% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::23 14 0.02% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32 1 0.00% 99.97% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::33 1 0.00% 99.97% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::34 1 0.00% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::35 5 0.01% 99.98% # Writes before turning the bus around for reads
|
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system.physmem.wrPerTurnAround::36 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::38 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::39 3 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 59878 # Writes before turning the bus around for reads
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system.physmem.totQLat 40967898000 # Total ticks spent queuing
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|
system.physmem.totMemAccLat 77866023000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 9839500000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 20818.08 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 39568.08 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 187.17 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 97.04 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 187.29 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 97.04 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 2.22 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 794560 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 415972 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 40.38 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 225087.32 # Average gap between requests
|
|
system.physmem.pageHitRate 40.51 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 6515684280 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 3555184875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 7409165400 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3239410320 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 305964835695 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 135337912500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 505971439710 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 751.948773 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 223158478000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 22468940000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 427253308500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 6922850760 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 3777349125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 7940244000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3371641200 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 312976099035 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 129187681500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 508125112260 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 755.149450 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 212887456750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 22468940000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 437523815750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 410709882 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 318998342 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 16277823 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 282986544 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 279468528 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 98.756826 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 26379180 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 646309229 # DTB read hits
|
|
system.cpu.dtb.read_misses 12154225 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 658463454 # DTB read accesses
|
|
system.cpu.dtb.write_hits 218201258 # DTB write hits
|
|
system.cpu.dtb.write_misses 7510092 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 225711350 # DTB write accesses
|
|
system.cpu.dtb.data_hits 864510487 # DTB hits
|
|
system.cpu.dtb.data_misses 19664317 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 884174804 # DTB accesses
|
|
system.cpu.itb.fetch_hits 422619736 # ITB hits
|
|
system.cpu.itb.fetch_misses 46 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 422619782 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 29 # Number of system calls
|
|
system.cpu.numCycles 1345763040 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 433914332 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 3420599858 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 410709882 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 305847708 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 888768265 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 46015780 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 422619736 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 8427195 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 1345692377 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.541888 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.149351 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 718495980 53.39% 53.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 48031633 3.57% 56.96% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 24393578 1.81% 58.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 45267643 3.36% 62.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 143041045 10.63% 72.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 66223895 4.92% 77.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 43793513 3.25% 80.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 29627313 2.20% 83.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 226817777 16.86% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1345692377 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.305187 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.541755 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 355603714 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 406294583 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 525817435 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 34969591 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 23007054 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 62310888 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 895 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 3264812656 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2282 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 23007054 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 373973816 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 212778142 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 7997 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 538797541 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 197127827 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 3181847820 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 1862600 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 20249864 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 150635497 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 31416943 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 2377870821 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 4127617004 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 4127447466 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 169537 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 1001667858 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 209 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 99280769 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 719325488 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 272942348 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 90808423 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 59047660 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2890368727 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 1140831193 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1345692377 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.950220 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.146970 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 540762104 40.18% 40.18% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 169795677 12.62% 52.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 158437148 11.77% 64.58% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 149383051 11.10% 75.68% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 126329288 9.39% 85.06% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 84501883 6.28% 91.34% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 68040537 5.06% 96.40% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 34033784 2.53% 98.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 14408905 1.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1345692377 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 13165371 35.79% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 19036657 51.75% 87.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4585623 12.47% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1719509054 65.52% 65.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 896832 0.03% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 25 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 673114194 25.65% 91.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 230876222 8.80% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2624396643 # Type of FU issued
|
|
system.cpu.iq.rate 1.950118 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 4030049566 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 1296863 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 69569005 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 274729825 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 379855 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 148630 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 112213846 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 321 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 6130129 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 23007054 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 150994559 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 20053347 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 3041642230 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 6687101 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 719325488 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 272942348 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 819254 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 19491023 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 148630 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 10888571 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 8843177 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 19731748 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2578706854 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 658463458 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 45689789 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 151273322 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 884174883 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 315972780 # Number of branches executed
|
|
system.cpu.iew.exec_stores 225711425 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.916167 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2553063246 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2523069590 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1489308587 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1920703402 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.874825 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.775397 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 1005912526 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 16276987 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1206693157 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.508072 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.543192 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 717446911 59.46% 59.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 159887401 13.25% 72.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 79830197 6.62% 79.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 52027392 4.31% 83.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 28503242 2.36% 85.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 19553290 1.62% 87.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 20023421 1.66% 89.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 23140213 1.92% 91.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106281090 8.81% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1206693157 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 605324165 # Number of memory references committed
|
|
system.cpu.commit.loads 444595663 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 214632552 # Number of branches committed
|
|
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 3840325519 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 5790523687 # The number of ROB writes
|
|
system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 70663 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.775190 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.775190 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.290007 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.290007 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3468053564 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2022530151 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 45442 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 563 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 9208756 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4087.479772 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 713775439 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9212852 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 77.476056 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 5132407000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.479772 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.997920 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.997920 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 697 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2970 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1472909430 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1472909430 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 558274718 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 558274718 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 155500717 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 155500717 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 713775435 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 713775435 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 713775435 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 713775435 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 12845064 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 12845064 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5227785 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5227785 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 18072849 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 18072849 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 18072849 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 18072849 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 414536288750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 414536288750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 316664843212 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 316664843212 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 731201131962 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 731201131962 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 731201131962 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 731201131962 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 571119782 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 571119782 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 731848284 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 731848284 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 731848284 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 731848284 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022491 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.022491 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032526 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032526 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.024695 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.024695 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.024695 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.024695 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32272.029844 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 32272.029844 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60573.425114 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 60573.425114 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 40458.542644 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 40458.542644 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 15275634 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 9588635 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1068737 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 67992 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.293165 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 141.025930 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3742849 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3742849 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5511228 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5511228 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3348770 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3348770 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 8859998 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 8859998 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 8859998 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 8859998 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333836 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7333836 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879015 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1879015 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9212851 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9212851 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9212851 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9212851 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180521790750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 180521790750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83364623703 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83364623703 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263886414453 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 263886414453 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263886414453 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 263886414453 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012841 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012841 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.012588 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.012588 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24614.920589 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24614.920589 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.129969 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.129969 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71000 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71000 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 773.497223 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 422618194 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 975 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 433454.557949 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 773.497223 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.377684 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.377684 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 974 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.475586 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 845240447 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 845240447 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 422618194 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 422618194 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 422618194 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 422618194 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 422618194 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 422618194 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1542 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1542 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1542 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1542 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1542 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1542 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 116278500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 116278500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 116278500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 116278500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 116278500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 116278500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 422619736 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 422619736 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 422619736 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 422619736 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 422619736 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 422619736 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75407.587549 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 75407.587549 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 75407.587549 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 75407.587549 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 435 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 62.142857 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 567 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 567 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 567 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 567 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 567 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 567 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 975 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 975 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79199000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 79199000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79199000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 79199000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79199000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 79199000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81229.743590 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81229.743590 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 1936457 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31413.219008 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 9110872 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1966244 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.633643 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 28158140750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14523.555801 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.886283 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 16862.776924 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.443224 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.514611 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.958655 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29787 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 973 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 615 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17524 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10518 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 107498682 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 107498682 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6136947 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6136947 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3742849 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3742849 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107709 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1107709 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7244656 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7244656 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7244656 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7244656 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 975 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1196875 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1197850 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 771321 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 771321 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 975 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1968196 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1969171 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 975 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1968196 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1969171 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78215000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 107761725750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 107839940750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69308457750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 69308457750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 78215000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 177070183500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 177148398500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 78215000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 177070183500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 177148398500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 975 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7333822 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7334797 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3742849 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3742849 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879030 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1879030 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 975 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9212852 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9213827 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 975 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9212852 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9213827 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163199 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.163311 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.410489 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.410489 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.213636 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.213719 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.213636 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.213719 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80220.512821 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 90035.906632 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 90027.917310 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89856.827119 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89856.827119 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 89960.901567 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 89960.901567 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1020253 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1020253 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196875 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1197850 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771321 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 771321 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1968196 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1969171 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1968196 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1969171 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66029500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 92659024750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92725054250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59593481750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59593481750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66029500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 152252506500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 152318536000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66029500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 152252506500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 152318536000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163199 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163311 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410489 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410489 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.213719 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.213719 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67722.564103 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77417.461932 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77409.570689 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77261.583374 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77261.583374 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7334797 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7334797 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 3742849 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1879030 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1879030 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1950 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168553 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 22170503 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829164864 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 829227264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 12956676 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 12956676 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 12956676 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10221187000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1642000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 14136511250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 1197850 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1197850 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1020253 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 771321 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 771321 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958595 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 4958595 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191323136 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 191323136 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 2989424 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 2989424 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 2989424 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 7771933000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 10726595500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.6 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|