inorder: initialize res. req. vectors based on resource bandwidth

first change in an optimization that will stop InOrder from allocating new memory for every instruction's
request to a resource. This gets expensive since every instruction needs to access ~10 requests before
graduation. Instead, the plan is to allocate just enough resource request objects to satisfy each resource's
bandwidth (e.g. the execution unit would need to allocate 3 resource request objects for a 1-issue pipeline
since on any given cycle it could have 2 read requests and 1 write request) and then let the instructions
contend and reuse those allocated requests. The end result is a smaller memory footprint for the InOrder model
and increased simulation performance
This commit is contained in:
Korey Sewell 2011-02-18 14:27:52 -05:00
parent 2971b8401a
commit 991d0185c6
5 changed files with 28 additions and 0 deletions

View file

@ -40,6 +40,8 @@ Resource::Resource(string res_name, int res_id, int res_width,
: resName(res_name), id(res_id), : resName(res_name), id(res_id),
width(res_width), latency(res_latency), cpu(_cpu) width(res_width), latency(res_latency), cpu(_cpu)
{ {
reqs.resize(width);
// Use to deny a instruction a resource. // Use to deny a instruction a resource.
deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0); deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0);
} }
@ -57,6 +59,10 @@ Resource::init()
// Set Up Resource Events to Appropriate Resource BandWidth // Set Up Resource Events to Appropriate Resource BandWidth
resourceEvent = new ResourceEvent[width]; resourceEvent = new ResourceEvent[width];
for (int i = 0; i < width; i++) {
reqs[i] = new ResourceRequest(this, NULL, 0, 0, 0, 0);
}
initSlots(); initSlots();
} }

View file

@ -224,6 +224,8 @@ class Resource {
/** Mapping of slot-numbers to the resource-request pointers */ /** Mapping of slot-numbers to the resource-request pointers */
std::map<int, ResReqPtr> reqMap; std::map<int, ResReqPtr> reqMap;
std::vector<ResReqPtr> reqs;
/** A list of all the available execution slots for this resource. /** A list of all the available execution slots for this resource.
* This correlates with the actual resource event idx. * This correlates with the actual resource event idx.
*/ */

View file

@ -133,6 +133,11 @@ CacheUnit::getPort(const string &if_name, int idx)
void void
CacheUnit::init() CacheUnit::init()
{ {
for (int i = 0; i < width; i++) {
reqs[i] = new CacheRequest(this, NULL, 0, 0, 0, 0, 0,
MemCmd::Command(0), 0, 0, 0);
}
// Currently Used to Model TLB Latency. Eventually // Currently Used to Model TLB Latency. Eventually
// Switch to Timing TLB translations. // Switch to Timing TLB translations.
resourceEvent = new CacheUnitEvent[width]; resourceEvent = new CacheUnitEvent[width];

View file

@ -88,6 +88,19 @@ UseDefUnit::regStats()
Resource::regStats(); Resource::regStats();
} }
void
UseDefUnit::init()
{
// Set Up Resource Events to Appropriate Resource BandWidth
resourceEvent = new ResourceEvent[width];
for (int i = 0; i < width; i++) {
reqs[i] = new UseDefRequest(this, NULL, 0, 0, 0, 0, 0);
}
initSlots();
}
ResReqPtr ResReqPtr
UseDefUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, UseDefUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
int slot_num, unsigned cmd) int slot_num, unsigned cmd)

View file

@ -56,6 +56,8 @@ class UseDefUnit : public Resource {
UseDefUnit(std::string res_name, int res_id, int res_width, UseDefUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
void init();
ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
int res_idx, int slot_num, int res_idx, int slot_num,
unsigned cmd); unsigned cmd);