Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc arch/alpha/faults.cc: Hand merge. --HG-- rename : arch/alpha/linux_process.cc => arch/alpha/linux/process.cc rename : arch/alpha/tru64_process.cc => arch/alpha/tru64/process.cc extra : convert_revision : 6ea1fae5be0ebd02eff330423d16da63b790516d
This commit is contained in:
commit
97c4a84985
36 changed files with 1793 additions and 956 deletions
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@ -212,11 +212,6 @@ mysql_sources = Split('''
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# Full-system sources
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# Full-system sources
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full_system_sources = Split('''
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full_system_sources = Split('''
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arch/alpha/freebsd/system.cc
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arch/alpha/linux/system.cc
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arch/alpha/system.cc
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arch/alpha/tru64/system.cc
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base/crc.cc
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base/crc.cc
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base/inet.cc
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base/inet.cc
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base/remote_gdb.cc
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base/remote_gdb.cc
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|
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@ -56,14 +56,18 @@ full_system_sources = Split('''
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osfpal.cc
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osfpal.cc
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stacktrace.cc
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stacktrace.cc
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vtophys.cc
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vtophys.cc
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system.cc
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freebsd/system.cc
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linux/system.cc
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tru64/system.cc
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''')
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''')
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# Syscall emulation (non-full-system) sources
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# Syscall emulation (non-full-system) sources
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syscall_emulation_sources = Split('''
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syscall_emulation_sources = Split('''
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common_syscall_emul.cc
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common_syscall_emul.cc
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linux_process.cc
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linux/process.cc
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tru64_process.cc
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tru64/process.cc
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process.cc
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process.cc
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''')
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''')
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@ -30,84 +30,80 @@
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#include "cpu/exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/base.hh"
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#include "cpu/base.hh"
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#include "base/trace.hh"
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#include "base/trace.hh"
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#include "kern/kernel_stats.hh"
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namespace AlphaISA
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namespace AlphaISA
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{
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{
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FaultName MachineCheckFault::_name = "mchk";
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FaultName MachineCheckFault::_name = "mchk";
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FaultVect MachineCheckFault::_vect = 0x0401;
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FaultVect MachineCheckFault::_vect = 0x0401;
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FaultStat MachineCheckFault::_stat;
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FaultStat MachineCheckFault::_count;
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FaultName AlignmentFault::_name = "unalign";
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FaultName AlignmentFault::_name = "unalign";
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FaultVect AlignmentFault::_vect = 0x0301;
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FaultVect AlignmentFault::_vect = 0x0301;
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FaultStat AlignmentFault::_stat;
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FaultStat AlignmentFault::_count;
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FaultName ResetFault::_name = "reset";
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FaultName ResetFault::_name = "reset";
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FaultVect ResetFault::_vect = 0x0001;
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FaultVect ResetFault::_vect = 0x0001;
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FaultStat ResetFault::_stat;
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FaultStat ResetFault::_count;
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FaultName ArithmeticFault::_name = "arith";
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FaultName ArithmeticFault::_name = "arith";
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FaultVect ArithmeticFault::_vect = 0x0501;
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FaultVect ArithmeticFault::_vect = 0x0501;
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FaultStat ArithmeticFault::_stat;
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FaultStat ArithmeticFault::_count;
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FaultName InterruptFault::_name = "interrupt";
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FaultName InterruptFault::_name = "interrupt";
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FaultVect InterruptFault::_vect = 0x0101;
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FaultVect InterruptFault::_vect = 0x0101;
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FaultStat InterruptFault::_stat;
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FaultStat InterruptFault::_count;
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultStat NDtbMissFault::_stat;
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FaultStat NDtbMissFault::_count;
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultStat PDtbMissFault::_stat;
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FaultStat PDtbMissFault::_count;
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FaultName DtbPageFault::_name = "dfault";
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FaultName DtbPageFault::_name = "dfault";
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultStat DtbPageFault::_stat;
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FaultStat DtbPageFault::_count;
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FaultName DtbAcvFault::_name = "dfault";
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FaultName DtbAcvFault::_name = "dfault";
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultStat DtbAcvFault::_stat;
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FaultStat DtbAcvFault::_count;
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FaultName ItbMissFault::_name = "itbmiss";
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FaultName ItbMissFault::_name = "itbmiss";
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultStat ItbMissFault::_stat;
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FaultStat ItbMissFault::_count;
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FaultName ItbPageFault::_name = "itbmiss";
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FaultName ItbPageFault::_name = "itbmiss";
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultStat ItbPageFault::_stat;
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FaultStat ItbPageFault::_count;
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultStat ItbAcvFault::_stat;
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FaultStat ItbAcvFault::_count;
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultStat UnimplementedOpcodeFault::_stat;
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FaultStat UnimplementedOpcodeFault::_count;
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FaultName FloatEnableFault::_name = "fen";
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FaultName FloatEnableFault::_name = "fen";
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultStat FloatEnableFault::_stat;
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FaultStat FloatEnableFault::_count;
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FaultName PalFault::_name = "pal";
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FaultName PalFault::_name = "pal";
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FaultVect PalFault::_vect = 0x2001;
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FaultVect PalFault::_vect = 0x2001;
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FaultStat PalFault::_stat;
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FaultStat PalFault::_count;
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FaultName IntegerOverflowFault::_name = "intover";
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FaultName IntegerOverflowFault::_name = "intover";
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultStat IntegerOverflowFault::_stat;
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FaultStat IntegerOverflowFault::_count;
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void AlphaFault::invoke(ExecContext * xc)
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void AlphaFault::invoke(ExecContext * xc)
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{
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{
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DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC());
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FaultBase::invoke(xc);
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xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
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countStat()++;
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assert(!xc->misspeculating());
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xc->getCpuPtr()->kernelStats->fault(this);
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// exception restart address
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// exception restart address
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if (setRestartAddress() || !xc->inPalMode())
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if (setRestartAddress() || !xc->inPalMode())
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@ -125,43 +121,11 @@ void AlphaFault::invoke(ExecContext * xc)
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void ArithmeticFault::invoke(ExecContext * xc)
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void ArithmeticFault::invoke(ExecContext * xc)
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{
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{
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DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC());
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FaultBase::invoke(xc);
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xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
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assert(!xc->misspeculating());
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xc->getCpuPtr()->kernelStats->fault(this);
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panic("Arithmetic traps are unimplemented!");
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panic("Arithmetic traps are unimplemented!");
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}
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}
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/*void ArithmeticFault::invoke(ExecContext * xc)
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{
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panic("Arithmetic traps are unimplemented!");
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}*/
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#endif
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#endif
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} // namespace AlphaISA
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} // namespace AlphaISA
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/*Fault * ListOfFaults[] = {
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(Fault *)&NoFault,
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(Fault *)&ResetFault,
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(Fault *)&MachineCheckFault,
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(Fault *)&ArithmeticFault,
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(Fault *)&InterruptFault,
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(Fault *)&NDtbMissFault,
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(Fault *)&PDtbMissFault,
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(Fault *)&AlignmentFault,
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(Fault *)&DtbPageFault,
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(Fault *)&DtbAcvFault,
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(Fault *)&ItbMissFault,
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(Fault *)&ItbPageFault,
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(Fault *)&ItbAcvFault,
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(Fault *)&UnimplementedOpcodeFault,
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(Fault *)&FloatEnableFault,
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(Fault *)&PalFault,
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(Fault *)&IntegerOverflowFault,
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};
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int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
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@ -38,7 +38,7 @@ namespace AlphaISA
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typedef const Addr FaultVect;
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typedef const Addr FaultVect;
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class AlphaFault : public virtual FaultBase
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class AlphaFault : public FaultBase
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{
|
{
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protected:
|
protected:
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virtual bool skipFaultingInstruction() {return false;}
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virtual bool skipFaultingInstruction() {return false;}
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|
@ -48,6 +48,7 @@ class AlphaFault : public virtual FaultBase
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void invoke(ExecContext * xc);
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void invoke(ExecContext * xc);
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#endif
|
#endif
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virtual FaultVect vect() = 0;
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virtual FaultVect vect() = 0;
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virtual FaultStat & countStat() = 0;
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};
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};
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class MachineCheckFault : public AlphaFault
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class MachineCheckFault : public AlphaFault
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@ -55,11 +56,11 @@ class MachineCheckFault : public AlphaFault
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private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
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||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
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||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
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||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
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FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
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||||||
bool isMachineCheckFault() {return true;}
|
bool isMachineCheckFault() {return true;}
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||||||
};
|
};
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|
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||||||
|
@ -68,11 +69,11 @@ class AlignmentFault : public AlphaFault
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||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
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static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
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||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
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||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
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||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
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||||||
bool isAlignmentFault() {return true;}
|
bool isAlignmentFault() {return true;}
|
||||||
};
|
};
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||||||
|
|
||||||
|
@ -91,11 +92,11 @@ class ResetFault : public AlphaFault
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||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class ArithmeticFault : public AlphaFault
|
class ArithmeticFault : public AlphaFault
|
||||||
|
@ -105,11 +106,11 @@ class ArithmeticFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
void invoke(ExecContext * xc);
|
void invoke(ExecContext * xc);
|
||||||
#endif
|
#endif
|
||||||
|
@ -122,11 +123,11 @@ class InterruptFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class NDtbMissFault : public AlphaFault
|
class NDtbMissFault : public AlphaFault
|
||||||
|
@ -134,11 +135,11 @@ class NDtbMissFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class PDtbMissFault : public AlphaFault
|
class PDtbMissFault : public AlphaFault
|
||||||
|
@ -146,11 +147,11 @@ class PDtbMissFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class DtbPageFault : public AlphaFault
|
class DtbPageFault : public AlphaFault
|
||||||
|
@ -158,11 +159,11 @@ class DtbPageFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class DtbAcvFault : public AlphaFault
|
class DtbAcvFault : public AlphaFault
|
||||||
|
@ -170,11 +171,11 @@ class DtbAcvFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class ItbMissFault : public AlphaFault
|
class ItbMissFault : public AlphaFault
|
||||||
|
@ -182,11 +183,11 @@ class ItbMissFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class ItbPageFault : public AlphaFault
|
class ItbPageFault : public AlphaFault
|
||||||
|
@ -194,11 +195,11 @@ class ItbPageFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class ItbAcvFault : public AlphaFault
|
class ItbAcvFault : public AlphaFault
|
||||||
|
@ -206,11 +207,11 @@ class ItbAcvFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class UnimplementedOpcodeFault : public AlphaFault
|
class UnimplementedOpcodeFault : public AlphaFault
|
||||||
|
@ -218,11 +219,11 @@ class UnimplementedOpcodeFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class FloatEnableFault : public AlphaFault
|
class FloatEnableFault : public AlphaFault
|
||||||
|
@ -230,11 +231,11 @@ class FloatEnableFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class PalFault : public AlphaFault
|
class PalFault : public AlphaFault
|
||||||
|
@ -244,11 +245,11 @@ class PalFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
class IntegerOverflowFault : public AlphaFault
|
class IntegerOverflowFault : public AlphaFault
|
||||||
|
@ -256,11 +257,11 @@ class IntegerOverflowFault : public AlphaFault
|
||||||
private:
|
private:
|
||||||
static FaultName _name;
|
static FaultName _name;
|
||||||
static FaultVect _vect;
|
static FaultVect _vect;
|
||||||
static FaultStat _stat;
|
static FaultStat _count;
|
||||||
public:
|
public:
|
||||||
FaultName name() {return _name;}
|
FaultName name() {return _name;}
|
||||||
FaultVect vect() {return _vect;}
|
FaultVect vect() {return _vect;}
|
||||||
FaultStat & stat() {return _stat;}
|
FaultStat & countStat() {return _count;}
|
||||||
};
|
};
|
||||||
|
|
||||||
} // AlphaISA namespace
|
} // AlphaISA namespace
|
||||||
|
|
|
@ -27,7 +27,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "arch/alpha/common_syscall_emul.hh"
|
#include "arch/alpha/common_syscall_emul.hh"
|
||||||
#include "arch/alpha/linux_process.hh"
|
#include "arch/alpha/linux/process.hh"
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
|
@ -31,8 +31,8 @@
|
||||||
|
|
||||||
#include <string>
|
#include <string>
|
||||||
|
|
||||||
#include "arch/alpha/linux_process.hh"
|
#include "arch/alpha/linux/process.hh"
|
||||||
#include "arch/alpha/tru64_process.hh"
|
#include "arch/alpha/tru64/process.hh"
|
||||||
#include "base/loader/object_file.hh"
|
#include "base/loader/object_file.hh"
|
||||||
|
|
||||||
namespace AlphaISA
|
namespace AlphaISA
|
||||||
|
|
|
@ -37,6 +37,7 @@
|
||||||
#include "sim/byteswap.hh"
|
#include "sim/byteswap.hh"
|
||||||
#include "sim/builder.hh"
|
#include "sim/builder.hh"
|
||||||
|
|
||||||
|
|
||||||
using namespace LittleEndianGuest;
|
using namespace LittleEndianGuest;
|
||||||
|
|
||||||
AlphaSystem::AlphaSystem(Params *p)
|
AlphaSystem::AlphaSystem(Params *p)
|
||||||
|
|
|
@ -28,7 +28,7 @@
|
||||||
|
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/alpha/isa_traits.hh"
|
||||||
#include "arch/alpha/common_syscall_emul.hh"
|
#include "arch/alpha/common_syscall_emul.hh"
|
||||||
#include "arch/alpha/tru64_process.hh"
|
#include "arch/alpha/tru64/process.hh"
|
||||||
#include "cpu/exec_context.hh"
|
#include "cpu/exec_context.hh"
|
||||||
#include "kern/tru64/tru64.hh"
|
#include "kern/tru64/tru64.hh"
|
||||||
#include "mem/functional/functional.hh"
|
#include "mem/functional/functional.hh"
|
248
arch/sparc/faults.cc
Normal file
248
arch/sparc/faults.cc
Normal file
|
@ -0,0 +1,248 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arch/sparc/faults.hh"
|
||||||
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/base.hh"
|
||||||
|
#include "base/trace.hh"
|
||||||
|
|
||||||
|
namespace SparcISA
|
||||||
|
{
|
||||||
|
|
||||||
|
FaultName InternalProcessorError::_name = "intprocerr";
|
||||||
|
TrapType InternalProcessorError::_trapType = 0x029;
|
||||||
|
FaultPriority InternalProcessorError::_priority = 4;
|
||||||
|
FaultStat InternalProcessorError::_count;
|
||||||
|
|
||||||
|
FaultName MemAddressNotAligned::_name = "unalign";
|
||||||
|
TrapType MemAddressNotAligned::_trapType = 0x034;
|
||||||
|
FaultPriority MemAddressNotAligned::_priority = 10;
|
||||||
|
FaultStat MemAddressNotAligned::_count;
|
||||||
|
|
||||||
|
FaultName PowerOnReset::_name = "pow_reset";
|
||||||
|
TrapType PowerOnReset::_trapType = 0x001;
|
||||||
|
FaultPriority PowerOnReset::_priority = 0;
|
||||||
|
FaultStat PowerOnReset::_count;
|
||||||
|
|
||||||
|
FaultName WatchDogReset::_name = "watch_dog_reset";
|
||||||
|
TrapType WatchDogReset::_trapType = 0x002;
|
||||||
|
FaultPriority WatchDogReset::_priority = 1;
|
||||||
|
FaultStat WatchDogReset::_count;
|
||||||
|
|
||||||
|
FaultName ExternallyInitiatedReset::_name = "extern_reset";
|
||||||
|
TrapType ExternallyInitiatedReset::_trapType = 0x003;
|
||||||
|
FaultPriority ExternallyInitiatedReset::_priority = 1;
|
||||||
|
FaultStat ExternallyInitiatedReset::_count;
|
||||||
|
|
||||||
|
FaultName SoftwareInitiatedReset::_name = "software_reset";
|
||||||
|
TrapType SoftwareInitiatedReset::_trapType = 0x004;
|
||||||
|
FaultPriority SoftwareInitiatedReset::_priority = 1;
|
||||||
|
FaultStat SoftwareInitiatedReset::_count;
|
||||||
|
|
||||||
|
FaultName REDStateException::_name = "red_counte";
|
||||||
|
TrapType REDStateException::_trapType = 0x005;
|
||||||
|
FaultPriority REDStateException::_priority = 1;
|
||||||
|
FaultStat REDStateException::_count;
|
||||||
|
|
||||||
|
FaultName InstructionAccessException::_name = "inst_access";
|
||||||
|
TrapType InstructionAccessException::_trapType = 0x008;
|
||||||
|
FaultPriority InstructionAccessException::_priority = 5;
|
||||||
|
FaultStat InstructionAccessException::_count;
|
||||||
|
|
||||||
|
FaultName InstructionAccessMMUMiss::_name = "inst_mmu";
|
||||||
|
TrapType InstructionAccessMMUMiss::_trapType = 0x009;
|
||||||
|
FaultPriority InstructionAccessMMUMiss::_priority = 2;
|
||||||
|
FaultStat InstructionAccessMMUMiss::_count;
|
||||||
|
|
||||||
|
FaultName InstructionAccessError::_name = "inst_error";
|
||||||
|
TrapType InstructionAccessError::_trapType = 0x00A;
|
||||||
|
FaultPriority InstructionAccessError::_priority = 3;
|
||||||
|
FaultStat InstructionAccessError::_count;
|
||||||
|
|
||||||
|
FaultName IllegalInstruction::_name = "illegal_inst";
|
||||||
|
TrapType IllegalInstruction::_trapType = 0x010;
|
||||||
|
FaultPriority IllegalInstruction::_priority = 7;
|
||||||
|
FaultStat IllegalInstruction::_count;
|
||||||
|
|
||||||
|
FaultName PrivelegedOpcode::_name = "priv_opcode";
|
||||||
|
TrapType PrivelegedOpcode::_trapType = 0x011;
|
||||||
|
FaultPriority PrivelegedOpcode::_priority = 6;
|
||||||
|
FaultStat PrivelegedOpcode::_count;
|
||||||
|
|
||||||
|
FaultName UnimplementedLDD::_name = "unimp_ldd";
|
||||||
|
TrapType UnimplementedLDD::_trapType = 0x012;
|
||||||
|
FaultPriority UnimplementedLDD::_priority = 6;
|
||||||
|
FaultStat UnimplementedLDD::_count;
|
||||||
|
|
||||||
|
FaultName UnimplementedSTD::_name = "unimp_std";
|
||||||
|
TrapType UnimplementedSTD::_trapType = 0x013;
|
||||||
|
FaultPriority UnimplementedSTD::_priority = 6;
|
||||||
|
FaultStat UnimplementedSTD::_count;
|
||||||
|
|
||||||
|
FaultName FpDisabled::_name = "fp_disabled";
|
||||||
|
TrapType FpDisabled::_trapType = 0x020;
|
||||||
|
FaultPriority FpDisabled::_priority = 8;
|
||||||
|
FaultStat FpDisabled::_count;
|
||||||
|
|
||||||
|
FaultName FpExceptionIEEE754::_name = "fp_754";
|
||||||
|
TrapType FpExceptionIEEE754::_trapType = 0x021;
|
||||||
|
FaultPriority FpExceptionIEEE754::_priority = 11;
|
||||||
|
FaultStat FpExceptionIEEE754::_count;
|
||||||
|
|
||||||
|
FaultName FpExceptionOther::_name = "fp_other";
|
||||||
|
TrapType FpExceptionOther::_trapType = 0x022;
|
||||||
|
FaultPriority FpExceptionOther::_priority = 11;
|
||||||
|
FaultStat FpExceptionOther::_count;
|
||||||
|
|
||||||
|
FaultName TagOverflow::_name = "tag_overflow";
|
||||||
|
TrapType TagOverflow::_trapType = 0x023;
|
||||||
|
FaultPriority TagOverflow::_priority = 14;
|
||||||
|
FaultStat TagOverflow::_count;
|
||||||
|
|
||||||
|
FaultName DivisionByZero::_name = "div_by_zero";
|
||||||
|
TrapType DivisionByZero::_trapType = 0x028;
|
||||||
|
FaultPriority DivisionByZero::_priority = 15;
|
||||||
|
FaultStat DivisionByZero::_count;
|
||||||
|
|
||||||
|
FaultName DataAccessException::_name = "data_access";
|
||||||
|
TrapType DataAccessException::_trapType = 0x030;
|
||||||
|
FaultPriority DataAccessException::_priority = 12;
|
||||||
|
FaultStat DataAccessException::_count;
|
||||||
|
|
||||||
|
FaultName DataAccessMMUMiss::_name = "data_mmu";
|
||||||
|
TrapType DataAccessMMUMiss::_trapType = 0x031;
|
||||||
|
FaultPriority DataAccessMMUMiss::_priority = 12;
|
||||||
|
FaultStat DataAccessMMUMiss::_count;
|
||||||
|
|
||||||
|
FaultName DataAccessError::_name = "data_error";
|
||||||
|
TrapType DataAccessError::_trapType = 0x032;
|
||||||
|
FaultPriority DataAccessError::_priority = 12;
|
||||||
|
FaultStat DataAccessError::_count;
|
||||||
|
|
||||||
|
FaultName DataAccessProtection::_name = "data_protection";
|
||||||
|
TrapType DataAccessProtection::_trapType = 0x033;
|
||||||
|
FaultPriority DataAccessProtection::_priority = 12;
|
||||||
|
FaultStat DataAccessProtection::_count;
|
||||||
|
|
||||||
|
FaultName LDDFMemAddressNotAligned::_name = "unalign_lddf";
|
||||||
|
TrapType LDDFMemAddressNotAligned::_trapType = 0x035;
|
||||||
|
FaultPriority LDDFMemAddressNotAligned::_priority = 10;
|
||||||
|
FaultStat LDDFMemAddressNotAligned::_count;
|
||||||
|
|
||||||
|
FaultName STDFMemAddressNotAligned::_name = "unalign_stdf";
|
||||||
|
TrapType STDFMemAddressNotAligned::_trapType = 0x036;
|
||||||
|
FaultPriority STDFMemAddressNotAligned::_priority = 10;
|
||||||
|
FaultStat STDFMemAddressNotAligned::_count;
|
||||||
|
|
||||||
|
FaultName PrivelegedAction::_name = "priv_action";
|
||||||
|
TrapType PrivelegedAction::_trapType = 0x037;
|
||||||
|
FaultPriority PrivelegedAction::_priority = 11;
|
||||||
|
FaultStat PrivelegedAction::_count;
|
||||||
|
|
||||||
|
FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf";
|
||||||
|
TrapType LDQFMemAddressNotAligned::_trapType = 0x038;
|
||||||
|
FaultPriority LDQFMemAddressNotAligned::_priority = 10;
|
||||||
|
FaultStat LDQFMemAddressNotAligned::_count;
|
||||||
|
|
||||||
|
FaultName STQFMemAddressNotAligned::_name = "unalign_stqf";
|
||||||
|
TrapType STQFMemAddressNotAligned::_trapType = 0x039;
|
||||||
|
FaultPriority STQFMemAddressNotAligned::_priority = 10;
|
||||||
|
FaultStat STQFMemAddressNotAligned::_count;
|
||||||
|
|
||||||
|
FaultName AsyncDataError::_name = "async_data";
|
||||||
|
TrapType AsyncDataError::_trapType = 0x040;
|
||||||
|
FaultPriority AsyncDataError::_priority = 2;
|
||||||
|
FaultStat AsyncDataError::_count;
|
||||||
|
|
||||||
|
//The enumerated faults
|
||||||
|
|
||||||
|
FaultName CleanWindow::_name = "clean_win";
|
||||||
|
TrapType CleanWindow::_baseTrapType = 0x024;
|
||||||
|
FaultPriority CleanWindow::_priority = 10;
|
||||||
|
FaultStat CleanWindow::_count;
|
||||||
|
|
||||||
|
FaultName InterruptLevelN::_name = "interrupt_n";
|
||||||
|
TrapType InterruptLevelN::_baseTrapType = 0x041;
|
||||||
|
FaultStat InterruptLevelN::_count;
|
||||||
|
|
||||||
|
FaultName SpillNNormal::_name = "spill_n_normal";
|
||||||
|
TrapType SpillNNormal::_baseTrapType = 0x080;
|
||||||
|
FaultPriority SpillNNormal::_priority = 9;
|
||||||
|
FaultStat SpillNNormal::_count;
|
||||||
|
|
||||||
|
FaultName SpillNOther::_name = "spill_n_other";
|
||||||
|
TrapType SpillNOther::_baseTrapType = 0x0A0;
|
||||||
|
FaultPriority SpillNOther::_priority = 9;
|
||||||
|
FaultStat SpillNOther::_count;
|
||||||
|
|
||||||
|
FaultName FillNNormal::_name = "fill_n_normal";
|
||||||
|
TrapType FillNNormal::_baseTrapType = 0x0C0;
|
||||||
|
FaultPriority FillNNormal::_priority = 9;
|
||||||
|
FaultStat FillNNormal::_count;
|
||||||
|
|
||||||
|
FaultName FillNOther::_name = "fill_n_other";
|
||||||
|
TrapType FillNOther::_baseTrapType = 0x0E0;
|
||||||
|
FaultPriority FillNOther::_priority = 9;
|
||||||
|
FaultStat FillNOther::_count;
|
||||||
|
|
||||||
|
FaultName TrapInstruction::_name = "trap_inst_n";
|
||||||
|
TrapType TrapInstruction::_baseTrapType = 0x100;
|
||||||
|
FaultPriority TrapInstruction::_priority = 16;
|
||||||
|
FaultStat TrapInstruction::_count;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
|
||||||
|
void SparcFault::invoke(ExecContext * xc)
|
||||||
|
{
|
||||||
|
FaultBase::invoke(xc);
|
||||||
|
countStat()++;
|
||||||
|
|
||||||
|
//Use the SPARC trap state machine
|
||||||
|
/*// exception restart address
|
||||||
|
if (setRestartAddress() || !xc->inPalMode())
|
||||||
|
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
|
||||||
|
|
||||||
|
if (skipFaultingInstruction()) {
|
||||||
|
// traps... skip faulting instruction.
|
||||||
|
xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
|
||||||
|
xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!xc->inPalMode())
|
||||||
|
AlphaISA::swap_palshadow(&(xc->regs), true);
|
||||||
|
|
||||||
|
xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
|
||||||
|
xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
} // namespace SparcISA
|
||||||
|
|
587
arch/sparc/faults.hh
Normal file
587
arch/sparc/faults.hh
Normal file
|
@ -0,0 +1,587 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ALPHA_FAULTS_HH__
|
||||||
|
#define __ALPHA_FAULTS_HH__
|
||||||
|
|
||||||
|
#include "sim/faults.hh"
|
||||||
|
|
||||||
|
// The design of the "name" and "vect" functions is in sim/faults.hh
|
||||||
|
|
||||||
|
namespace SparcISA
|
||||||
|
{
|
||||||
|
|
||||||
|
typedef const uint32_t TrapType;
|
||||||
|
typedef const uint32_t FaultPriority;
|
||||||
|
|
||||||
|
class SparcFault : public FaultBase
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
void invoke(ExecContext * xc);
|
||||||
|
#endif
|
||||||
|
virtual TrapType trapType() = 0;
|
||||||
|
virtual FaultPriority priority() = 0;
|
||||||
|
virtual FaultStat & countStat() = 0;
|
||||||
|
};
|
||||||
|
|
||||||
|
class InternalProcessorError : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
bool isMachineCheckFault() {return true;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class MemAddressNotAligned : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
bool isAlignmentFault() {return true;}
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline Fault genMachineCheckFault()
|
||||||
|
{
|
||||||
|
return new InternalProcessorError;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline Fault genAlignmentFault()
|
||||||
|
{
|
||||||
|
return new MemAddressNotAligned;
|
||||||
|
}
|
||||||
|
|
||||||
|
class PowerOnReset : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class WatchDogReset : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class ExternallyInitiatedReset : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class SoftwareInitiatedReset : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class REDStateException : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class InstructionAccessException : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class InstructionAccessMMUMiss : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class InstructionAccessError : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class IllegalInstruction : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class PrivelegedOpcode : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class UnimplementedLDD : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class UnimplementedSTD : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class FpDisabled : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class FpExceptionIEEE754 : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class FpExceptionOther : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class TagOverflow : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class DivisionByZero : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class DataAccessException : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class DataAccessMMUMiss : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class DataAccessError : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class DataAccessProtection : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class LDDFMemAddressNotAligned : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class STDFMemAddressNotAligned : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class PrivelegedAction : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class LDQFMemAddressNotAligned : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class STQFMemAddressNotAligned : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class AsyncDataError : public SparcFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _trapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
public:
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
TrapType trapType() {return _trapType;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class EnumeratedFault : public SparcFault
|
||||||
|
{
|
||||||
|
protected:
|
||||||
|
uint32_t _n;
|
||||||
|
virtual TrapType baseTrapType() = 0;
|
||||||
|
public:
|
||||||
|
EnumeratedFault(uint32_t n) : SparcFault() {_n = n;}
|
||||||
|
TrapType trapType() {return baseTrapType() + _n;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class CleanWindow : public EnumeratedFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _baseTrapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
TrapType baseTrapType() {return _baseTrapType;}
|
||||||
|
public:
|
||||||
|
CleanWindow(uint32_t n) : EnumeratedFault(n) {;}
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class InterruptLevelN : public EnumeratedFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _baseTrapType;
|
||||||
|
static FaultStat _count;
|
||||||
|
TrapType baseTrapType() {return _baseTrapType;}
|
||||||
|
public:
|
||||||
|
InterruptLevelN(uint32_t n) : EnumeratedFault(n) {;}
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
FaultPriority priority() {return 32 - _n;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class SpillNNormal : public EnumeratedFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _baseTrapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
TrapType baseTrapType() {return _baseTrapType;}
|
||||||
|
public:
|
||||||
|
SpillNNormal(uint32_t n) : EnumeratedFault(n) {;}
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class SpillNOther : public EnumeratedFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _baseTrapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
TrapType baseTrapType() {return _baseTrapType;}
|
||||||
|
public:
|
||||||
|
SpillNOther(uint32_t n) : EnumeratedFault(n) {;}
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class FillNNormal : public EnumeratedFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _baseTrapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
TrapType baseTrapType() {return _baseTrapType;}
|
||||||
|
public:
|
||||||
|
FillNNormal(uint32_t n) : EnumeratedFault(n) {;}
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class FillNOther : public EnumeratedFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _baseTrapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
TrapType baseTrapType() {return _baseTrapType;}
|
||||||
|
public:
|
||||||
|
FillNOther(uint32_t n) : EnumeratedFault(n) {;}
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
class TrapInstruction : public EnumeratedFault
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
static FaultName _name;
|
||||||
|
static TrapType _baseTrapType;
|
||||||
|
static FaultPriority _priority;
|
||||||
|
static FaultStat _count;
|
||||||
|
TrapType baseTrapType() {return _baseTrapType;}
|
||||||
|
public:
|
||||||
|
TrapInstruction(uint32_t n) : EnumeratedFault(n) {;}
|
||||||
|
FaultName name() {return _name;}
|
||||||
|
FaultPriority priority() {return _priority;}
|
||||||
|
FaultStat & countStat() {return _count;}
|
||||||
|
};
|
||||||
|
|
||||||
|
} // SparcISA namespace
|
||||||
|
|
||||||
|
#endif // __FAULTS_HH__
|
|
@ -4,28 +4,59 @@
|
||||||
//
|
//
|
||||||
|
|
||||||
output header {{
|
output header {{
|
||||||
|
|
||||||
|
struct condCodes
|
||||||
|
{
|
||||||
|
uint8_t c:1;
|
||||||
|
uint8_t v:1;
|
||||||
|
uint8_t z:1;
|
||||||
|
uint8_t n:1;
|
||||||
|
}
|
||||||
|
|
||||||
|
enum condTest
|
||||||
|
{
|
||||||
|
Always=0x8,
|
||||||
|
Never=0x0,
|
||||||
|
NotEqual=0x9,
|
||||||
|
Equal=0x1,
|
||||||
|
Greater=0xA,
|
||||||
|
LessOrEqual=0x2,
|
||||||
|
GreaterOrEqual=0xB,
|
||||||
|
Less=0x3,
|
||||||
|
GreaterUnsigned=0xC,
|
||||||
|
LessOrEqualUnsigned=0x4,
|
||||||
|
CarryClear=0xD,
|
||||||
|
CarrySet=0x5,
|
||||||
|
Positive=0xE,
|
||||||
|
Negative=0x6,
|
||||||
|
OverflowClear=0xF,
|
||||||
|
OverflowSet=0x7
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Base class for all SPARC static instructions.
|
* Base class for all SPARC static instructions.
|
||||||
*/
|
*/
|
||||||
class SparcStaticInst : public StaticInst<SPARCISA>
|
class SparcStaticInst : public StaticInst
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
// Constructor.
|
// Constructor.
|
||||||
SparcStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
|
SparcStaticInst(const char *mnem,
|
||||||
: StaticInst<SPARCISA>(mnem, _machInst, __opClass)
|
MachInst _machInst, OpClass __opClass)
|
||||||
|
: StaticInst(mnem, _machInst, __opClass)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
std::string generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const;
|
||||||
};
|
};
|
||||||
|
|
||||||
bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition);
|
bool passesCondition(condCodes codes, condTest condition);
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output decoder {{
|
output decoder {{
|
||||||
|
|
||||||
std::string SparcStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
std::string SparcStaticInst::generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const
|
||||||
{
|
{
|
||||||
std::stringstream ss;
|
std::stringstream ss;
|
||||||
|
|
||||||
|
@ -56,26 +87,42 @@ output decoder {{
|
||||||
return ss.str();
|
return ss.str();
|
||||||
}
|
}
|
||||||
|
|
||||||
bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition)
|
bool passesCondition(condCodes codes, condTest condition)
|
||||||
{
|
{
|
||||||
switch(condition)
|
switch(condition)
|
||||||
{
|
{
|
||||||
case 0b1000: return true;
|
case Always:
|
||||||
case 0b0000: return false;
|
return true;
|
||||||
case 0b1001: return !codes.z;
|
case Never:
|
||||||
case 0b0001: return codes.z;
|
return false;
|
||||||
case 0b1010: return !(codes.z | (codes.n ^ codes.v));
|
case NotEqual:
|
||||||
case 0b0010: return codes.z | (codes.n ^ codes.v);
|
return !codes.z;
|
||||||
case 0b1011: return !(codes.n ^ codes.v);
|
case Equal:
|
||||||
case 0b0011: return (codes.n ^ codes.v);
|
return codes.z;
|
||||||
case 0b1100: return !(codes.c | codes.z);
|
case Greater:
|
||||||
case 0b0100: return (codes.c | codes.z);
|
return !(codes.z | (codes.n ^ codes.v));
|
||||||
case 0b1101: return !codes.c;
|
case LessOrEqual:
|
||||||
case 0b0101: return codes.c;
|
return codes.z | (codes.n ^ codes.v);
|
||||||
case 0b1110: return !codes.n;
|
case GreaterOrEqual:
|
||||||
case 0b0110: return codes.n;
|
return !(codes.n ^ codes.v);
|
||||||
case 0b1111: return !codes.v;
|
case Less:
|
||||||
case 0b0111: return codes.v;
|
return (codes.n ^ codes.v);
|
||||||
|
case GreaterUnsigned:
|
||||||
|
return !(codes.c | codes.z);
|
||||||
|
case LessOrEqualUnsigned:
|
||||||
|
return (codes.c | codes.z);
|
||||||
|
case CarryClear:
|
||||||
|
return !codes.c;
|
||||||
|
case CarrySet:
|
||||||
|
return codes.c;
|
||||||
|
case Positive:
|
||||||
|
return !codes.n;
|
||||||
|
case Negative:
|
||||||
|
return codes.n;
|
||||||
|
case OverflowClear:
|
||||||
|
return !codes.v;
|
||||||
|
case OverflowSet:
|
||||||
|
return codes.v;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
|
@ -3,15 +3,16 @@
|
||||||
// The actual decoder specification
|
// The actual decoder specification
|
||||||
//
|
//
|
||||||
|
|
||||||
decode OP default Trap::unknown({{illegal_instruction}}) {
|
decode OP default Trap::unknown({{IllegalInstruction}}) {
|
||||||
|
|
||||||
0x0: decode OP2 {
|
0x0: decode OP2 {
|
||||||
0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP
|
0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP
|
||||||
0x1: Branch::bpcc({{
|
0x1: Branch::bpcc({{
|
||||||
switch((CC12 << 1) | CC02)
|
switch((CC12 << 1) | CC02)
|
||||||
{
|
{
|
||||||
case 1: case 3:
|
case 1:
|
||||||
throw illegal_instruction;
|
case 3:
|
||||||
|
fault = new IllegalInstruction;
|
||||||
case 0:
|
case 0:
|
||||||
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
|
if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
|
||||||
;//branchHere
|
;//branchHere
|
||||||
|
@ -29,29 +30,37 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
0x3: Branch::bpr({{
|
0x3: Branch::bpr({{
|
||||||
switch(RCOND)
|
switch(RCOND)
|
||||||
{
|
{
|
||||||
case 0: case 4:
|
case 0:
|
||||||
throw illegal_instruction;
|
case 4:
|
||||||
|
fault = new IllegalInstruction;
|
||||||
case 1:
|
case 1:
|
||||||
if(Rs1 == 0) ;//branchHere
|
if(Rs1 == 0)
|
||||||
|
;//branchHere
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
if(Rs1 <= 0) ;//branchHere
|
if(Rs1 <= 0)
|
||||||
|
;//branchHere
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
if(Rs1 < 0) ;//branchHere
|
if(Rs1 < 0)
|
||||||
|
;//branchHere
|
||||||
break;
|
break;
|
||||||
case 5:
|
case 5:
|
||||||
if(Rs1 != 0) ;//branchHere
|
if(Rs1 != 0)
|
||||||
|
;//branchHere
|
||||||
break;
|
break;
|
||||||
case 6:
|
case 6:
|
||||||
if(Rs1 > 0) ;//branchHere
|
if(Rs1 > 0)
|
||||||
|
;//branchHere
|
||||||
break;
|
break;
|
||||||
case 7:
|
case 7:
|
||||||
if(Rs1 >= 0) ;//branchHere
|
if(Rs1 >= 0)
|
||||||
|
;//branchHere
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}}); //BPr
|
}}); //BPr
|
||||||
0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); //SETHI (or NOP if rd == 0 and imm == 0)
|
//SETHI (or NOP if rd == 0 and imm == 0)
|
||||||
|
0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
|
||||||
0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
|
0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
|
||||||
0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc
|
0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc
|
||||||
}
|
}
|
||||||
|
@ -62,88 +71,100 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
0x2: decode OP3 {
|
0x2: decode OP3 {
|
||||||
format IntegerOp {
|
format IntegerOp {
|
||||||
0x00: add({{
|
0x00: add({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
Rd = Rs1.sdw + val2;
|
Rd = Rs1.sdw + val2;
|
||||||
}});//ADD
|
}});//ADD
|
||||||
0x01: and({{
|
0x01: and({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
Rd = Rs1.udw & val2;
|
Rd = Rs1.udw & val2;
|
||||||
}});//AND
|
}});//AND
|
||||||
0x02: or({{
|
0x02: or({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
Rd = Rs1.udw | val2;
|
Rd = Rs1.udw | val2;
|
||||||
}});//OR
|
}});//OR
|
||||||
0x03: xor({{
|
0x03: xor({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
Rd = Rs1.udw ^ val2;
|
Rd = Rs1.udw ^ val2;
|
||||||
}});//XOR
|
}});//XOR
|
||||||
0x04: sub({{
|
0x04: sub({{
|
||||||
INT64 val2 = ~((UINT64)(I ? SIMM13.sdw : Rs2.udw))+1;
|
int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
|
||||||
Rd = Rs1.sdw + val2;
|
Rd = Rs1.sdw + val2;
|
||||||
}});//SUB
|
}});//SUB
|
||||||
0x05: andn({{
|
0x05: andn({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
Rd = Rs1.udw & ~val2;
|
Rd = Rs1.udw & ~val2;
|
||||||
}});//ANDN
|
}});//ANDN
|
||||||
0x06: orn({{
|
0x06: orn({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
Rd = Rs1.udw | ~val2;
|
Rd = Rs1.udw | ~val2;
|
||||||
}});//ORN
|
}});//ORN
|
||||||
0x07: xnor({{
|
0x07: xnor({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
Rd = ~(Rs1.udw ^ val2);
|
Rd = ~(Rs1.udw ^ val2);
|
||||||
}});//XNOR
|
}});//XNOR
|
||||||
0x08: addc({{
|
0x08: addc({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
||||||
Rd = Rs1.sdw + val2 + carryin;
|
Rd = Rs1.sdw + val2 + carryin;
|
||||||
}});//ADDC
|
}});//ADDC
|
||||||
0x09: mulx({{
|
0x09: mulx({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = Rs1 * val2;
|
Rd = Rs1 * val2;
|
||||||
}});//MULX
|
}});//MULX
|
||||||
0x0A: umul({{
|
0x0A: umul({{
|
||||||
UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
|
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
|
||||||
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
|
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
|
||||||
}});//UMUL
|
}});//UMUL
|
||||||
0x0B: smul({{
|
0x0B: smul({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
|
rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
|
||||||
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
|
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
|
||||||
}});//SMUL
|
}});//SMUL
|
||||||
0x0C: subc({{
|
0x0C: subc({{
|
||||||
INT64 val2 = ~((INT64)(I ? SIMM13.sdw : Rs2.sdw))+1;
|
int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
|
||||||
INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
||||||
Rd.sdw = Rs1.sdw + val2 + carryin;
|
Rd.sdw = Rs1.sdw + val2 + carryin;
|
||||||
}});//SUBC
|
}});//SUBC
|
||||||
0x0D: udivx({{
|
0x0D: udivx({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
if(val2 == 0) throw division_by_zero;
|
if(val2 == 0) throw division_by_zero;
|
||||||
Rd.udw = Rs1.udw / val2;
|
Rd.udw = Rs1.udw / val2;
|
||||||
}});//UDIVX
|
}});//UDIVX
|
||||||
0x0E: udiv({{
|
0x0E: udiv({{
|
||||||
UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
|
uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
|
||||||
if(val2 == 0) throw division_by_zero;
|
if(val2 == 0)
|
||||||
resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
|
fault = new DivisionByZero;
|
||||||
INT32 overflow = (resTemp<63:32> != 0);
|
resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32)
|
||||||
if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
|
| Rs1.udw<31:0>) / val2;
|
||||||
else rd.udw = resTemp;
|
int32_t overflow = (resTemp<63:32> != 0);
|
||||||
|
if(overflow)
|
||||||
|
rd.udw = resTemp = 0xFFFFFFFF;
|
||||||
|
else
|
||||||
|
rd.udw = resTemp;
|
||||||
}}); //UDIV
|
}}); //UDIV
|
||||||
0x0F: sdiv({{
|
0x0F: sdiv({{
|
||||||
INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
|
int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
|
||||||
if(val2 == 0) throw division_by_zero;
|
if(val2 == 0)
|
||||||
Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
|
fault = new DivisionByZero;
|
||||||
INT32 overflow = (resTemp<63:31> != 0);
|
|
||||||
INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
|
Rd.sdw = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) |
|
||||||
if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
|
Rs1.sdw<31:0>) / val2;
|
||||||
else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
|
resTemp = Rd.sdw;
|
||||||
else rd.udw = resTemp;
|
int32_t overflow = (resTemp<63:31> != 0);
|
||||||
|
int32_t underflow =
|
||||||
|
(resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
|
||||||
|
if(overflow)
|
||||||
|
rd.udw = resTemp = 0x7FFFFFFF;
|
||||||
|
else if(underflow)
|
||||||
|
rd.udw = resTemp = 0xFFFFFFFF80000000;
|
||||||
|
else
|
||||||
|
rd.udw = resTemp;
|
||||||
}});//SDIV
|
}});//SDIV
|
||||||
}
|
}
|
||||||
format IntegerOpCc {
|
format IntegerOpCc {
|
||||||
0x10: addcc({{
|
0x10: addcc({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1 + val2;}},
|
Rd = resTemp = Rs1 + val2;}},
|
||||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||||
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
|
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
|
||||||
|
@ -151,59 +172,62 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||||
);//ADDcc
|
);//ADDcc
|
||||||
0x11: andcc({{
|
0x11: andcc({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = Rs1 & val2;}}
|
Rd = Rs1 & val2;}},
|
||||||
,{{0}},{{0}},{{0}},{{0}});//ANDcc
|
{{0}},{{0}},{{0}},{{0}});//ANDcc
|
||||||
0x12: orcc({{
|
0x12: orcc({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = Rs1 | val2;}}
|
Rd = Rs1 | val2;}},
|
||||||
,{{0}},{{0}},{{0}},{{0}});//ORcc
|
{{0}},{{0}},{{0}},{{0}});//ORcc
|
||||||
0x13: xorcc({{
|
0x13: xorcc({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = Rs1 ^ val2;}}
|
Rd = Rs1 ^ val2;}},
|
||||||
,{{0}},{{0}},{{0}},{{0}});//XORcc
|
{{0}},{{0}},{{0}},{{0}});//XORcc
|
||||||
0x14: subcc({{
|
0x14: subcc({{
|
||||||
INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1 - val2;}},
|
Rd = resTemp = Rs1 - val2;}},
|
||||||
{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
|
{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
|
||||||
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
|
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
|
||||||
{{((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}},
|
{{((Rs1 >> 1) + (~val2) >> 1) +
|
||||||
|
((Rs1 | ~val2) & 0x1))<63:>}},
|
||||||
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
|
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
|
||||||
);//SUBcc
|
);//SUBcc
|
||||||
0x15: andncc({{
|
0x15: andncc({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = Rs1 & ~val2;}}
|
Rd = Rs1 & ~val2;}},
|
||||||
,{{0}},{{0}},{{0}},{{0}});//ANDNcc
|
{{0}},{{0}},{{0}},{{0}});//ANDNcc
|
||||||
0x16: orncc({{
|
0x16: orncc({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = Rs1 | ~val2;}}
|
Rd = Rs1 | ~val2;}},
|
||||||
,{{0}},{{0}},{{0}},{{0}});//ORNcc
|
{{0}},{{0}},{{0}},{{0}});//ORNcc
|
||||||
0x17: xnorcc({{
|
0x17: xnorcc({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = ~(Rs1 ^ val2);}}
|
Rd = ~(Rs1 ^ val2);}},
|
||||||
,{{0}},{{0}},{{0}},{{0}});//XNORcc
|
{{0}},{{0}},{{0}},{{0}});//XNORcc
|
||||||
0x18: addccc({{
|
0x18: addccc({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
||||||
Rd = resTemp = Rs1 + val2 + carryin;}},
|
Rd = resTemp = Rs1 + val2 + carryin;}},
|
||||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 + carryin)}},
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
|
||||||
|
+ carryin)}},
|
||||||
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
|
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
|
||||||
{{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
|
{{((Rs1 >> 1) + (val2 >> 1) +
|
||||||
|
((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
|
||||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||||
);//ADDCcc
|
);//ADDCcc
|
||||||
0x1A: umulcc({{
|
0x1A: umulcc({{
|
||||||
UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
|
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
|
||||||
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
|
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}},
|
||||||
,{{0}},{{0}},{{0}},{{0}});//UMULcc
|
{{0}},{{0}},{{0}},{{0}});//UMULcc
|
||||||
0x1B: smulcc({{
|
0x1B: smulcc({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
|
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
|
||||||
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
|
xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
|
||||||
,{{0}},{{0}},{{0}},{{0}});//SMULcc
|
,{{0}},{{0}},{{0}},{{0}});//SMULcc
|
||||||
0x1C: subccc({{
|
0x1C: subccc({{
|
||||||
INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
|
||||||
INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
|
||||||
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
|
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
|
||||||
{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
|
{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
|
||||||
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
|
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
|
||||||
|
@ -211,15 +235,15 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
|
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
|
||||||
);//SUBCcc
|
);//SUBCcc
|
||||||
0x1D: udivxcc({{
|
0x1D: udivxcc({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
|
||||||
if(val2 == 0) throw division_by_zero;
|
if(val2 == 0) throw division_by_zero;
|
||||||
Rd.udw = Rs1.udw / val2;}}
|
Rd.udw = Rs1.udw / val2;}}
|
||||||
,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
|
,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
|
||||||
0x1E: udivcc({{
|
0x1E: udivcc({{
|
||||||
UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
|
uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
|
||||||
if(val2 == 0) throw division_by_zero;
|
if(val2 == 0) throw division_by_zero;
|
||||||
resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
|
resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
|
||||||
INT32 overflow = (resTemp<63:32> != 0);
|
int32_t overflow = (resTemp<63:32> != 0);
|
||||||
if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
|
if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
|
||||||
else rd.udw = resTemp;}},
|
else rd.udw = resTemp;}},
|
||||||
{{0}},
|
{{0}},
|
||||||
|
@ -228,11 +252,11 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
{{0}}
|
{{0}}
|
||||||
);//UDIVcc
|
);//UDIVcc
|
||||||
0x1F: sdivcc({{
|
0x1F: sdivcc({{
|
||||||
INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
|
int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
|
||||||
if(val2 == 0) throw division_by_zero;
|
if(val2 == 0) throw division_by_zero;
|
||||||
Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
|
Rd.sdw = resTemp = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
|
||||||
INT32 overflow = (resTemp<63:31> != 0);
|
int32_t overflow = (resTemp<63:31> != 0);
|
||||||
INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
|
int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
|
||||||
if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
|
if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
|
||||||
else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
|
else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
|
||||||
else rd.udw = resTemp;}},
|
else rd.udw = resTemp;}},
|
||||||
|
@ -242,27 +266,27 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
{{0}}
|
{{0}}
|
||||||
);//SDIVcc
|
);//SDIVcc
|
||||||
0x20: taddcc({{
|
0x20: taddcc({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1 + val2;
|
Rd = resTemp = Rs1 + val2;
|
||||||
INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
||||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||||
{{overflow}},
|
{{overflow}},
|
||||||
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
||||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||||
);//TADDcc
|
);//TADDcc
|
||||||
0x21: tsubcc({{
|
0x21: tsubcc({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1 + val2;
|
Rd = resTemp = Rs1 + val2;
|
||||||
INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
|
||||||
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||||
{{overflow}},
|
{{overflow}},
|
||||||
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
|
||||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||||
);//TSUBcc
|
);//TSUBcc
|
||||||
0x22: taddcctv({{
|
0x22: taddcctv({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1 + val2;
|
Rd = resTemp = Rs1 + val2;
|
||||||
INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
||||||
if(overflow) throw tag_overflow;}},
|
if(overflow) throw tag_overflow;}},
|
||||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||||
{{overflow}},
|
{{overflow}},
|
||||||
|
@ -270,9 +294,9 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||||
);//TADDccTV
|
);//TADDccTV
|
||||||
0x23: tsubcctv({{
|
0x23: tsubcctv({{
|
||||||
INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
|
||||||
Rd = resTemp = Rs1 + val2;
|
Rd = resTemp = Rs1 + val2;
|
||||||
INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
|
||||||
if(overflow) throw tag_overflow;}},
|
if(overflow) throw tag_overflow;}},
|
||||||
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
|
||||||
{{overflow}},
|
{{overflow}},
|
||||||
|
@ -280,9 +304,9 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
|
||||||
);//TSUBccTV
|
);//TSUBccTV
|
||||||
0x24: mulscc({{
|
0x24: mulscc({{
|
||||||
INT64 resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
|
int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
|
||||||
INT32 multiplier = Rs1<31:0>;
|
int32_t multiplier = Rs1<31:0>;
|
||||||
INT32 savedLSB = Rs1<0:>;
|
int32_t savedLSB = Rs1<0:>;
|
||||||
multiplier = multipler<31:1> |
|
multiplier = multipler<31:1> |
|
||||||
((xc->regs.MiscRegs.ccrFields.iccFields.n
|
((xc->regs.MiscRegs.ccrFields.iccFields.n
|
||||||
^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
|
^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
|
||||||
|
@ -368,14 +392,14 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
}
|
}
|
||||||
}});//MOVcc
|
}});//MOVcc
|
||||||
0x2D: sdivx({{
|
0x2D: sdivx({{
|
||||||
INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
if(val2 == 0) throw division_by_zero;
|
if(val2 == 0) throw division_by_zero;
|
||||||
Rd.sdw = Rs1.sdw / val2;
|
Rd.sdw = Rs1.sdw / val2;
|
||||||
}});//SDIVX
|
}});//SDIVX
|
||||||
0x2E: decode RS1 {
|
0x2E: decode RS1 {
|
||||||
0x0: IntegerOp::popc({{
|
0x0: IntegerOp::popc({{
|
||||||
INT64 count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
UINT8 oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
|
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
|
||||||
for(unsigned int x = 0; x < 16; x++)
|
for(unsigned int x = 0; x < 16; x++)
|
||||||
{
|
{
|
||||||
count += oneBits[val2 & 0xF];
|
count += oneBits[val2 & 0xF];
|
||||||
|
@ -384,7 +408,7 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
}});//POPC
|
}});//POPC
|
||||||
}
|
}
|
||||||
0x2F: movr({{
|
0x2F: movr({{
|
||||||
UINT64 val2 = (I ? SIMM10.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
|
||||||
switch(RCOND)
|
switch(RCOND)
|
||||||
{
|
{
|
||||||
case 0: case 4:
|
case 0: case 4:
|
||||||
|
@ -412,19 +436,19 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
}});//MOVR
|
}});//MOVR
|
||||||
0x30: decode RD {
|
0x30: decode RD {
|
||||||
0x0: wry({{
|
0x0: wry({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.y = Rs1 ^ val2;
|
xc->regs.MiscRegs.y = Rs1 ^ val2;
|
||||||
}});//WRY
|
}});//WRY
|
||||||
0x2: wrccr({{
|
0x2: wrccr({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.ccr = Rs1 ^ val2;
|
xc->regs.MiscRegs.ccr = Rs1 ^ val2;
|
||||||
}});//WRCCR
|
}});//WRCCR
|
||||||
0x3: wrasi({{
|
0x3: wrasi({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
||||||
}});//WRASI
|
}});//WRASI
|
||||||
0x6: wrfprs({{
|
0x6: wrfprs({{
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
xc->regs.MiscRegs.asi = Rs1 ^ val2;
|
||||||
}});//WRFPRS
|
}});//WRFPRS
|
||||||
0xF: Trap::sir({{software_initiated_reset}}); //SIR
|
0xF: Trap::sir({{software_initiated_reset}}); //SIR
|
||||||
|
@ -435,63 +459,63 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
}
|
}
|
||||||
0x32: decode RD {
|
0x32: decode RD {
|
||||||
0x0: wrprtpc({{checkPriv
|
0x0: wrprtpc({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x1: wrprtnpc({{checkPriv
|
0x1: wrprtnpc({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x2: wrprtstate({{checkPriv
|
0x2: wrprtstate({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x3: wrprtt({{checkPriv
|
0x3: wrprtt({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x4: wrprtick({{checkPriv
|
0x4: wrprtick({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.tick = Rs1 ^ val2;
|
xc->regs.MiscRegs.tick = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x5: wrprtba({{checkPriv
|
0x5: wrprtba({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.tba = Rs1 ^ val2;
|
xc->regs.MiscRegs.tba = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x6: wrprpstate({{checkPriv
|
0x6: wrprpstate({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.pstate = Rs1 ^ val2;
|
xc->regs.MiscRegs.pstate = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x7: wrprtl({{checkPriv
|
0x7: wrprtl({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.tl = Rs1 ^ val2;
|
xc->regs.MiscRegs.tl = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x8: wrprpil({{checkPriv
|
0x8: wrprpil({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.pil = Rs1 ^ val2;
|
xc->regs.MiscRegs.pil = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0x9: wrprcwp({{checkPriv
|
0x9: wrprcwp({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.cwp = Rs1 ^ val2;
|
xc->regs.MiscRegs.cwp = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0xA: wrprcansave({{checkPriv
|
0xA: wrprcansave({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.cansave = Rs1 ^ val2;
|
xc->regs.MiscRegs.cansave = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0xB: wrprcanrestore({{checkPriv
|
0xB: wrprcanrestore({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
|
xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0xC: wrprcleanwin({{checkPriv
|
0xC: wrprcleanwin({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
|
xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0xD: wrprotherwin({{checkPriv
|
0xD: wrprotherwin({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
|
xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
0xE: wrprwstate({{checkPriv
|
0xE: wrprwstate({{checkPriv
|
||||||
UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
|
||||||
xc->regs.MiscRegs.wstate = Rs1 ^ val2;
|
xc->regs.MiscRegs.wstate = Rs1 ^ val2;
|
||||||
}});
|
}});
|
||||||
}
|
}
|
||||||
|
@ -532,7 +556,7 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
|
0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
|
||||||
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
|
0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
|
||||||
0x03: ldd({{
|
0x03: ldd({{
|
||||||
UINT64 val = Mem.udw;
|
uint64_t val = Mem.udw;
|
||||||
setIntReg(RD & (~1), val<31:0>);
|
setIntReg(RD & (~1), val<31:0>);
|
||||||
setIntReg(RD | 1, val<63:32>);
|
setIntReg(RD | 1, val<63:32>);
|
||||||
}});//LDD
|
}});//LDD
|
||||||
|
@ -553,7 +577,7 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
}}); //LDSTUB
|
}}); //LDSTUB
|
||||||
0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
|
0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
|
||||||
0x0F: swap({{
|
0x0F: swap({{
|
||||||
UINT32 temp = Rd.uw;
|
uint32_t temp = Rd.uw;
|
||||||
Rd.uw = Mem.uw;
|
Rd.uw = Mem.uw;
|
||||||
Mem.uw = temp;
|
Mem.uw = temp;
|
||||||
}}); //SWAP
|
}}); //SWAP
|
||||||
|
@ -561,7 +585,7 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
|
0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
|
||||||
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
|
0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
|
||||||
0x13: ldda({{
|
0x13: ldda({{
|
||||||
UINT64 val = Mem.udw;
|
uint64_t val = Mem.udw;
|
||||||
setIntReg(RD & (~1), val<31:0>);
|
setIntReg(RD & (~1), val<31:0>);
|
||||||
setIntReg(RD | 1, val<63:32>);
|
setIntReg(RD | 1, val<63:32>);
|
||||||
}}); //LDDA
|
}}); //LDDA
|
||||||
|
@ -582,7 +606,7 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
}}); //LDSTUBA
|
}}); //LDSTUBA
|
||||||
0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
|
0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
|
||||||
0x1F: swapa({{
|
0x1F: swapa({{
|
||||||
UINT32 temp = Rd.uw;
|
uint32_t temp = Rd.uw;
|
||||||
Rd.uw = Mem.uw;
|
Rd.uw = Mem.uw;
|
||||||
Mem.uw = temp;
|
Mem.uw = temp;
|
||||||
}}); //SWAPA
|
}}); //SWAPA
|
||||||
|
@ -621,14 +645,14 @@ decode OP default Trap::unknown({{illegal_instruction}}) {
|
||||||
|
|
||||||
|
|
||||||
0x3C: Cas::casa(
|
0x3C: Cas::casa(
|
||||||
{{UINT64 val = Mem.uw;
|
{{uint64_t val = Mem.uw;
|
||||||
if(Rs2.uw == val)
|
if(Rs2.uw == val)
|
||||||
Mem.uw = Rd.uw;
|
Mem.uw = Rd.uw;
|
||||||
Rd.uw = val;
|
Rd.uw = val;
|
||||||
}}); //CASA
|
}}); //CASA
|
||||||
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
|
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
|
||||||
0x3E: Cas::casxa(
|
0x3E: Cas::casxa(
|
||||||
{{UINT64 val = Mem.udw;
|
{{uint64_t val = Mem.udw;
|
||||||
if(Rs2 == val)
|
if(Rs2 == val)
|
||||||
Mem.udw = Rd;
|
Mem.udw = Rd;
|
||||||
Rd = val;
|
Rd = val;
|
||||||
|
|
|
@ -12,7 +12,7 @@ def template BasicDeclare {{
|
||||||
class %(class_name)s : public %(base_class)s
|
class %(class_name)s : public %(base_class)s
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
/// Constructor.
|
// Constructor.
|
||||||
%(class_name)s(MachInst machInst);
|
%(class_name)s(MachInst machInst);
|
||||||
%(BasicExecDeclare)s
|
%(BasicExecDeclare)s
|
||||||
};
|
};
|
||||||
|
@ -20,7 +20,8 @@ def template BasicDeclare {{
|
||||||
|
|
||||||
// Basic instruction class constructor template.
|
// Basic instruction class constructor template.
|
||||||
def template BasicConstructor {{
|
def template BasicConstructor {{
|
||||||
inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
|
inline %(class_name)s::%(class_name)s(MachInst machInst)
|
||||||
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
|
||||||
{
|
{
|
||||||
%(constructor)s;
|
%(constructor)s;
|
||||||
}
|
}
|
||||||
|
@ -28,16 +29,17 @@ def template BasicConstructor {{
|
||||||
|
|
||||||
// Basic instruction class execute method template.
|
// Basic instruction class execute method template.
|
||||||
def template BasicExecute {{
|
def template BasicExecute {{
|
||||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
{
|
{
|
||||||
Fault fault = No_Fault;
|
Fault fault = NoFault;
|
||||||
|
|
||||||
%(fp_enable_check)s;
|
%(fp_enable_check)s;
|
||||||
%(op_decl)s;
|
%(op_decl)s;
|
||||||
%(op_rd)s;
|
%(op_rd)s;
|
||||||
%(code)s;
|
%(code)s;
|
||||||
|
|
||||||
if(fault == No_Fault)
|
if(fault == NoFault)
|
||||||
{
|
{
|
||||||
%(op_wb)s;
|
%(op_wb)s;
|
||||||
}
|
}
|
||||||
|
@ -57,7 +59,8 @@ def template BasicDecodeWithMnemonic {{
|
||||||
|
|
||||||
// The most basic instruction format... used only for a few misc. insts
|
// The most basic instruction format... used only for a few misc. insts
|
||||||
def format BasicOperate(code, *flags) {{
|
def format BasicOperate(code, *flags) {{
|
||||||
iop = InstObjParams(name, Name, 'SparcStaticInst', CodeBlock(code), flags)
|
iop = InstObjParams(name, Name, 'SparcStaticInst',
|
||||||
|
CodeBlock(code), flags)
|
||||||
header_output = BasicDeclare.subst(iop)
|
header_output = BasicDeclare.subst(iop)
|
||||||
decoder_output = BasicConstructor.subst(iop)
|
decoder_output = BasicConstructor.subst(iop)
|
||||||
decode_block = BasicDecode.subst(iop)
|
decode_block = BasicDecode.subst(iop)
|
||||||
|
|
|
@ -10,47 +10,43 @@ output header {{
|
||||||
class Branch : public SparcStaticInst
|
class Branch : public SparcStaticInst
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
|
// Constructor
|
||||||
/// Constructor
|
Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||||
Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
SparcStaticInst(mnem, _machInst, __opClass)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
std::string generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const;
|
||||||
};
|
};
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output decoder {{
|
output decoder {{
|
||||||
std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||||
{
|
{
|
||||||
return "Disassembly of integer instruction\n";
|
return "Branch instruction\n";
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
def template BranchExecute {{
|
def template BranchExecute {{
|
||||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
{
|
{
|
||||||
//Attempt to execute the instruction
|
//Attempt to execute the instruction
|
||||||
try
|
Fault fault = NoFault;
|
||||||
{
|
|
||||||
checkPriv;
|
checkPriv;
|
||||||
|
|
||||||
%(op_decl)s;
|
%(op_decl)s;
|
||||||
%(op_rd)s;
|
%(op_rd)s;
|
||||||
%(code)s;
|
%(code)s;
|
||||||
}
|
|
||||||
//If we have an exception for some reason,
|
|
||||||
//deal with it
|
|
||||||
catch(SparcException except)
|
|
||||||
{
|
|
||||||
//Deal with exception
|
|
||||||
return No_Fault;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
if(fault == NoFault)
|
||||||
|
{
|
||||||
//Write the resulting state to the execution context
|
//Write the resulting state to the execution context
|
||||||
%(op_wb)s;
|
%(op_wb)s;
|
||||||
|
}
|
||||||
|
|
||||||
return No_Fault;
|
return fault;
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
|
@ -10,20 +10,22 @@ output header {{
|
||||||
class IntegerOp : public SparcStaticInst
|
class IntegerOp : public SparcStaticInst
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
|
// Constructor
|
||||||
/// Constructor
|
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||||
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
SparcStaticInst(mnem, _machInst, __opClass)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
std::string generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const;
|
||||||
};
|
};
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output decoder {{
|
output decoder {{
|
||||||
std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
std::string IntegerOp::generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const
|
||||||
{
|
{
|
||||||
return "Disassembly of integer instruction\n";
|
return "Integer instruction\n";
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
|
@ -11,46 +11,41 @@ output header {{
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
/// Constructor
|
// Constructor
|
||||||
Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
Mem(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||||
|
SparcStaticInst(mnem, _machInst, __opClass)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
std::string generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const;
|
||||||
};
|
};
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output decoder {{
|
output decoder {{
|
||||||
std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||||
{
|
{
|
||||||
return "Disassembly of integer instruction\n";
|
return "Memory instruction\n";
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
def template MemExecute {{
|
def template MemExecute {{
|
||||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
{
|
{
|
||||||
//Attempt to execute the instruction
|
Fault fault = NoFault;
|
||||||
try
|
|
||||||
{
|
|
||||||
|
|
||||||
%(op_decl)s;
|
%(op_decl)s;
|
||||||
%(op_rd)s;
|
%(op_rd)s;
|
||||||
ea_code
|
ea_code
|
||||||
%(code)s;
|
%(code)s;
|
||||||
}
|
|
||||||
//If we have an exception for some reason,
|
|
||||||
//deal with it
|
|
||||||
catch(SparcException except)
|
|
||||||
{
|
|
||||||
//Deal with exception
|
|
||||||
return No_Fault;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
if(fault == NoFault)
|
||||||
|
{
|
||||||
//Write the resulting state to the execution context
|
//Write the resulting state to the execution context
|
||||||
%(op_wb)s;
|
%(op_wb)s;
|
||||||
|
}
|
||||||
|
|
||||||
return No_Fault;
|
return fault;
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
|
@ -5,33 +5,36 @@
|
||||||
|
|
||||||
output header {{
|
output header {{
|
||||||
/**
|
/**
|
||||||
* Base class for integer operations.
|
* Noop class.
|
||||||
*/
|
*/
|
||||||
class Noop : public SparcStaticInst
|
class Noop : public SparcStaticInst
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
|
// Constructor
|
||||||
/// Constructor
|
Noop(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||||
Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
SparcStaticInst(mnem, _machInst, __opClass)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
std::string generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const;
|
||||||
};
|
};
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output decoder {{
|
output decoder {{
|
||||||
std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
std::string Noop::generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const
|
||||||
{
|
{
|
||||||
return "Disassembly of integer instruction\n";
|
return "Noop\n";
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
def template NoopExecute {{
|
def template NoopExecute {{
|
||||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
{
|
{
|
||||||
//Nothing to see here, move along
|
//Nothing to see here, move along
|
||||||
return No_Fault;
|
return NoFault;
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
|
@ -11,33 +11,31 @@ output header {{
|
||||||
{
|
{
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
/// Constructor
|
// Constructor
|
||||||
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
|
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||||
|
SparcStaticInst(mnem, _machInst, __opClass)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
std::string generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const;
|
||||||
};
|
};
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output decoder {{
|
output decoder {{
|
||||||
std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
std::string Trap::generateDisassembly(Addr pc,
|
||||||
|
const SymbolTable *symtab) const
|
||||||
{
|
{
|
||||||
return "Disassembly of integer instruction\n";
|
return "Trap instruction\n";
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
def template TrapExecute {{
|
def template TrapExecute {{
|
||||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||||
|
Trace::InstRecord *traceData) const
|
||||||
{
|
{
|
||||||
//Call into the trap handler with the appropriate fault
|
//TODO: set up a software fault and return it.
|
||||||
return No_Fault;
|
return NoFault;
|
||||||
}
|
|
||||||
|
|
||||||
//Write the resulting state to the execution context
|
|
||||||
%(op_wb)s;
|
|
||||||
|
|
||||||
return No_Fault;
|
|
||||||
}
|
}
|
||||||
}};
|
}};
|
||||||
|
|
||||||
|
|
|
@ -9,8 +9,9 @@ output header {{
|
||||||
#include <iomanip>
|
#include <iomanip>
|
||||||
|
|
||||||
#include "cpu/static_inst.hh"
|
#include "cpu/static_inst.hh"
|
||||||
#include "traps.hh"
|
#include "arch/sparc/faults.hh"
|
||||||
#include "mem/mem_req.hh" // some constructors use MemReq flags
|
#include "mem/mem_req.hh" // some constructors use MemReq flags
|
||||||
|
#include "arch/sparc/isa_traits.hh"
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output decoder {{
|
output decoder {{
|
||||||
|
@ -22,6 +23,8 @@ output decoder {{
|
||||||
#if defined(linux)
|
#if defined(linux)
|
||||||
#include <fenv.h>
|
#include <fenv.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
using namespace SparcISA;
|
||||||
}};
|
}};
|
||||||
|
|
||||||
output exec {{
|
output exec {{
|
||||||
|
|
|
@ -22,11 +22,10 @@ def operands {{
|
||||||
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
|
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
|
||||||
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
|
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
|
||||||
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
|
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
|
||||||
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
|
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
||||||
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
|
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
|
||||||
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
|
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
|
||||||
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
|
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
|
||||||
# The next two are hacks for non-full-system call-pal emulation
|
'R0': ('IntReg', 'udw', '0', None, 1),
|
||||||
#'R0': ('IntReg', 'uq', '0', None, 1),
|
'R16': ('IntReg', 'udw', '16', None, 1)
|
||||||
#'R16': ('IntReg', 'uq', '16', None, 1)
|
|
||||||
}};
|
}};
|
||||||
|
|
|
@ -29,22 +29,24 @@
|
||||||
#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
|
#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
|
||||||
#define __ARCH_SPARC_ISA_TRAITS_HH__
|
#define __ARCH_SPARC_ISA_TRAITS_HH__
|
||||||
|
|
||||||
|
#include "arch/sparc/faults.hh"
|
||||||
|
#include "base/misc.hh"
|
||||||
|
#include "config/full_system.hh"
|
||||||
|
#include "sim/host.hh"
|
||||||
|
|
||||||
//This makes sure the big endian versions of certain functions are used.
|
//This makes sure the big endian versions of certain functions are used.
|
||||||
namespace BigEndianGuest {}
|
namespace BigEndianGuest {}
|
||||||
using namespace BigEndianGuest;
|
using namespace BigEndianGuest;
|
||||||
|
|
||||||
#include "arch/sparc/faults.hh"
|
class ExecContext;
|
||||||
#include "base/misc.hh"
|
|
||||||
#include "sim/host.hh"
|
|
||||||
|
|
||||||
class FastCPU;
|
class FastCPU;
|
||||||
//class FullCPU;
|
//class FullCPU;
|
||||||
//class Checkpoint;
|
class Checkpoint;
|
||||||
|
|
||||||
#define TARGET_SPARC
|
#define TARGET_SPARC
|
||||||
|
|
||||||
template <class ISA> class StaticInst;
|
class StaticInst;
|
||||||
template <class ISA> class StaticInstPtr;
|
class StaticInstPtr;
|
||||||
|
|
||||||
//namespace EV5
|
//namespace EV5
|
||||||
//{
|
//{
|
||||||
|
@ -52,10 +54,8 @@ template <class ISA> class StaticInstPtr;
|
||||||
// int ITB_ASN_ASN(uint64_t reg);
|
// int ITB_ASN_ASN(uint64_t reg);
|
||||||
//}
|
//}
|
||||||
|
|
||||||
class SPARCISA
|
namespace SparcISA
|
||||||
{
|
{
|
||||||
public:
|
|
||||||
|
|
||||||
typedef uint32_t MachInst;
|
typedef uint32_t MachInst;
|
||||||
typedef uint64_t Addr;
|
typedef uint64_t Addr;
|
||||||
typedef uint8_t RegIndex;
|
typedef uint8_t RegIndex;
|
||||||
|
@ -73,12 +73,12 @@ class SPARCISA
|
||||||
MaxInstDestRegs = 2,
|
MaxInstDestRegs = 2,
|
||||||
|
|
||||||
// Maximum trap level
|
// Maximum trap level
|
||||||
MaxTL = 4
|
MaxTL = 4,
|
||||||
|
|
||||||
// semantically meaningful register indices
|
// semantically meaningful register indices
|
||||||
ZeroReg = 0, // architecturally meaningful
|
ZeroReg = 0 // architecturally meaningful
|
||||||
// the rest of these depend on the ABI
|
// the rest of these depend on the ABI
|
||||||
}
|
};
|
||||||
typedef uint64_t IntReg;
|
typedef uint64_t IntReg;
|
||||||
|
|
||||||
class IntRegFile
|
class IntRegFile
|
||||||
|
@ -90,20 +90,14 @@ class SPARCISA
|
||||||
IntReg & operator [] (RegIndex index)
|
IntReg & operator [] (RegIndex index)
|
||||||
{
|
{
|
||||||
//Don't allow indexes outside of the 32 registers
|
//Don't allow indexes outside of the 32 registers
|
||||||
index &= 0x1F
|
index &= 0x1F;
|
||||||
return regs[index];
|
return regs[index];
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
void inline serialize(std::ostream & os)
|
void serialize(std::ostream & os);
|
||||||
{
|
|
||||||
SERIALIZE_ARRAY(regs, 32);
|
|
||||||
}
|
|
||||||
|
|
||||||
void inline unserialize(Checkpoint &*cp, const std::string §ion)
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
{
|
|
||||||
UNSERIALIZE_ARRAY(regs, 32);
|
|
||||||
}
|
|
||||||
|
|
||||||
class FloatRegFile
|
class FloatRegFile
|
||||||
{
|
{
|
||||||
|
@ -112,7 +106,7 @@ class SPARCISA
|
||||||
//is aligned correctly in memory
|
//is aligned correctly in memory
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
double double rawRegs[16];
|
long double rawRegs[16];
|
||||||
uint64_t regDump[32];
|
uint64_t regDump[32];
|
||||||
};
|
};
|
||||||
class QuadRegs
|
class QuadRegs
|
||||||
|
@ -121,7 +115,7 @@ class SPARCISA
|
||||||
FloatRegFile * parent;
|
FloatRegFile * parent;
|
||||||
public:
|
public:
|
||||||
QuadRegs(FloatRegFile * p) : parent(p) {;}
|
QuadRegs(FloatRegFile * p) : parent(p) {;}
|
||||||
double double & operator [] (RegIndex index)
|
long double & operator [] (RegIndex index)
|
||||||
{
|
{
|
||||||
//Quad floats are index by the single
|
//Quad floats are index by the single
|
||||||
//precision register the start on,
|
//precision register the start on,
|
||||||
|
@ -141,33 +135,27 @@ class SPARCISA
|
||||||
//Double floats are index by the single
|
//Double floats are index by the single
|
||||||
//precision register the start on,
|
//precision register the start on,
|
||||||
//and only 32 should be accessed
|
//and only 32 should be accessed
|
||||||
index = (index >> 1) & 0x1F
|
index = (index >> 1) & 0x1F;
|
||||||
return ((double [])parent->rawRegs)[index];
|
return ((double *)parent->rawRegs)[index];
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
};
|
||||||
class SingleRegs
|
class SingleRegs
|
||||||
{
|
{
|
||||||
private:
|
private:
|
||||||
FloatRegFile * parent;
|
FloatRegFile * parent;
|
||||||
public:
|
public:
|
||||||
SingleRegs(FloatRegFile * p) : parent(p) {;}
|
SingleRegs(FloatRegFile * p) : parent(p) {;}
|
||||||
double & operator [] (RegFile index)
|
float & operator [] (RegIndex index)
|
||||||
{
|
{
|
||||||
//Only 32 single floats should be accessed
|
//Only 32 single floats should be accessed
|
||||||
index &= 0x1F
|
index &= 0x1F;
|
||||||
return ((float [])parent->rawRegs)[index];
|
return ((float *)parent->rawRegs)[index];
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
};
|
||||||
public:
|
public:
|
||||||
void inline serialize(std::ostream & os)
|
void serialize(std::ostream & os);
|
||||||
{
|
|
||||||
SERIALIZE_ARRAY(regDump, 32);
|
|
||||||
}
|
|
||||||
|
|
||||||
void inline unserialize(Checkpoint &* cp, std::string & section)
|
void unserialize(Checkpoint * cp, std::string & section);
|
||||||
{
|
|
||||||
UNSERIALIZE_ARRAY(regDump, 32);
|
|
||||||
}
|
|
||||||
|
|
||||||
QuadRegs quadRegs;
|
QuadRegs quadRegs;
|
||||||
DoubleRegs doubleRegs;
|
DoubleRegs doubleRegs;
|
||||||
|
@ -197,7 +185,7 @@ class SPARCISA
|
||||||
uint16_t tle:1; // Trap little-endian
|
uint16_t tle:1; // Trap little-endian
|
||||||
uint16_t cle:1; // Current little-endian
|
uint16_t cle:1; // Current little-endian
|
||||||
} pstateFields;
|
} pstateFields;
|
||||||
}
|
};
|
||||||
uint64_t tba; // Trap Base Address
|
uint64_t tba; // Trap Base Address
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
|
@ -207,10 +195,11 @@ class SPARCISA
|
||||||
uint64_t value:32; // The actual value stored in y
|
uint64_t value:32; // The actual value stored in y
|
||||||
const uint64_t :32; // reserved bits
|
const uint64_t :32; // reserved bits
|
||||||
} yFields;
|
} yFields;
|
||||||
}
|
};
|
||||||
uint8_t pil; // Process Interrupt Register
|
uint8_t pil; // Process Interrupt Register
|
||||||
uint8_t cwp; // Current Window Pointer
|
uint8_t cwp; // Current Window Pointer
|
||||||
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level)
|
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
|
||||||
|
// on the previous level)
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
uint8_t ccr; // Condition Code Register
|
uint8_t ccr; // Condition Code Register
|
||||||
|
@ -239,11 +228,13 @@ class SPARCISA
|
||||||
} xccFields:4;
|
} xccFields:4;
|
||||||
} :4;
|
} :4;
|
||||||
} ccrFields;
|
} ccrFields;
|
||||||
}
|
};
|
||||||
uint8_t asi; // Address Space Identifier
|
uint8_t asi; // Address Space Identifier
|
||||||
uint8_t tl; // Trap Level
|
uint8_t tl; // Trap Level
|
||||||
uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level)
|
uint64_t tpc[MaxTL]; // Trap Program Counter (value from
|
||||||
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level)
|
// previous trap level)
|
||||||
|
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
|
||||||
|
// previous trap level)
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
uint64_t tstate[MaxTL]; // Trap State
|
uint64_t tstate[MaxTL]; // Trap State
|
||||||
|
@ -257,7 +248,7 @@ class SPARCISA
|
||||||
uint64_t asi:8; // Address Space Identifier
|
uint64_t asi:8; // Address Space Identifier
|
||||||
uint64_t ccr:8; // Condition Code Register
|
uint64_t ccr:8; // Condition Code Register
|
||||||
} tstateFields[MaxTL];
|
} tstateFields[MaxTL];
|
||||||
}
|
};
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
uint64_t tick; // Hardware clock-tick counter
|
uint64_t tick; // Hardware clock-tick counter
|
||||||
|
@ -281,7 +272,7 @@ class SPARCISA
|
||||||
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
|
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
|
||||||
// register window trap
|
// register window trap
|
||||||
} wstateFields;
|
} wstateFields;
|
||||||
}
|
};
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
uint64_t ver; // Version
|
uint64_t ver; // Version
|
||||||
|
@ -295,7 +286,7 @@ class SPARCISA
|
||||||
uint64_t impl:16; // Implementation identification number
|
uint64_t impl:16; // Implementation identification number
|
||||||
uint64_t manuf:16; // Manufacturer code
|
uint64_t manuf:16; // Manufacturer code
|
||||||
} verFields;
|
} verFields;
|
||||||
}
|
};
|
||||||
union
|
union
|
||||||
{
|
{
|
||||||
uint64_t fsr; // Floating-Point State Register
|
uint64_t fsr; // Floating-Point State Register
|
||||||
|
@ -358,8 +349,8 @@ class SPARCISA
|
||||||
uint8_t fprs; // Floating-Point Register State
|
uint8_t fprs; // Floating-Point Register State
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
dl:1; // Dirty lower
|
uint8_t dl:1; // Dirty lower
|
||||||
du:1; // Dirty upper
|
uint8_t du:1; // Dirty upper
|
||||||
fef:1; // FPRS enable floating-Point
|
fef:1; // FPRS enable floating-Point
|
||||||
} fprsFields;
|
} fprsFields;
|
||||||
};
|
};
|
||||||
|
@ -435,7 +426,7 @@ class SPARCISA
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
};
|
};
|
||||||
|
|
||||||
static StaticInstPtr<AlphaISA> decodeInst(MachInst);
|
static StaticInstPtr decodeInst(MachInst);
|
||||||
|
|
||||||
// return a no-op instruction... used for instruction fetch faults
|
// return a no-op instruction... used for instruction fetch faults
|
||||||
static const MachInst NoopMachInst;
|
static const MachInst NoopMachInst;
|
||||||
|
@ -466,29 +457,15 @@ class SPARCISA
|
||||||
static void zeroRegisters(XC *xc);
|
static void zeroRegisters(XC *xc);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
typedef SPARCISA TheISA;
|
|
||||||
|
|
||||||
typedef TheISA::MachInst MachInst;
|
|
||||||
typedef TheISA::Addr Addr;
|
|
||||||
typedef TheISA::RegIndex RegIndex;
|
|
||||||
typedef TheISA::IntReg IntReg;
|
|
||||||
typedef TheISA::IntRegFile IntRegFile;
|
|
||||||
typedef TheISA::FloatReg FloatReg;
|
|
||||||
typedef TheISA::FloatRegFile FloatRegFile;
|
|
||||||
typedef TheISA::MiscReg MiscReg;
|
|
||||||
typedef TheISA::MiscRegFile MiscRegFile;
|
|
||||||
typedef TheISA::AnyReg AnyReg;
|
|
||||||
typedef TheISA::RegFile RegFile;
|
|
||||||
|
|
||||||
const int VMPageSize = TheISA::VMPageSize;
|
const int VMPageSize = TheISA::VMPageSize;
|
||||||
const int LogVMPageSize = TheISA::LogVMPageSize;
|
const int LogVMPageSize = TheISA::LogVMPageSize;
|
||||||
const int ZeroReg = TheISA::ZeroReg;
|
const int ZeroReg = TheISA::ZeroReg;
|
||||||
const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
|
const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
|
||||||
const int MaxAddr = (Addr)-1;
|
const int MaxAddr = (Addr)-1;
|
||||||
|
|
||||||
#ifndef FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
class SyscallReturn {
|
class SyscallReturn
|
||||||
|
{
|
||||||
public:
|
public:
|
||||||
template <class T>
|
template <class T>
|
||||||
SyscallReturn(T v, bool s)
|
SyscallReturn(T v, bool s)
|
||||||
|
@ -506,7 +483,8 @@ class SyscallReturn {
|
||||||
|
|
||||||
~SyscallReturn() {}
|
~SyscallReturn() {}
|
||||||
|
|
||||||
SyscallReturn& operator=(const SyscallReturn& s) {
|
SyscallReturn& operator=(const SyscallReturn& s)
|
||||||
|
{
|
||||||
retval = s.retval;
|
retval = s.retval;
|
||||||
success = s.success;
|
success = s.success;
|
||||||
return *this;
|
return *this;
|
||||||
|
@ -515,7 +493,6 @@ class SyscallReturn {
|
||||||
bool successful() { return success; }
|
bool successful() { return success; }
|
||||||
uint64_t value() { return retval; }
|
uint64_t value() { return retval; }
|
||||||
|
|
||||||
|
|
||||||
private:
|
private:
|
||||||
uint64_t retval;
|
uint64_t retval;
|
||||||
bool success;
|
bool success;
|
||||||
|
@ -524,7 +501,7 @@ class SyscallReturn {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
#ifdef FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
|
|
||||||
#include "arch/alpha/ev5.hh"
|
#include "arch/alpha/ev5.hh"
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -27,7 +27,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "arch/sparc/common_syscall_emul.hh"
|
#include "arch/sparc/common_syscall_emul.hh"
|
||||||
#include "arch/sparc/linux_process.hh"
|
#include "arch/sparc/linux/process.hh"
|
||||||
#include "arch/sparc/isa_traits.hh"
|
#include "arch/sparc/isa_traits.hh"
|
||||||
|
|
||||||
#include "base/trace.hh"
|
#include "base/trace.hh"
|
|
@ -29,7 +29,7 @@
|
||||||
#ifndef __SPARC_PROCESS_HH__
|
#ifndef __SPARC_PROCESS_HH__
|
||||||
#define __SPARC_PROCESS_HH__
|
#define __SPARC_PROCESS_HH__
|
||||||
|
|
||||||
#include "arch/sparc/linux_process.hh"
|
#include "arch/sparc/linux/process.hh"
|
||||||
#include "base/loader/object_file.hh"
|
#include "base/loader/object_file.hh"
|
||||||
|
|
||||||
namespace SparcISA
|
namespace SparcISA
|
||||||
|
|
|
@ -341,11 +341,11 @@ for build_dir in build_dirs:
|
||||||
sticky_opts.files = []
|
sticky_opts.files = []
|
||||||
# Name of default options file is taken from 'default=' on command
|
# Name of default options file is taken from 'default=' on command
|
||||||
# line if set, otherwise name of build dir.
|
# line if set, otherwise name of build dir.
|
||||||
default_options_file = os.path.join('build_options', 'default',
|
default_options_file = os.path.join('default_options',
|
||||||
ARGUMENTS.get('default', build_dir))
|
ARGUMENTS.get('default', build_dir))
|
||||||
if os.path.isfile(default_options_file):
|
if os.path.isfile(default_options_file):
|
||||||
sticky_opts.files.append(default_options_file)
|
sticky_opts.files.append(default_options_file)
|
||||||
current_options_file = os.path.join('build_options', 'current', build_dir)
|
current_options_file = os.path.join('options', build_dir)
|
||||||
if os.path.isfile(current_options_file):
|
if os.path.isfile(current_options_file):
|
||||||
sticky_opts.files.append(current_options_file)
|
sticky_opts.files.append(current_options_file)
|
||||||
else:
|
else:
|
||||||
|
@ -355,7 +355,7 @@ for build_dir in build_dirs:
|
||||||
if not os.path.isdir(opt_dir):
|
if not os.path.isdir(opt_dir):
|
||||||
os.mkdir(opt_dir)
|
os.mkdir(opt_dir)
|
||||||
if not sticky_opts.files:
|
if not sticky_opts.files:
|
||||||
print "%s: No options file found in build_options, using defaults." \
|
print "%s: No options file found in options, using defaults." \
|
||||||
% build_dir
|
% build_dir
|
||||||
|
|
||||||
# Apply current option settings to env
|
# Apply current option settings to env
|
||||||
|
|
|
@ -137,19 +137,6 @@ Statistics::regStats(const string &_name)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* _faults
|
|
||||||
.init(NumFaults)
|
|
||||||
.name(name() + ".faults")
|
|
||||||
.desc("number of faults")
|
|
||||||
.flags(total | pdf | nozero | nonan)
|
|
||||||
;
|
|
||||||
|
|
||||||
for (int i = 1; i < NumFaults; ++i) {
|
|
||||||
const char *str = (*ListOfFaults[i])->name;
|
|
||||||
if (str)
|
|
||||||
_faults.subname(i, str);
|
|
||||||
}*/
|
|
||||||
|
|
||||||
_mode
|
_mode
|
||||||
.init(cpu_mode_num)
|
.init(cpu_mode_num)
|
||||||
.name(name() + ".mode_switch")
|
.name(name() + ".mode_switch")
|
||||||
|
|
|
@ -175,11 +175,6 @@ class Statistics : public Serializable
|
||||||
void ivlb() { _ivlb++; }
|
void ivlb() { _ivlb++; }
|
||||||
void ivle() { _ivle++; }
|
void ivle() { _ivle++; }
|
||||||
void hwrei() { _hwrei++; }
|
void hwrei() { _hwrei++; }
|
||||||
void fault(Fault fault)
|
|
||||||
{
|
|
||||||
if(fault != NoFault)
|
|
||||||
fault->stat()++;
|
|
||||||
}// FIXME: When there are no generic system fault objects, this will go back to _faults[fault]++; }
|
|
||||||
void swpipl(int ipl);
|
void swpipl(int ipl);
|
||||||
void mode(cpu_mode newmode, ExecContext *xc);
|
void mode(cpu_mode newmode, ExecContext *xc);
|
||||||
void context(Addr oldpcbb, Addr newpcbb, ExecContext *xc);
|
void context(Addr oldpcbb, Addr newpcbb, ExecContext *xc);
|
||||||
|
|
|
@ -28,10 +28,19 @@
|
||||||
|
|
||||||
#include "sim/faults.hh"
|
#include "sim/faults.hh"
|
||||||
#include "cpu/exec_context.hh"
|
#include "cpu/exec_context.hh"
|
||||||
|
#include "cpu/base.hh"
|
||||||
|
|
||||||
#if !FULL_SYSTEM
|
#if !FULL_SYSTEM
|
||||||
void FaultBase::invoke(ExecContext * xc)
|
void FaultBase::invoke(ExecContext * xc)
|
||||||
{
|
{
|
||||||
fatal("fault (%s) detected @ PC 0x%08p", name(), xc->readPC());
|
fatal("fault (%s) detected @ PC 0x%08p", name(), xc->readPC());
|
||||||
}
|
}
|
||||||
|
#else
|
||||||
|
void FaultBase::invoke(ExecContext * xc)
|
||||||
|
{
|
||||||
|
DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
|
||||||
|
xc->cpu->recordEvent(csprintf("Fault %s", name()));
|
||||||
|
|
||||||
|
assert(!xc->misspeculating());
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -51,9 +51,8 @@ class FaultBase : public RefCounted
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
virtual FaultName name() = 0;
|
virtual FaultName name() = 0;
|
||||||
virtual FaultStat & stat() = 0;
|
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
virtual void invoke(ExecContext * xc) = 0;
|
virtual void invoke(ExecContext * xc);
|
||||||
#else
|
#else
|
||||||
virtual void invoke(ExecContext * xc);
|
virtual void invoke(ExecContext * xc);
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in a new issue