Get basic full-system working with AtomicSimpleCPU.

SConscript:
    Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
    Fix paths.
configs/test/fs.py:
    SimpleCPU -> AtomicSimpleCPU
    Fix vmlinux path
cpu/simple/atomic.cc:
    Fix suspendContext() so quiesce works.
    Don't forget to checkForInterrupts().
cpu/simple/base.cc:
    Minor fix to interrupt check code.
dev/ide_disk.hh:
    Don't declare regStats() in header since it's not in
    .cc file anymore (will need to add it back in when
    stats are added back).
dev/io_device.cc:
    Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
    Set PCI config packet result to Success.
python/m5/objects/Root.py:
    Add debug object to Root so things like break_cycles
    can be set from command line.

--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
This commit is contained in:
Steve Reinhardt 2006-05-17 22:08:44 -04:00
parent 5da14ec60a
commit 935ba67b4f
9 changed files with 23 additions and 19 deletions

View file

@ -207,7 +207,6 @@ full_system_sources = Split('''
dev/platform.cc dev/platform.cc
dev/simconsole.cc dev/simconsole.cc
dev/simple_disk.cc dev/simple_disk.cc
dev/sinic.cc
dev/tsunami.cc dev/tsunami.cc
dev/tsunami_cchip.cc dev/tsunami_cchip.cc
dev/tsunami_io.cc dev/tsunami_io.cc
@ -228,6 +227,7 @@ full_system_sources = Split('''
sim/pseudo_inst.cc sim/pseudo_inst.cc
''') ''')
# dev/sinic.cc
if env['TARGET_ISA'] == 'alpha': if env['TARGET_ISA'] == 'alpha':

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@ -22,11 +22,11 @@ BINDIR = SYSTEMDIR + '/binaries'
DISKDIR = SYSTEMDIR + '/disks' DISKDIR = SYSTEMDIR + '/disks'
def disk(file): def disk(file):
return '%s/%s' % (DISKDIR, file) return os.path.join(DISKDIR, file)
def binary(file): def binary(file):
return '%s/%s' % (BINDIR, file) return os.path.join(BINDIR, file)
def script(file): def script(file):
return '%s/%s' % ('/z/saidi/work/m5.newmem/configs/boot', file) return os.path.join(SYSTEMDIR, 'boot', file)

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@ -181,9 +181,9 @@ class LinuxAlphaSystem(LinuxAlphaSystem):
read_only=True) read_only=True)
simple_disk = SimpleDisk(disk=Parent.raw_image) simple_disk = SimpleDisk(disk=Parent.raw_image)
intrctrl = IntrControl() intrctrl = IntrControl()
cpu = SimpleCPU(mem=Parent.magicbus2) cpu = AtomicSimpleCPU(mem=Parent.magicbus2)
sim_console = SimConsole(listener=ConsoleListener(port=3456)) sim_console = SimConsole(listener=ConsoleListener(port=3456))
kernel = '/z/saidi/work/m5.newmem/build/vmlinux' kernel = binary('vmlinux')
pal = binary('ts_osfpal') pal = binary('ts_osfpal')
console = binary('console') console = binary('console')
boot_osflags = 'root=/dev/hda1 console=ttyS0' boot_osflags = 'root=/dev/hda1 console=ttyS0'

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@ -100,6 +100,9 @@ AtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt)
void void
AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
{ {
if (status == RangeChange)
return;
panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
} }
@ -227,10 +230,13 @@ AtomicSimpleCPU::suspendContext(int thread_num)
assert(cpuXC); assert(cpuXC);
assert(_status == Running); assert(_status == Running);
assert(tickEvent.scheduled());
// tick event may not be scheduled if this gets called from inside
// an instruction's execution, e.g. "quiesce"
if (tickEvent.scheduled())
tickEvent.deschedule();
notIdleFraction--; notIdleFraction--;
tickEvent.deschedule();
_status = Idle; _status = Idle;
} }
@ -417,6 +423,8 @@ AtomicSimpleCPU::tick()
for (int i = 0; i < width; ++i) { for (int i = 0; i < width; ++i) {
numCycles++; numCycles++;
checkForInterrupts();
ifetch_req->resetMin(); ifetch_req->resetMin();
ifetch_pkt->reset(); ifetch_pkt->reset();
Fault fault = setupFetchPacket(ifetch_pkt); Fault fault = setupFetchPacket(ifetch_pkt);
@ -452,6 +460,7 @@ AtomicSimpleCPU::tick()
advancePC(fault); advancePC(fault);
} }
if (_status != Idle)
tickEvent.schedule(curTick + latency); tickEvent.schedule(curTick + latency);
} }

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@ -307,8 +307,7 @@ void
BaseSimpleCPU::checkForInterrupts() BaseSimpleCPU::checkForInterrupts()
{ {
#if FULL_SYSTEM #if FULL_SYSTEM
if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() && if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) {
status() != IcacheAccessComplete) {
int ipl = 0; int ipl = 0;
int summary = 0; int summary = 0;
checkInterrupts = false; checkInterrupts = false;

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@ -259,12 +259,6 @@ class IdeDisk : public SimObject
*/ */
void reset(int id); void reset(int id);
/**
* Register statistics.
*/
void regStats();
/** /**
* Set the controller for this device * Set the controller for this device
* @param c The IDE controller * @param c The IDE controller

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@ -160,8 +160,7 @@ DmaPort::dmaAction(Command cmd, Addr addr, int size, Event *event,
basePkt.flags = 0; basePkt.flags = 0;
basePkt.coherence = NULL; basePkt.coherence = NULL;
basePkt.senderState = NULL; basePkt.senderState = NULL;
basePkt.src = 0; basePkt.dest = Packet::Broadcast;
basePkt.dest = 0;
basePkt.cmd = cmd; basePkt.cmd = cmd;
basePkt.result = Unknown; basePkt.result = Unknown;
basePkt.req = NULL; basePkt.req = NULL;

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@ -165,6 +165,7 @@ PciConfigAll::write(Packet &pkt)
default: default:
panic("invalid pci config write size\n"); panic("invalid pci config write size\n");
} }
pkt.result = Success;
return pioDelay; return pioDelay;
} }

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@ -3,6 +3,7 @@ from Serialize import Serialize
from Statistics import Statistics from Statistics import Statistics
from Trace import Trace from Trace import Trace
from ExeTrace import ExecutionTrace from ExeTrace import ExecutionTrace
from Debug import Debug
class Root(SimObject): class Root(SimObject):
type = 'Root' type = 'Root'
@ -19,3 +20,4 @@ class Root(SimObject):
trace = Trace() trace = Trace()
exetrace = ExecutionTrace() exetrace = ExecutionTrace()
serialize = Serialize() serialize = Serialize()
debug = Debug()