X86: Remove FULL_SYSTEM from the x86 faults.
This commit is contained in:
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51f7a66660
commit
91dd72a99a
3 changed files with 78 additions and 89 deletions
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@ -64,8 +64,9 @@ if env['TARGET_ISA'] == 'x86':
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Source('utility.cc')
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Source('utility.cc')
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SimObject('X86NativeTrace.py')
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SimObject('X86NativeTrace.py')
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SimObject('X86TLB.py')
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SimObject('X86TLB.py')
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DebugFlag('Faults', "Trace all faults/exceptions/traps")
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DebugFlag('Predecoder', "Predecoder debug output")
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DebugFlag('Predecoder', "Predecoder debug output")
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DebugFlag('X86', "Generic X86 ISA debugging")
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DebugFlag('X86', "Generic X86 ISA debugging")
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@ -73,7 +74,6 @@ if env['TARGET_ISA'] == 'x86':
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DebugFlag('LocalApic', "Local APIC debugging")
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DebugFlag('LocalApic', "Local APIC debugging")
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DebugFlag('PageTableWalker', \
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DebugFlag('PageTableWalker', \
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"Page table walker state machine debugging")
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"Page table walker state machine debugging")
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DebugFlag('Faults', "Trace all faults/exceptions/traps")
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SimObject('X86LocalApic.py')
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SimObject('X86LocalApic.py')
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SimObject('X86System.py')
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SimObject('X86System.py')
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@ -42,27 +42,21 @@
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#include "arch/x86/decoder.hh"
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#include "arch/x86/decoder.hh"
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#include "arch/x86/faults.hh"
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#include "arch/x86/faults.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#include "arch/x86/isa_traits.hh"
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#include "arch/x86/isa_traits.hh"
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#include "mem/page_table.hh"
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#include "base/trace.hh"
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#include "sim/process.hh"
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#include "cpu/thread_context.hh"
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#else
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#include "arch/x86/tlb.hh"
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#include "debug/Faults.hh"
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#include "debug/Faults.hh"
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#endif
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#include "sim/full_system.hh"
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namespace X86ISA
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namespace X86ISA
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{
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{
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#if FULL_SYSTEM
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void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
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void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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{
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if (FullSystem) {
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PCState pcState = tc->pcState();
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PCState pcState = tc->pcState();
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Addr pc = pcState.pc();
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Addr pc = pcState.pc();
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DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
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DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
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pc, vector, describe());
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using namespace X86ISAInst::RomLabels;
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using namespace X86ISAInst::RomLabels;
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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MicroPC entry;
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MicroPC entry;
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@ -84,14 +78,17 @@ namespace X86ISA
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panic("Legacy mode interrupts with error codes "
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panic("Legacy mode interrupts with error codes "
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"aren't implementde.\n");
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"aren't implementde.\n");
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}
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}
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// Software interrupts shouldn't have error codes. If one does,
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// Software interrupts shouldn't have error codes. If one
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// there would need to be microcode to set it up.
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// does, there would need to be microcode to set it up.
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assert(!isSoft());
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assert(!isSoft());
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tc->setIntReg(INTREG_MICRO(15), errorCode);
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tc->setIntReg(INTREG_MICRO(15), errorCode);
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}
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}
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pcState.upc(romMicroPC(entry));
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pcState.upc(romMicroPC(entry));
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pcState.nupc(romMicroPC(entry) + 1);
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pcState.nupc(romMicroPC(entry) + 1);
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tc->pcState(pcState);
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tc->pcState(pcState);
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} else {
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FaultBase::invoke(tc, inst);
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}
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}
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}
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std::string
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std::string
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@ -109,30 +106,57 @@ namespace X86ISA
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void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
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void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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{
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X86FaultBase::invoke(tc);
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X86FaultBase::invoke(tc);
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// This is the same as a fault, but it happens -after- the instruction.
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if (FullSystem) {
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// This is the same as a fault, but it happens -after- the
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// instruction.
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PCState pc = tc->pcState();
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PCState pc = tc->pcState();
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pc.uEnd();
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pc.uEnd();
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}
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}
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}
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void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
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void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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{
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panic("Abort exception!");
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panic("Abort exception!");
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}
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}
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void
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InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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if (FullSystem) {
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X86Fault::invoke(tc, inst);
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} else {
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panic("Unrecognized/invalid instruction executed:\n %s",
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inst->machInst);
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}
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}
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void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
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void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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{
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if (FullSystem) {
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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X86FaultBase::invoke(tc);
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X86FaultBase::invoke(tc);
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/*
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/*
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* If something bad happens while trying to enter the page fault
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* If something bad happens while trying to enter the page fault
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* handler, I'm pretty sure that's a double fault and then all bets are
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* handler, I'm pretty sure that's a double fault and then all
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* off. That means it should be safe to update this state now.
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* bets are off. That means it should be safe to update this
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* state now.
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*/
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*/
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if (m5reg.mode == LongMode) {
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if (m5reg.mode == LongMode) {
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tc->setMiscReg(MISCREG_CR2, addr);
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tc->setMiscReg(MISCREG_CR2, addr);
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} else {
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} else {
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tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
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tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
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}
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}
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} else {
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PageFaultErrorCode code = errorCode;
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const char *modeStr = "";
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if (code.fetch)
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modeStr = "execute";
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else if (code.write)
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modeStr = "write";
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else
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modeStr = "read";
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panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
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}
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}
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}
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std::string
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std::string
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@ -268,30 +292,5 @@ namespace X86ISA
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tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
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tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
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}
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}
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#else
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void
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InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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panic("Unrecognized/invalid instruction executed:\n %s",
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inst->machInst);
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}
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void
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PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
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{
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PageFaultErrorCode code = errorCode;
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const char *modeStr = "";
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if (code.fetch)
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modeStr = "execute";
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else if (code.write)
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modeStr = "write";
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else
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modeStr = "read";
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panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
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}
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#endif
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} // namespace X86ISA
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} // namespace X86ISA
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@ -85,12 +85,10 @@ namespace X86ISA
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return false;
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return false;
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}
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}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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virtual std::string describe() const;
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virtual std::string describe() const;
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#endif
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};
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};
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// Base class for x86 faults which behave as if the underlying instruction
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// Base class for x86 faults which behave as if the underlying instruction
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@ -114,10 +112,8 @@ namespace X86ISA
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: X86FaultBase(name, mnem, vector, _errorCode)
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: X86FaultBase(name, mnem, vector, _errorCode)
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{}
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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};
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// Base class for x86 aborts which seem to be catastrophic failures.
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// Base class for x86 aborts which seem to be catastrophic failures.
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@ -129,10 +125,8 @@ namespace X86ISA
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: X86FaultBase(name, mnem, vector, _errorCode)
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: X86FaultBase(name, mnem, vector, _errorCode)
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{}
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc,
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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};
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// Base class for x86 interrupts.
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// Base class for x86 interrupts.
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@ -246,10 +240,8 @@ namespace X86ISA
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X86Fault("Invalid-Opcode", "#UD", 6)
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X86Fault("Invalid-Opcode", "#UD", 6)
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{}
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{}
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#if !FULL_SYSTEM
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void invoke(ThreadContext * tc,
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#endif
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};
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};
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class DeviceNotAvailable : public X86Fault
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class DeviceNotAvailable : public X86Fault
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@ -334,9 +326,7 @@ namespace X86ISA
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void invoke(ThreadContext * tc,
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void invoke(ThreadContext * tc,
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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#if FULL_SYSTEM
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virtual std::string describe() const;
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virtual std::string describe() const;
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#endif
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};
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};
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class X87FpExceptionPending : public X86Fault
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class X87FpExceptionPending : public X86Fault
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