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Return an UnimpFault for an ITB translation of an uncachable address. We don't support fetching from uncached addresses in Alpha and it means that a speculative fetch can clobber device registers.

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This commit is contained in:
Ali Saidi 2008-08-13 16:29:59 -04:00
parent 1b1a7e33e7
commit 91d968783e
2 changed files with 9 additions and 3 deletions
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10
src/arch/alpha/tlb.cc
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@ -116,7 +116,7 @@ TLB::lookup(Addr vpn, uint8_t asn)
Fault Fault
TLB::checkCacheability(RequestPtr &req) TLB::checkCacheability(RequestPtr &req, bool itb)
{ {
// in Alpha, cacheability is controlled by upper-level bits of the // in Alpha, cacheability is controlled by upper-level bits of the
// physical address // physical address
@ -148,6 +148,12 @@ TLB::checkCacheability(RequestPtr &req)
req->setPaddr(req->getPaddr() & PAddrUncachedMask); req->setPaddr(req->getPaddr() & PAddrUncachedMask);
#endif #endif
} }
// We shouldn't be able to read from an uncachable address in Alpha as
// we don't have a ROM and we don't want to try to fetch from a device
// register as we destroy any data that is clear-on-read.
if (req->isUncacheable() && itb)
return new UnimpFault("CPU trying to fetch from uncached I/O");
} }
return NoFault; return NoFault;
} }
@ -390,7 +396,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
if (req->getPaddr() & ~PAddrImplMask) if (req->getPaddr() & ~PAddrImplMask)
return genMachineCheckFault(); return genMachineCheckFault();
return checkCacheability(req); return checkCacheability(req, true);
} }

2
src/arch/alpha/tlb.hh
View file

@ -92,7 +92,7 @@ namespace AlphaISA
return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
} }
static Fault checkCacheability(RequestPtr &req); static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing // Checkpointing
virtual void serialize(std::ostream &os); virtual void serialize(std::ostream &os);