tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which worked as long as we never attempted to switch CPUs or checked that a CPU was in a memory system with the correct mode. Future changes will make CPUs verify that they're operating in the correct mode and thus we need to always set it.
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f32f372455
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90bd20aae2
7 changed files with 16 additions and 7 deletions
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@ -40,7 +40,8 @@ cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleDRAM(),
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membus = CoherentBus())
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membus = CoherentBus(),
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mem_mode = "timing")
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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# create the interrupt controller
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@ -53,7 +53,8 @@ cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleDRAM(),
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membus = CoherentBus())
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membus = CoherentBus(),
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mem_mode = "timing")
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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cpu.connectAllPorts(system.membus)
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@ -38,7 +38,8 @@ import ruby_config
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ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
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# system simulated
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system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
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system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
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mem_mode = "timing")
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for cpu in cpus:
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# create the interrupt controller
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@ -35,7 +35,10 @@ nb_cores = 4
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cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
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system = System(cpu = cpus,
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physmem = SimpleDRAM(),
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membus = CoherentBus(),
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mem_mode = "timing")
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock = '2GHz')
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@ -40,7 +40,8 @@ cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = ruby_memory,
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membus = CoherentBus())
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membus = CoherentBus(),
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mem_mode = "timing")
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system.physmem.port = system.membus.master
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# create the interrupt controller
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cpu.createInterruptController()
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@ -42,7 +42,8 @@ cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleDRAM(),
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membus = CoherentBus())
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membus = CoherentBus(),
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mem_mode = "timing")
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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# create the interrupt controller
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@ -37,7 +37,8 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
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L2Cache(size = '2MB'))
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system = System(cpu = cpu,
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physmem = SimpleMemory(),
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membus = CoherentBus())
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membus = CoherentBus(),
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mem_mode = "timing")
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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# create the interrupt controller
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