Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/ehallnor/work/m5 --HG-- extra : convert_revision : 3f1842ffa9c193fbbdcfefb5aa364671b3d90785
This commit is contained in:
commit
8efb592e0b
5 changed files with 41 additions and 74 deletions
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@ -173,6 +173,7 @@ base_sources = Split('''
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mem/timing_mem/base_memory.cc
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mem/timing_mem/base_memory.cc
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mem/timing_mem/memory_builder.cc
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mem/timing_mem/memory_builder.cc
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mem/timing_mem/simple_mem_bank.cc
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mem/timing_mem/simple_mem_bank.cc
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mem/trace/itx_writer.cc
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mem/trace/mem_trace_writer.cc
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mem/trace/mem_trace_writer.cc
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mem/trace/m5_writer.cc
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mem/trace/m5_writer.cc
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@ -130,6 +130,7 @@ ITXReader::getNextReq(MemReqPtr &req)
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// Get the page offset from the virtual address.
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// Get the page offset from the virtual address.
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tmp_req->paddr = tmp_req->vaddr & 0xfff;
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tmp_req->paddr = tmp_req->vaddr & 0xfff;
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tmp_req->paddr |= (c & 0xf0) << 8;
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tmp_req->paddr |= (c & 0xf0) << 8;
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tmp_req->paddr |= (Addr)(c & 0xf0) << 32;
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for (int i = 2; i < 4; ++i) {
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for (int i = 2; i < 4; ++i) {
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c = getc(trace);
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c = getc(trace);
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if (c == EOF) {
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if (c == EOF) {
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@ -160,6 +161,7 @@ ITXReader::getNextReq(MemReqPtr &req)
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break;
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break;
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case ITXCode:
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case ITXCode:
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tmp_req->cmd = Read;
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tmp_req->cmd = Read;
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tmp_req->flags |= INST_READ;
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break;
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break;
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default:
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default:
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fatal("Unknown ITX type");
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fatal("Unknown ITX type");
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@ -35,6 +35,7 @@
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#define __ITX_READER_HH__
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#define __ITX_READER_HH__
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#include <stdio.h>
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#include <stdio.h>
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#include <string>
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#include "cpu/trace/reader/mem_trace_reader.hh"
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#include "cpu/trace/reader/mem_trace_reader.hh"
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#include "mem/mem_req.hh"
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#include "mem/mem_req.hh"
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@ -46,23 +46,13 @@ using namespace std;
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TraceCPU::TraceCPU(const string &name,
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TraceCPU::TraceCPU(const string &name,
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MemInterface *icache_interface,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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MemInterface *dcache_interface,
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MemTraceReader *inst_trace,
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MemTraceReader *data_trace)
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MemTraceReader *data_trace,
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int icache_ports,
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int dcache_ports)
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: BaseCPU(name, 4), icacheInterface(icache_interface),
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: BaseCPU(name, 4), icacheInterface(icache_interface),
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dcacheInterface(dcache_interface), instTrace(inst_trace),
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dcacheInterface(dcache_interface),
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dataTrace(data_trace), icachePorts(icache_ports),
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dataTrace(data_trace), outstandingRequests(0), tickEvent(this)
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dcachePorts(dcache_ports), outstandingRequests(0), tickEvent(this)
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{
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{
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if (instTrace) {
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assert(icacheInterface);
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nextInstCycle = instTrace->getNextReq(nextInstReq);
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}
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if (dataTrace) {
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assert(dcacheInterface);
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assert(dcacheInterface);
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nextDataCycle = dataTrace->getNextReq(nextDataReq);
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nextCycle = dataTrace->getNextReq(nextReq);
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}
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tickEvent.schedule(0);
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tickEvent.schedule(0);
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}
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}
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@ -74,41 +64,35 @@ TraceCPU::tick()
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int instReqs = 0;
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int instReqs = 0;
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int dataReqs = 0;
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int dataReqs = 0;
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// Do data first to match tracing with FullCPU dumps
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while (nextReq && curTick >= nextCycle) {
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assert(nextReq->thread_num < 4 && "Not enough threads");
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if (nextReq->isInstRead() && icacheInterface) {
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if (icacheInterface->isBlocked())
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break;
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while (nextDataReq && (dataReqs < dcachePorts) &&
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nextReq->time = curTick;
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curTick >= nextDataCycle) {
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if (nextReq->cmd == Squash) {
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assert(nextDataReq->thread_num < 4 && "Not enough threads");
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icacheInterface->squash(nextReq->asid);
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} else {
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++instReqs;
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nextReq->completionEvent =
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new TraceCompleteEvent(nextReq, this);
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icacheInterface->access(nextReq);
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}
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} else {
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if (dcacheInterface->isBlocked())
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if (dcacheInterface->isBlocked())
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break;
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break;
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++dataReqs;
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++dataReqs;
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nextDataReq->time = curTick;
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nextReq->time = curTick;
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nextDataReq->completionEvent =
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nextReq->completionEvent =
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new TraceCompleteEvent(nextDataReq, this);
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new TraceCompleteEvent(nextReq, this);
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dcacheInterface->access(nextDataReq);
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dcacheInterface->access(nextReq);
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nextDataCycle = dataTrace->getNextReq(nextDataReq);
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}
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nextCycle = dataTrace->getNextReq(nextReq);
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}
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}
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while (nextInstReq && (instReqs < icachePorts) &&
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if (!nextReq) {
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curTick >= nextInstCycle) {
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assert(nextInstReq->thread_num < 4 && "Not enough threads");
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if (icacheInterface->isBlocked())
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break;
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nextInstReq->time = curTick;
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if (nextInstReq->cmd == Squash) {
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icacheInterface->squash(nextInstReq->asid);
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} else {
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++instReqs;
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nextInstReq->completionEvent =
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new TraceCompleteEvent(nextInstReq, this);
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icacheInterface->access(nextInstReq);
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}
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nextInstCycle = instTrace->getNextReq(nextInstReq);
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}
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if (!nextInstReq && !nextDataReq) {
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// No more requests to send. Finish trailing events and exit.
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// No more requests to send. Finish trailing events and exit.
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if (mainEventQueue.empty()) {
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if (mainEventQueue.empty()) {
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new SimExitEvent("Finshed Memory Trace");
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new SimExitEvent("Finshed Memory Trace");
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@ -116,8 +100,7 @@ TraceCPU::tick()
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tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
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tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
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}
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}
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} else {
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} else {
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tickEvent.schedule(max(curTick + 1,
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tickEvent.schedule(max(curTick + 1, nextCycle));
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min(nextInstCycle, nextDataCycle)));
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}
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}
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}
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}
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@ -161,10 +144,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> dcache;
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SimObjectParam<BaseMem *> dcache;
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SimObjectParam<MemTraceReader *> inst_trace;
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SimObjectParam<MemTraceReader *> data_trace;
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SimObjectParam<MemTraceReader *> data_trace;
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Param<int> inst_ports;
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Param<int> data_ports;
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END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
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END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
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@ -172,10 +152,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
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INIT_PARAM_DFLT(icache, "instruction cache", NULL),
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INIT_PARAM_DFLT(icache, "instruction cache", NULL),
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INIT_PARAM_DFLT(dcache, "data cache", NULL),
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INIT_PARAM_DFLT(dcache, "data cache", NULL),
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INIT_PARAM_DFLT(inst_trace, "instruction trace", NULL),
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INIT_PARAM_DFLT(data_trace, "data trace", NULL)
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INIT_PARAM_DFLT(data_trace, "data trace", NULL),
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INIT_PARAM_DFLT(inst_ports, "instruction cache read ports", 4),
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INIT_PARAM_DFLT(data_ports, "data cache read/write ports", 4)
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END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
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END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
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@ -184,7 +161,7 @@ CREATE_SIM_OBJECT(TraceCPU)
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return new TraceCPU(getInstanceName(),
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return new TraceCPU(getInstanceName(),
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(icache) ? icache->getInterface() : NULL,
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(icache) ? icache->getInterface() : NULL,
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(dcache) ? dcache->getInterface() : NULL,
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(dcache) ? dcache->getInterface() : NULL,
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inst_trace, data_trace, inst_ports, data_ports);
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data_trace);
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}
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}
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REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
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REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
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@ -55,28 +55,17 @@ class TraceCPU : public BaseCPU
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/** Interface for data trace requests, if any. */
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/** Interface for data trace requests, if any. */
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MemInterface *dcacheInterface;
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MemInterface *dcacheInterface;
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/** Instruction reference trace. */
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MemTraceReader *instTrace;
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/** Data reference trace. */
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/** Data reference trace. */
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MemTraceReader *dataTrace;
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MemTraceReader *dataTrace;
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/** Number of Icache read ports. */
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int icachePorts;
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/** Number of Dcache read/write ports. */
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int dcachePorts;
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/** Number of outstanding requests. */
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/** Number of outstanding requests. */
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int outstandingRequests;
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int outstandingRequests;
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/** Cycle of the next instruction request, 0 if not available. */
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/** Cycle of the next request, 0 if not available. */
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Tick nextInstCycle;
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Tick nextCycle;
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/** Cycle of the next data request, 0 if not available. */
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Tick nextDataCycle;
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/** Next instruction request. */
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/** Next request. */
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MemReqPtr nextInstReq;
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MemReqPtr nextReq;
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/** Next data request. */
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MemReqPtr nextDataReq;
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/**
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/**
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* Event to call the TraceCPU::tick
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* Event to call the TraceCPU::tick
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@ -113,10 +102,7 @@ class TraceCPU : public BaseCPU
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TraceCPU(const std::string &name,
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TraceCPU(const std::string &name,
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MemInterface *icache_interface,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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MemInterface *dcache_interface,
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MemTraceReader *inst_trace,
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MemTraceReader *data_trace);
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MemTraceReader *data_trace,
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int icache_ports,
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int dcache_ports);
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/**
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/**
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* Perform all the accesses for one cycle.
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* Perform all the accesses for one cycle.
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