diff --git a/SConscript b/SConscript index f22c85059..ddd16564b 100644 --- a/SConscript +++ b/SConscript @@ -173,6 +173,7 @@ base_sources = Split(''' mem/timing_mem/base_memory.cc mem/timing_mem/memory_builder.cc mem/timing_mem/simple_mem_bank.cc + mem/trace/itx_writer.cc mem/trace/mem_trace_writer.cc mem/trace/m5_writer.cc diff --git a/cpu/trace/reader/itx_reader.cc b/cpu/trace/reader/itx_reader.cc index 593d383ec..615eb414e 100644 --- a/cpu/trace/reader/itx_reader.cc +++ b/cpu/trace/reader/itx_reader.cc @@ -130,6 +130,7 @@ ITXReader::getNextReq(MemReqPtr &req) // Get the page offset from the virtual address. tmp_req->paddr = tmp_req->vaddr & 0xfff; tmp_req->paddr |= (c & 0xf0) << 8; + tmp_req->paddr |= (Addr)(c & 0xf0) << 32; for (int i = 2; i < 4; ++i) { c = getc(trace); if (c == EOF) { @@ -160,6 +161,7 @@ ITXReader::getNextReq(MemReqPtr &req) break; case ITXCode: tmp_req->cmd = Read; + tmp_req->flags |= INST_READ; break; default: fatal("Unknown ITX type"); diff --git a/cpu/trace/reader/itx_reader.hh b/cpu/trace/reader/itx_reader.hh index 0e08d5db5..d45a16a69 100644 --- a/cpu/trace/reader/itx_reader.hh +++ b/cpu/trace/reader/itx_reader.hh @@ -35,6 +35,7 @@ #define __ITX_READER_HH__ #include +#include #include "cpu/trace/reader/mem_trace_reader.hh" #include "mem/mem_req.hh" diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc index 94f311d4b..e19509fec 100644 --- a/cpu/trace/trace_cpu.cc +++ b/cpu/trace/trace_cpu.cc @@ -46,23 +46,13 @@ using namespace std; TraceCPU::TraceCPU(const string &name, MemInterface *icache_interface, MemInterface *dcache_interface, - MemTraceReader *inst_trace, - MemTraceReader *data_trace, - int icache_ports, - int dcache_ports) + MemTraceReader *data_trace) : BaseCPU(name, 4), icacheInterface(icache_interface), - dcacheInterface(dcache_interface), instTrace(inst_trace), - dataTrace(data_trace), icachePorts(icache_ports), - dcachePorts(dcache_ports), outstandingRequests(0), tickEvent(this) + dcacheInterface(dcache_interface), + dataTrace(data_trace), outstandingRequests(0), tickEvent(this) { - if (instTrace) { - assert(icacheInterface); - nextInstCycle = instTrace->getNextReq(nextInstReq); - } - if (dataTrace) { - assert(dcacheInterface); - nextDataCycle = dataTrace->getNextReq(nextDataReq); - } + assert(dcacheInterface); + nextCycle = dataTrace->getNextReq(nextReq); tickEvent.schedule(0); } @@ -74,41 +64,35 @@ TraceCPU::tick() int instReqs = 0; int dataReqs = 0; - // Do data first to match tracing with FullCPU dumps + while (nextReq && curTick >= nextCycle) { + assert(nextReq->thread_num < 4 && "Not enough threads"); + if (nextReq->isInstRead() && icacheInterface) { + if (icacheInterface->isBlocked()) + break; - while (nextDataReq && (dataReqs < dcachePorts) && - curTick >= nextDataCycle) { - assert(nextDataReq->thread_num < 4 && "Not enough threads"); - if (dcacheInterface->isBlocked()) - break; - - ++dataReqs; - nextDataReq->time = curTick; - nextDataReq->completionEvent = - new TraceCompleteEvent(nextDataReq, this); - dcacheInterface->access(nextDataReq); - nextDataCycle = dataTrace->getNextReq(nextDataReq); - } - - while (nextInstReq && (instReqs < icachePorts) && - curTick >= nextInstCycle) { - assert(nextInstReq->thread_num < 4 && "Not enough threads"); - if (icacheInterface->isBlocked()) - break; - - nextInstReq->time = curTick; - if (nextInstReq->cmd == Squash) { - icacheInterface->squash(nextInstReq->asid); + nextReq->time = curTick; + if (nextReq->cmd == Squash) { + icacheInterface->squash(nextReq->asid); + } else { + ++instReqs; + nextReq->completionEvent = + new TraceCompleteEvent(nextReq, this); + icacheInterface->access(nextReq); + } } else { - ++instReqs; - nextInstReq->completionEvent = - new TraceCompleteEvent(nextInstReq, this); - icacheInterface->access(nextInstReq); + if (dcacheInterface->isBlocked()) + break; + + ++dataReqs; + nextReq->time = curTick; + nextReq->completionEvent = + new TraceCompleteEvent(nextReq, this); + dcacheInterface->access(nextReq); } - nextInstCycle = instTrace->getNextReq(nextInstReq); + nextCycle = dataTrace->getNextReq(nextReq); } - if (!nextInstReq && !nextDataReq) { + if (!nextReq) { // No more requests to send. Finish trailing events and exit. if (mainEventQueue.empty()) { new SimExitEvent("Finshed Memory Trace"); @@ -116,8 +100,7 @@ TraceCPU::tick() tickEvent.schedule(mainEventQueue.nextEventTime() + 1); } } else { - tickEvent.schedule(max(curTick + 1, - min(nextInstCycle, nextDataCycle))); + tickEvent.schedule(max(curTick + 1, nextCycle)); } } @@ -161,10 +144,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU) SimObjectParam icache; SimObjectParam dcache; - SimObjectParam inst_trace; SimObjectParam data_trace; - Param inst_ports; - Param data_ports; END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU) @@ -172,10 +152,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU) INIT_PARAM_DFLT(icache, "instruction cache", NULL), INIT_PARAM_DFLT(dcache, "data cache", NULL), - INIT_PARAM_DFLT(inst_trace, "instruction trace", NULL), - INIT_PARAM_DFLT(data_trace, "data trace", NULL), - INIT_PARAM_DFLT(inst_ports, "instruction cache read ports", 4), - INIT_PARAM_DFLT(data_ports, "data cache read/write ports", 4) + INIT_PARAM_DFLT(data_trace, "data trace", NULL) END_INIT_SIM_OBJECT_PARAMS(TraceCPU) @@ -184,7 +161,7 @@ CREATE_SIM_OBJECT(TraceCPU) return new TraceCPU(getInstanceName(), (icache) ? icache->getInterface() : NULL, (dcache) ? dcache->getInterface() : NULL, - inst_trace, data_trace, inst_ports, data_ports); + data_trace); } REGISTER_SIM_OBJECT("TraceCPU", TraceCPU) diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh index 6f3ef50a6..1711646a8 100644 --- a/cpu/trace/trace_cpu.hh +++ b/cpu/trace/trace_cpu.hh @@ -55,28 +55,17 @@ class TraceCPU : public BaseCPU /** Interface for data trace requests, if any. */ MemInterface *dcacheInterface; - /** Instruction reference trace. */ - MemTraceReader *instTrace; /** Data reference trace. */ MemTraceReader *dataTrace; - /** Number of Icache read ports. */ - int icachePorts; - /** Number of Dcache read/write ports. */ - int dcachePorts; - /** Number of outstanding requests. */ int outstandingRequests; - /** Cycle of the next instruction request, 0 if not available. */ - Tick nextInstCycle; - /** Cycle of the next data request, 0 if not available. */ - Tick nextDataCycle; + /** Cycle of the next request, 0 if not available. */ + Tick nextCycle; - /** Next instruction request. */ - MemReqPtr nextInstReq; - /** Next data request. */ - MemReqPtr nextDataReq; + /** Next request. */ + MemReqPtr nextReq; /** * Event to call the TraceCPU::tick @@ -113,10 +102,7 @@ class TraceCPU : public BaseCPU TraceCPU(const std::string &name, MemInterface *icache_interface, MemInterface *dcache_interface, - MemTraceReader *inst_trace, - MemTraceReader *data_trace, - int icache_ports, - int dcache_ports); + MemTraceReader *data_trace); /** * Perform all the accesses for one cycle.