mem: Add precharge all (PREA) to the DRAM controller
This patch adds the basic ingredients for a precharge all operation, to be used in conjunction with DRAM power modelling. Currently we do not try and apply any cleverness when precharging all banks, thus even if only a single bank is open we use PREA as opposed to PRE. At the moment we only have a single tRP (tRPpb), and do not model the slightly longer all-bank precharge constraint (tRPab).
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1 changed files with 26 additions and 5 deletions
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@ -850,6 +850,9 @@ DRAMCtrl::prechargeBank(Bank& bank, Tick pre_at)
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bank.openRow = Bank::NO_ROW;
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// no precharge allowed before this one
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bank.preAllowedAt = pre_at;
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Tick pre_done_at = pre_at + tRP;
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bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at);
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@ -1305,16 +1308,34 @@ DRAMCtrl::processRefreshEvent()
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// precharge any active bank if we are not already in the idle
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// state
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if (pwrState != PWR_IDLE) {
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// at the moment, we use a precharge all even if there is
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// only a single bank open
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DPRINTF(DRAM, "Precharging all\n");
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// first determine when we can precharge
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Tick pre_at = curTick();
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for (int i = 0; i < ranksPerChannel; i++) {
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for (int j = 0; j < banksPerRank; j++) {
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// respect both causality and any existing bank
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// constraints, some banks could already have a
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// (auto) precharge scheduled
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pre_at = std::max(banks[i][j].preAllowedAt, pre_at);
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}
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}
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// make sure all banks are precharged, and for those that
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// already are, update their availability
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Tick act_allowed_at = pre_at + tRP;
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for (int i = 0; i < ranksPerChannel; i++) {
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for (int j = 0; j < banksPerRank; j++) {
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if (banks[i][j].openRow != Bank::NO_ROW) {
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// respect both causality and any existing bank
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// constraints
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Tick pre_at = std::max(banks[i][j].preAllowedAt,
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curTick());
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prechargeBank(banks[i][j], pre_at);
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} else {
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banks[i][j].actAllowedAt =
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std::max(banks[i][j].actAllowedAt, act_allowed_at);
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banks[i][j].preAllowedAt =
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std::max(banks[i][j].preAllowedAt, pre_at);
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}
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}
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}
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