mem: Remove printing of DRAM params
This patch removes the redundant printing of DRAM params.
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6753cb705e
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2 changed files with 0 additions and 59 deletions
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@ -165,9 +165,6 @@ DRAMCtrl::startup()
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// start of simulation
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busBusyUntil = curTick() + tRP + tRCD + tCL;
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// print the configuration of the controller
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printParams();
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// kick off the refresh, and give ourselves enough time to
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// precharge
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schedule(refreshEvent, curTick() + tREFI - tRP);
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@ -512,60 +509,6 @@ DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
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}
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}
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void
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DRAMCtrl::printParams() const
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{
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// Sanity check print of important parameters
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DPRINTF(DRAM,
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"Memory controller %s physical organization\n" \
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"Number of devices per rank %d\n" \
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"Device bus width (in bits) %d\n" \
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"DRAM data bus burst (bytes) %d\n" \
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"Row buffer size (bytes) %d\n" \
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"Columns per row buffer %d\n" \
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"Rows per bank %d\n" \
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"Banks per rank %d\n" \
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"Ranks per channel %d\n" \
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"Total mem capacity (bytes) %u\n",
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name(), devicesPerRank, deviceBusWidth, burstSize, rowBufferSize,
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columnsPerRowBuffer, rowsPerBank, banksPerRank, ranksPerChannel,
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rowBufferSize * rowsPerBank * banksPerRank * ranksPerChannel);
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string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS";
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string address_mapping = addrMapping == Enums::RoRaBaChCo ? "RoRaBaChCo" :
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(addrMapping == Enums::RoRaBaCoCh ? "RoRaBaCoCh" : "RoCoRaBaCh");
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string page_policy = pageMgmt == Enums::open ? "OPEN" :
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(pageMgmt == Enums::open_adaptive ? "OPEN (adaptive)" :
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(pageMgmt == Enums::close_adaptive ? "CLOSE (adaptive)" : "CLOSE"));
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DPRINTF(DRAM,
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"Memory controller %s characteristics\n" \
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"Read buffer size %d\n" \
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"Write buffer size %d\n" \
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"Write high thresh %d\n" \
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"Write low thresh %d\n" \
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"Scheduler %s\n" \
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"Address mapping %s\n" \
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"Page policy %s\n",
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name(), readBufferSize, writeBufferSize, writeHighThreshold,
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writeLowThreshold, scheduler, address_mapping, page_policy);
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DPRINTF(DRAM, "Memory controller %s timing specs\n" \
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"tRCD %d ticks\n" \
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"tCL %d ticks\n" \
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"tRP %d ticks\n" \
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"tBURST %d ticks\n" \
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"tRFC %d ticks\n" \
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"tREFI %d ticks\n" \
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"tWTR %d ticks\n" \
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"tRTW %d ticks\n" \
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"tWR %d ticks\n" \
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"tRTP %d ticks\n" \
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"tXAW (%d) %d ticks\n",
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name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR,
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tRTW, tWR, tRTP, activationLimit, tXAW);
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}
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void
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DRAMCtrl::printQs() const {
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DPRINTF(DRAM, "===READ QUEUE===\n\n");
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@ -414,8 +414,6 @@ class DRAMCtrl : public AbstractMemory
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*/
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void prechargeBank(Bank& bank, Tick pre_at);
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void printParams() const;
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/**
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* Used for debugging to observe the contents of the queues.
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*/
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