sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

config: tweak ruby configs to clean up hierarchy

Browse source 
Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings.  This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
   caches children of the sequencer rather than the controller; these
   config ciles are rewritten to assign the L1 caches to the
   controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
   causes the sequencers to be children of system.ruby, generating
   warnings because they are already parented to their respective
   controllers.  Changing this attribute to _cpu_ruby_ports fixes this
   because the leading underscore means this is now treated as a plain
   Python attribute rather than a child assignment. As a result, the
   configuration hierarchy changes such that, e.g.,
   system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
   internal link node rather than direct children of the topology.
   The topology classes are rewritten to assign the routers to the
   topology object first.
This commit is contained in:
Steve Reinhardt 2011-05-23 14:29:23 -07:00
parent 41fc9bbab5
commit 8a652f9871
22 changed files with 138 additions and 118 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
configs/example/ruby_direct_test.py
View file

@ -99,9 +99,9 @@ system.tester = RubyDirectedTester(requests_to_complete = \
system.ruby = Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for ruby_port in system.ruby.cpu_ruby_ports:
for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#

8
configs/example/ruby_fs.py
View file

@ -128,11 +128,11 @@ for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = system.ruby.cpu_ruby_ports[i].port
cpu.dtb.walker.port = system.ruby.cpu_ruby_ports[i].port
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.interrupts.pio = system.piobus.port
cpu.interrupts.int_port = system.piobus.port

6
configs/example/ruby_mem_test.py
View file

@ -126,20 +126,20 @@ system.ruby = Ruby.create_system(options, \
#
system.ruby.randomization = True
assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
cpu.test = system.ruby.cpu_ruby_ports[i].port
cpu.test = system.ruby._cpu_ruby_ports[i].port
cpu.functional = system.funcmem.port
#
# Since the memtester is incredibly bursty, increase the deadlock
# threshold to 5 million cycles
#
system.ruby.cpu_ruby_ports[i].deadlock_threshold = 5000000
system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
for (i, dma) in enumerate(dmas):
#

2
configs/example/ruby_network_test.py
View file

@ -108,7 +108,7 @@ system = System(cpu = cpus,
system.ruby = Ruby.create_system(options, system)
i = 0
for ruby_port in system.ruby.cpu_ruby_ports:
for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the cpu test ports to the ruby cpu port
#

4
configs/example/ruby_random_test.py
View file

@ -101,7 +101,7 @@ system = System(tester = tester, physmem = PhysicalMemory())
system.ruby = Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
# The tester is most effective when randomization is turned on and
@ -109,7 +109,7 @@ assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
#
system.ruby.randomization = True
for ruby_port in system.ruby.cpu_ruby_ports:
for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#

6
configs/example/se.py
View file

@ -178,7 +178,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
if options.ruby:
options.use_map = True
system.ruby = Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
else:
system.physmem.port = system.membus.port
CacheConfig.config_cache(options, system)
@ -187,8 +187,8 @@ for i in xrange(np):
system.cpu[i].workload = multiprocesses[i]
if options.ruby:
system.cpu[i].icache_port = system.ruby.cpu_ruby_ports[i].port
system.cpu[i].dcache_port = system.ruby.cpu_ruby_ports[i].port
system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port

15
configs/ruby/MESI_CMP_directory.py
View file

@ -84,22 +84,23 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits)
exec("system.l1_cntrl%d = l1_cntrl" % i)
#

11
configs/ruby/MI_example.py
View file

@ -78,20 +78,21 @@ def create_system(options, system, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
cacheMemory = cache)
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
sequencer = cpu_seq,
cacheMemory = cache)
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists

15
configs/ruby/MOESI_CMP_directory.py
View file

@ -84,22 +84,23 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits)
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists

21
configs/ruby/MOESI_CMP_token.py
View file

@ -97,18 +97,8 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
if piobus != None:
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
@ -122,6 +112,17 @@ def create_system(options, system, piobus, dma_devices):
no_mig_atomic = not \
options.allow_atomic_migration)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists

19
configs/ruby/MOESI_hammer.py
View file

@ -96,24 +96,25 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l2_assoc,
start_index_bit = block_size_bits)
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
L2cacheMemory = l2_cache,
no_mig_atomic = not \
options.allow_atomic_migration)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
L2cacheMemory = l2_cache,
no_mig_atomic = not \
options.allow_atomic_migration)
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency

11
configs/ruby/Network_test.py
View file

@ -83,20 +83,21 @@ def create_system(options, system, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
cacheMemory = cache)
cpu_seq = RubySequencer(icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
using_network_tester = True)
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
sequencer = cpu_seq,
cacheMemory = cache)
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists

2
configs/ruby/Ruby.py
View file

@ -145,7 +145,7 @@ def create_system(options, system, piobus = None, dma_devices = []):
tracer = RubyTracer(),
mem_size = total_mem_size)
ruby.cpu_ruby_ports = cpu_sequencers
ruby._cpu_ruby_ports = cpu_sequencers
ruby.random_seed = options.random_seed
return ruby

13
src/mem/ruby/network/topologies/Crossbar.py
View file

@ -37,14 +37,15 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
# centralized crossbar. The large numbers of routers are needed because
# external links do not model outgoing bandwidth in the simple network, but
# internal links do.
routers = [Router(router_id=i) for i in range(len(nodes)+1)]
ext_links = [ExtLink(link_id=i, ext_node=n, int_node=routers[i])
cb = Crossbar()
cb.routers = [Router(router_id=i) for i in range(len(nodes)+1)]
cb.ext_links = [ExtLink(link_id=i, ext_node=n, int_node=cb.routers[i])
for (i, n) in enumerate(nodes)]
link_count = len(nodes)
xbar = routers[len(nodes)] # the crossbar router is the last router created
int_links = [IntLink(link_id=(link_count+i), node_a=routers[i], node_b=xbar)
xbar = cb.routers[len(nodes)] # the crossbar router is the last router created
cb.int_links = [IntLink(link_id=(link_count+i),
node_a=cb.routers[i], node_b=xbar)
for i in range(len(nodes))]
return Crossbar(ext_links=ext_links, int_links=int_links,
routers=routers)
return cb

25
src/mem/ruby/network/topologies/Mesh.py
View file

@ -46,8 +46,11 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
num_columns = int(num_routers / num_rows)
assert(num_columns * num_rows == num_routers)
# Create the mesh object
mesh = Mesh()
# Create the routers in the mesh
routers = [Router(router_id=i) for i in range(num_routers)]
mesh.routers = [Router(router_id=i) for i in range(num_routers)]
# link counter to set unique link ids
link_count = 0
@ -68,7 +71,7 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
cntrl_level, router_id = divmod(i, num_routers)
assert(cntrl_level < cntrls_per_router)
ext_links.append(ExtLink(link_id=link_count, ext_node=n,
int_node=routers[router_id]))
int_node=mesh.routers[router_id]))
link_count += 1
# Connect the remainding nodes to router 0. These should only be
@ -77,7 +80,7 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
assert(node.type == 'DMA_Controller')
assert(i < remainder)
ext_links.append(ExtLink(link_id=link_count, ext_node=node,
int_node=routers[0]))
int_node=mesh.routers[0]))
link_count += 1
# Create the mesh links. First row (east-west) links then column
@ -89,8 +92,8 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
east_id = col + (row * num_columns)
west_id = (col + 1) + (row * num_columns)
int_links.append(IntLink(link_id=link_count,
node_a=routers[east_id],
node_b=routers[west_id],
node_a=mesh.routers[east_id],
node_b=mesh.routers[west_id],
weight=1))
link_count += 1
@ -100,10 +103,12 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
north_id = col + (row * num_columns)
south_id = col + ((row + 1) * num_columns)
int_links.append(IntLink(link_id=link_count,
node_a=routers[north_id],
node_b=routers[south_id],
node_a=mesh.routers[north_id],
node_b=mesh.routers[south_id],
weight=2))
link_count += 1
return Mesh(ext_links=ext_links,
int_links=int_links,
routers=routers)
mesh.int_links = int_links
mesh.ext_links = ext_links
return mesh

30
src/mem/ruby/network/topologies/MeshDirCorners.py
View file

@ -65,8 +65,10 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
assert(remainder == 0)
assert(len(dir_nodes) == 4)
mesh = MeshDirCorners()
# Create the routers in the mesh
routers = [Router(router_id=i) for i in range(num_routers)]
mesh.routers = [Router(router_id=i) for i in range(num_routers)]
# link counter to set unique link ids
link_count = 0
@ -77,27 +79,27 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
cntrl_level, router_id = divmod(i, num_routers)
assert(cntrl_level < caches_per_router)
ext_links.append(ExtLink(link_id=link_count, ext_node=n,
int_node=routers[router_id]))
int_node=mesh.routers[router_id]))
link_count += 1
# Connect the dir nodes to the corners.
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0],
int_node=routers[0]))
int_node=mesh.routers[0]))
link_count += 1
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1],
int_node=routers[num_columns - 1]))
int_node=mesh.routers[num_columns - 1]))
link_count += 1
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2],
int_node=routers[num_routers - num_columns]))
int_node=mesh.routers[num_routers - num_columns]))
link_count += 1
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3],
int_node=routers[num_routers - 1]))
int_node=mesh.routers[num_routers - 1]))
link_count += 1
# Connect the dma nodes to router 0. These should only be DMA nodes.
for (i, node) in enumerate(dma_nodes):
assert(node.type == 'DMA_Controller')
ext_links.append(ExtLink(ext_node=node, int_node=routers[0]))
ext_links.append(ExtLink(ext_node=node, int_node=mesh.routers[0]))
# Create the mesh links. First row (east-west) links then column
# (north-south) links
@ -108,8 +110,8 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
east_id = col + (row * num_columns)
west_id = (col + 1) + (row * num_columns)
int_links.append(IntLink(link_id=link_count,
node_a=routers[east_id],
node_b=routers[west_id],
node_a=mesh.routers[east_id],
node_b=mesh.routers[west_id],
weight=1))
link_count += 1
@ -119,12 +121,12 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
north_id = col + (row * num_columns)
south_id = col + ((row + 1) * num_columns)
int_links.append(IntLink(link_id=link_count,
node_a=routers[north_id],
node_b=routers[south_id],
node_a=mesh.routers[north_id],
node_b=mesh.routers[south_id],
weight=2))
link_count += 1
return MeshDirCorners(ext_links=ext_links,
int_links=int_links,
routers=routers)
mesh.ext_links = ext_links
mesh.int_links = int_links
return mesh

16
src/mem/ruby/network/topologies/Pt2Pt.py
View file

@ -36,8 +36,9 @@ class Pt2Pt(Topology):
def makeTopology(nodes, options, IntLink, ExtLink, Router):
# Create an individual router for each controller, and connect all to all.
routers = [Router(router_id=i) for i in range(len(nodes))]
ext_links = [ExtLink(link_id=i, ext_node=n, int_node=routers[i])
pt2pt = Pt2Pt()
pt2pt.routers = [Router(router_id=i) for i in range(len(nodes))]
ext_links = [ExtLink(link_id=i, ext_node=n, int_node=pt2pt.routers[i])
for (i, n) in enumerate(nodes)]
link_count = len(nodes)
@ -47,9 +48,10 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
if (i != j):
link_count += 1
int_links.append(IntLink(link_id=link_count,
node_a=routers[i],
node_b=routers[j]))
node_a=pt2pt.routers[i],
node_b=pt2pt.routers[j]))
return Pt2Pt(ext_links=ext_links,
int_links=int_links,
routers=routers)
pt2pt.ext_links = ext_links
pt2pt.int_links = int_links
return pt2pt

24
src/mem/ruby/network/topologies/Torus.py
View file

@ -51,8 +51,11 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
num_columns = int(num_routers / num_rows)
assert(num_columns * num_rows == num_routers)
# Create the torus object
torus = Torus()
# Create the routers in the torus
routers = [Router(router_id=i) for i in range(num_routers)]
torus.routers = [Router(router_id=i) for i in range(num_routers)]
# link counter to set unique link ids
link_count = 0
@ -73,7 +76,7 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
cntrl_level, router_id = divmod(i, num_routers)
assert(cntrl_level < cntrls_per_router)
ext_links.append(ExtLink(link_id=link_count, ext_node=n,
int_node=routers[router_id]))
int_node=torus.routers[router_id]))
link_count += 1
# Connect the remainding nodes to router 0. These should only be
@ -82,7 +85,7 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
assert(node.type == 'DMA_Controller')
assert(i < remainder)
ext_links.append(ExtLink(link_id=link_count, ext_node=node,
int_node=routers[0]))
int_node=torus.routers[0]))
link_count += 1
# Create the torus links. First row (east-west) links then column
@ -97,8 +100,8 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
else:
east_id = (row * num_columns)
int_links.append(IntLink(link_id=link_count,
node_a=routers[east_id],
node_b=routers[west_id],
node_a=torus.routers[east_id],
node_b=torus.routers[west_id],
latency=2,
weight=1))
link_count += 1
@ -111,12 +114,13 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
else:
south_id = col
int_links.append(IntLink(link_id=link_count,
node_a=routers[north_id],
node_b=routers[south_id],
node_a=torus.routers[north_id],
node_b=torus.routers[south_id],
latency=2,
weight=2))
link_count += 1
return Torus(ext_links=ext_links,
int_links=int_links,
routers=routers)
torus.ext_links = ext_links
torus.int_links = int_links
return torus

4
tests/configs/memtest-ruby.py
View file

@ -87,9 +87,9 @@ system = System(cpu = cpus,
system.ruby = Ruby.create_system(options, system)
assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
#
# Tie the cpu test and functional ports to the ruby cpu ports and
# physmem, respectively

4
tests/configs/rubytest-ruby.py
View file

@ -79,7 +79,7 @@ system = System(tester = tester, physmem = PhysicalMemory())
system.ruby = Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
# The tester is most effective when randomization is turned on and
@ -87,7 +87,7 @@ assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
#
system.ruby.randomization = True
for ruby_port in system.ruby.cpu_ruby_ports:
for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#

6
tests/configs/simple-timing-mp-ruby.py
View file

@ -79,14 +79,14 @@ system = System(cpu = cpus, physmem = PhysicalMemory())
system.ruby = Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the ruby cpu ports
#
cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
# -----------------------
# run simulation

6
tests/configs/simple-timing-ruby.py
View file

@ -76,14 +76,14 @@ system = System(cpu = cpu, physmem = PhysicalMemory())
system.ruby = Ruby.create_system(options, system)
assert(len(system.ruby.cpu_ruby_ports) == 1)
assert(len(system.ruby._cpu_ruby_ports) == 1)
#
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
# -----------------------
# run simulation