8a652f9871
Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first.
115 lines
4.7 KiB
Python
115 lines
4.7 KiB
Python
# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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from m5.params import *
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from m5.objects import *
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class Mesh(Topology):
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description='Mesh'
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# Makes a generic mesh assuming an equal number of cache and directory cntrls
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def makeTopology(nodes, options, IntLink, ExtLink, Router):
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num_routers = options.num_cpus
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num_rows = options.mesh_rows
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# There must be an evenly divisible number of cntrls to routers
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# Also, obviously the number or rows must be <= the number of routers
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cntrls_per_router, remainder = divmod(len(nodes), num_routers)
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assert(num_rows <= num_routers)
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num_columns = int(num_routers / num_rows)
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assert(num_columns * num_rows == num_routers)
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# Create the mesh object
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mesh = Mesh()
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# Create the routers in the mesh
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mesh.routers = [Router(router_id=i) for i in range(num_routers)]
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# link counter to set unique link ids
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link_count = 0
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# Add all but the remainder nodes to the list of nodes to be uniformly
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# distributed across the network.
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network_nodes = []
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remainder_nodes = []
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for node_index in xrange(len(nodes)):
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if node_index < (len(nodes) - remainder):
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network_nodes.append(nodes[node_index])
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else:
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remainder_nodes.append(nodes[node_index])
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# Connect each node to the appropriate router
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ext_links = []
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for (i, n) in enumerate(network_nodes):
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cntrl_level, router_id = divmod(i, num_routers)
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assert(cntrl_level < cntrls_per_router)
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ext_links.append(ExtLink(link_id=link_count, ext_node=n,
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int_node=mesh.routers[router_id]))
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link_count += 1
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# Connect the remainding nodes to router 0. These should only be
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# DMA nodes.
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for (i, node) in enumerate(remainder_nodes):
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assert(node.type == 'DMA_Controller')
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assert(i < remainder)
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ext_links.append(ExtLink(link_id=link_count, ext_node=node,
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int_node=mesh.routers[0]))
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link_count += 1
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# Create the mesh links. First row (east-west) links then column
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# (north-south) links
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int_links = []
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for row in xrange(num_rows):
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for col in xrange(num_columns):
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if (col + 1 < num_columns):
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east_id = col + (row * num_columns)
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west_id = (col + 1) + (row * num_columns)
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int_links.append(IntLink(link_id=link_count,
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node_a=mesh.routers[east_id],
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node_b=mesh.routers[west_id],
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weight=1))
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link_count += 1
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for col in xrange(num_columns):
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for row in xrange(num_rows):
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if (row + 1 < num_rows):
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north_id = col + (row * num_columns)
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south_id = col + ((row + 1) * num_columns)
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int_links.append(IntLink(link_id=link_count,
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node_a=mesh.routers[north_id],
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node_b=mesh.routers[south_id],
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weight=2))
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link_count += 1
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mesh.int_links = int_links
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mesh.ext_links = ext_links
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return mesh
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