mem: add local var in Cache::recvTimingResp()
The main loop in recvTimingResp() uses target->pkt all over the place. Create a local tgt_pkt to help keep lines under the line length limit.
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parent
ee0b52404c
commit
89bb03a1a6
57
src/mem/cache/cache_impl.hh
vendored
57
src/mem/cache/cache_impl.hh
vendored
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@ -1136,6 +1136,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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while (mshr->hasTargets()) {
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MSHR::Target *target = mshr->getTarget();
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Packet *tgt_pkt = target->pkt;
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switch (target->source) {
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case MSHR::Target::FromCPU:
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@ -1145,12 +1146,12 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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completion_time = pkt->headerDelay;
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// Software prefetch handling for cache closest to core
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if (target->pkt->cmd.isSWPrefetch() && isTopLevel) {
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if (tgt_pkt->cmd.isSWPrefetch() && isTopLevel) {
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// a software prefetch would have already been ack'd immediately
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// with dummy data so the core would be able to retire it.
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// this request completes right here, so we deallocate it.
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delete target->pkt->req;
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delete target->pkt;
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delete tgt_pkt->req;
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delete tgt_pkt;
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break; // skip response
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}
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@ -1160,24 +1161,24 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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// cannot actually be determined until examining the stored MSHR
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// state. We "catch up" with that logic here, which is duplicated
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// from above.
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if (target->pkt->isWriteInvalidate() && isTopLevel) {
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if (tgt_pkt->isWriteInvalidate() && isTopLevel) {
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assert(!is_error);
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// NB: we use the original packet here and not the response!
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mshr->handleFill(target->pkt, blk);
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blk = handleFill(target->pkt, blk, writebacks);
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mshr->handleFill(tgt_pkt, blk);
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blk = handleFill(tgt_pkt, blk, writebacks);
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assert(blk != NULL);
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is_fill = true;
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}
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if (is_fill) {
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satisfyCpuSideRequest(target->pkt, blk,
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satisfyCpuSideRequest(tgt_pkt, blk,
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true, mshr->hasPostDowngrade());
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// How many bytes past the first request is this one
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int transfer_offset =
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target->pkt->getOffset(blkSize) - initial_offset;
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tgt_pkt->getOffset(blkSize) - initial_offset;
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if (transfer_offset < 0) {
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transfer_offset += blkSize;
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}
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@ -1189,22 +1190,22 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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completion_time += clockEdge(responseLatency) +
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(transfer_offset ? pkt->payloadDelay : 0);
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assert(!target->pkt->req->isUncacheable());
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assert(!tgt_pkt->req->isUncacheable());
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assert(target->pkt->req->masterId() < system->maxMasters());
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missLatency[target->pkt->cmdToIndex()][target->pkt->req->masterId()] +=
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assert(tgt_pkt->req->masterId() < system->maxMasters());
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missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
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completion_time - target->recvTime;
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} else if (pkt->cmd == MemCmd::UpgradeFailResp) {
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// failed StoreCond upgrade
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assert(target->pkt->cmd == MemCmd::StoreCondReq ||
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target->pkt->cmd == MemCmd::StoreCondFailReq ||
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target->pkt->cmd == MemCmd::SCUpgradeFailReq);
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assert(tgt_pkt->cmd == MemCmd::StoreCondReq ||
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tgt_pkt->cmd == MemCmd::StoreCondFailReq ||
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tgt_pkt->cmd == MemCmd::SCUpgradeFailReq);
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// responseLatency is the latency of the return path
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// from lower level caches/memory to an upper level cache or
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// the core.
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completion_time += clockEdge(responseLatency) +
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pkt->payloadDelay;
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target->pkt->req->setExtraData(0);
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tgt_pkt->req->setExtraData(0);
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} else {
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// not a cache fill, just forwarding response
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// responseLatency is the latency of the return path
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@ -1212,34 +1213,33 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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completion_time += clockEdge(responseLatency) +
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pkt->payloadDelay;
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if (pkt->isRead() && !is_error) {
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target->pkt->setData(pkt->getConstPtr<uint8_t>());
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tgt_pkt->setData(pkt->getConstPtr<uint8_t>());
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}
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}
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target->pkt->makeTimingResponse();
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tgt_pkt->makeTimingResponse();
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// if this packet is an error copy that to the new packet
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if (is_error)
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target->pkt->copyError(pkt);
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if (target->pkt->cmd == MemCmd::ReadResp &&
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tgt_pkt->copyError(pkt);
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if (tgt_pkt->cmd == MemCmd::ReadResp &&
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(pkt->isInvalidate() || mshr->hasPostInvalidate())) {
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// If intermediate cache got ReadRespWithInvalidate,
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// propagate that. Response should not have
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// isInvalidate() set otherwise.
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target->pkt->cmd = MemCmd::ReadRespWithInvalidate;
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tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate;
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DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n",
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__func__, target->pkt->cmdString(),
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target->pkt->getAddr());
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__func__, tgt_pkt->cmdString(), tgt_pkt->getAddr());
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}
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// Reset the bus additional time as it is now accounted for
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target->pkt->headerDelay = target->pkt->payloadDelay = 0;
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cpuSidePort->schedTimingResp(target->pkt, completion_time);
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tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
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cpuSidePort->schedTimingResp(tgt_pkt, completion_time);
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break;
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case MSHR::Target::FromPrefetcher:
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assert(target->pkt->cmd == MemCmd::HardPFReq);
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assert(tgt_pkt->cmd == MemCmd::HardPFReq);
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if (blk)
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blk->status |= BlkHWPrefetched;
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delete target->pkt->req;
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delete target->pkt;
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delete tgt_pkt->req;
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delete tgt_pkt;
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break;
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case MSHR::Target::FromSnoop:
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@ -1248,8 +1248,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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// response to snoop request
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DPRINTF(Cache, "processing deferred snoop...\n");
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assert(!(pkt->isInvalidate() && !mshr->hasPostInvalidate()));
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handleSnoop(target->pkt, blk, true, true,
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mshr->hasPostInvalidate());
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handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate());
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break;
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default:
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