mem: restructure Packet cmd initialization a bit more
Refactor the way that specific MemCmd values are generated for packets. The new approach is a little more elegant in that we assign the right value up front, and it's also more amenable to non-heap-allocated Packet objects. Also replaced the code in the Minor model that was still doing it the ad-hoc way. This is basically a refinement of http://repo.gem5.org/gem5/rev/711eb0e64249.
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@ -811,10 +811,17 @@ CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req)
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void
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CacheUnit::buildDataPacket(CacheRequest *cache_req)
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{
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cache_req->dataPkt = new CacheReqPacket(cache_req,
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cache_req->pktCmd,
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MemCmd cmd;
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if (cache_req->pktCmd == MemCmd::ReadReq) {
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cmd = Packet::makeReadCmd(cache_req->memReq);
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} else {
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assert(cache_req->pktCmd == MemCmd::WriteReq);
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cmd = Packet::makeWriteCmd(cache_req->memReq);
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}
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cache_req->dataPkt = new CacheReqPacket(cache_req, cmd,
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cache_req->instIdx);
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cache_req->dataPkt->refineCommand(); // handle LL/SC, etc.
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DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
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cache_req->getSlot(),
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@ -230,7 +230,7 @@ class CacheRequest : public ResourceRequest
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bool isMemAccPending() { return memAccPending; }
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//Make this data private/protected!
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MemCmd::Command pktCmd;
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MemCmd pktCmd;
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RequestPtr memReq;
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PacketDataPtr reqData;
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CacheReqPacket *dataPkt;
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@ -252,7 +252,7 @@ class CacheReqPacket : public Packet
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{
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public:
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CacheReqPacket(CacheRequest *_req,
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Command _cmd, int _idx = 0)
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MemCmd _cmd, int _idx = 0)
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: Packet(&(*_req->memReq), _cmd), cacheReq(_req),
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instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
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{
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@ -1545,18 +1545,8 @@ PacketPtr
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makePacketForRequest(Request &request, bool isLoad,
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Packet::SenderState *sender_state, PacketDataPtr data)
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{
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MemCmd command;
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/* Make a ret with the right command type to match the request */
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if (request.isLLSC()) {
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command = (isLoad ? MemCmd::LoadLockedReq : MemCmd::StoreCondReq);
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} else if (request.isSwap()) {
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command = MemCmd::SwapReq;
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} else {
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command = (isLoad ? MemCmd::ReadReq : MemCmd::WriteReq);
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}
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PacketPtr ret = new Packet(&request, command);
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PacketPtr ret = isLoad ? Packet::createRead(&request)
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: Packet::createWrite(&request);
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if (sender_state)
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ret->pushSenderState(sender_state);
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@ -341,8 +341,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
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// Now do the access.
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if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
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Packet pkt(req, MemCmd::ReadReq);
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pkt.refineCommand();
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Packet pkt(req, Packet::makeReadCmd(req));
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pkt.dataStatic(data);
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if (req->isMmappedIpr())
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@ -643,45 +643,47 @@ class Packet : public Printable
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}
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/**
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* Change the packet type based on request type.
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* Generate the appropriate read MemCmd based on the Request flags.
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*/
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void
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refineCommand()
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static MemCmd
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makeReadCmd(const RequestPtr req)
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{
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if (cmd == MemCmd::ReadReq) {
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if (req->isLLSC()) {
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cmd = MemCmd::LoadLockedReq;
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} else if (req->isPrefetch()) {
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cmd = MemCmd::SoftPFReq;
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}
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} else if (cmd == MemCmd::WriteReq) {
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if (req->isLLSC()) {
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cmd = MemCmd::StoreCondReq;
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} else if (req->isSwap()) {
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cmd = MemCmd::SwapReq;
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}
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}
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if (req->isLLSC())
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return MemCmd::LoadLockedReq;
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else if (req->isPrefetch())
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return MemCmd::SoftPFReq;
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else
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return MemCmd::ReadReq;
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}
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/**
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* Generate the appropriate write MemCmd based on the Request flags.
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*/
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static MemCmd
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makeWriteCmd(const RequestPtr req)
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{
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if (req->isLLSC())
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return MemCmd::StoreCondReq;
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else if (req->isSwap())
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return MemCmd::SwapReq;
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else
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return MemCmd::WriteReq;
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}
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/**
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* Constructor-like methods that return Packets based on Request objects.
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* Will call refineCommand() to fine-tune the Packet type if it's not a
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* vanilla read or write.
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* Fine-tune the MemCmd type if it's not a vanilla read or write.
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*/
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static PacketPtr
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createRead(const RequestPtr req)
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{
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PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
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pkt->refineCommand();
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return pkt;
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return new Packet(req, makeReadCmd(req));
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}
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static PacketPtr
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createWrite(const RequestPtr req)
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{
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PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
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pkt->refineCommand();
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return pkt;
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return new Packet(req, makeWriteCmd(req));
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}
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/**
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