config: fixed ruby dma device connections

This commit is contained in:
Brad Beckmann 2010-08-24 13:20:31 -07:00
parent e983ef9e8c
commit 8572d8fd91
5 changed files with 10 additions and 12 deletions

View file

@ -124,9 +124,10 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
self.tsunami.ethernet.pio = self.piobus.port self.tsunami.ethernet.pio = self.piobus.port
# #
# store the dma devices for later connection to dma ruby ports # Store the dma devices for later connection to dma ruby ports.
# Append an underscore to dma_devices to avoid the SimObjectVector check.
# #
self.dma_devices = [self.tsunami.ide, self.tsunami.ethernet] self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True)) read_only = True))

View file

@ -115,7 +115,7 @@ system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
system.ruby = Ruby.create_system(options, system.ruby = Ruby.create_system(options,
system, system,
system.piobus, system.piobus,
system.dma_devices) system._dma_devices)
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]

View file

@ -151,12 +151,11 @@ def create_system(options, system, piobus, dma_devices):
dma_cntrl = DMA_Controller(version = i, dma_cntrl = DMA_Controller(version = i,
dma_sequencer = dma_seq) dma_sequencer = dma_seq)
dma_cntrl.dma_sequencer.port = dma_device.dma
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':
system.dma_cntrl.dma_sequencer.port = dma_device.test exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
else: else:
system.dma_cntrl.dma_sequencer.port = dma_device.dma exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl) dma_cntrl_nodes.append(dma_cntrl)
all_cntrls = l1_cntrl_nodes + \ all_cntrls = l1_cntrl_nodes + \

View file

@ -152,10 +152,9 @@ def create_system(options, system, piobus, dma_devices):
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':
system.dma_cntrl.dma_sequencer.port = dma_device.test exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
else: else:
system.dma_cntrl.dma_sequencer.port = dma_device.dma exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl.dma_sequencer.port = dma_device.dma
dma_cntrl_nodes.append(dma_cntrl) dma_cntrl_nodes.append(dma_cntrl)
all_cntrls = l1_cntrl_nodes + \ all_cntrls = l1_cntrl_nodes + \

View file

@ -178,10 +178,9 @@ def create_system(options, system, piobus, dma_devices):
exec("system.dma_cntrl%d = dma_cntrl" % i) exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest': if dma_device.type == 'MemTest':
system.dma_cntrl.dma_sequencer.port = dma_device.test exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
else: else:
system.dma_cntrl.dma_sequencer.port = dma_device.dma exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl.dma_sequencer.port = dma_device.dma
dma_cntrl_nodes.append(dma_cntrl) dma_cntrl_nodes.append(dma_cntrl)
all_cntrls = l1_cntrl_nodes + \ all_cntrls = l1_cntrl_nodes + \