O3CPU fixes.
src/cpu/o3/lsq_unit.hh: LSQ needs to decrement the WB counter if the load is going to be replayed. src/cpu/o3/lsq_unit_impl.hh: LSQ needs to decrement the WB counter if the load is squashed. --HG-- extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
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@ -601,6 +601,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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// Tell IQ/mem dep unit that this instruction will need to be
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// rescheduled eventually
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iewStage->rescheduleMemInst(load_inst);
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iewStage->decrWb(load_inst->seqNum);
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++lsqRescheduledLoads;
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// Do not generate a writeback event as this instruction is not
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@ -790,6 +790,7 @@ LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
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// Squashed instructions do not need to complete their access.
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if (inst->isSquashed()) {
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iewStage->decrWb(inst->seqNum);
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assert(!inst->isStore());
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++lsqIgnoredResponses;
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return;
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