From 85515c4976532e0057a56a16cd53367bb6d0bbdb Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Wed, 19 Jul 2006 15:28:02 -0400
Subject: [PATCH] O3CPU fixes.

src/cpu/o3/lsq_unit.hh:
    LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
    LSQ needs to decrement the WB counter if the load is squashed.

--HG--
extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
---
 src/cpu/o3/lsq_unit.hh      | 1 +
 src/cpu/o3/lsq_unit_impl.hh | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a76a73f0c..512b5a63c 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -601,6 +601,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             // Tell IQ/mem dep unit that this instruction will need to be
             // rescheduled eventually
             iewStage->rescheduleMemInst(load_inst);
+            iewStage->decrWb(load_inst->seqNum);
             ++lsqRescheduledLoads;
 
             // Do not generate a writeback event as this instruction is not
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 85b150cd9..4f5dbbf1c 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -790,6 +790,7 @@ LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
 
     // Squashed instructions do not need to complete their access.
     if (inst->isSquashed()) {
+        iewStage->decrWb(inst->seqNum);
         assert(!inst->isStore());
         ++lsqIgnoredResponses;
         return;