stats: Update stats to reflect cache changes
This commit is contained in:
Andreas Hansson
parent
2847d5f517
commit
80cd107e51
91 changed files with 25542 additions and 24820 deletions
File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 1.904438 # Nu
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sim_ticks 1904437574000 # Number of ticks simulated
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sim_ticks 1904437574000 # Number of ticks simulated
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final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 143053 # Simulator instruction rate (inst/s)
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host_inst_rate 149880 # Simulator instruction rate (inst/s)
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host_op_rate 143053 # Simulator op (including micro ops) rate (op/s)
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host_op_rate 149880 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4814720142 # Simulator tick rate (ticks/s)
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host_tick_rate 5044505517 # Simulator tick rate (ticks/s)
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host_mem_usage 313028 # Number of bytes of host memory used
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host_mem_usage 380636 # Number of bytes of host memory used
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host_seconds 395.54 # Real time elapsed on the host
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host_seconds 377.53 # Real time elapsed on the host
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sim_insts 56583768 # Number of instructions simulated
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sim_insts 56583768 # Number of instructions simulated
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sim_ops 56583768 # Number of ops (including micro ops) simulated
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sim_ops 56583768 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -780,6 +780,12 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444
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system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses
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system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable
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system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7039 # number of ReadReq MSHR uncacheable
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system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable
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system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10032 # number of WriteReq MSHR uncacheable
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system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17071 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles
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@ -822,12 +828,12 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557
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system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610 # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610 # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187 # average WriteReq mshr uncacheable latency
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187 # average WriteReq mshr uncacheable latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955 # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955 # average overall mshr uncacheable latency
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.tags.replacements 911417 # number of replacements
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system.cpu0.icache.tags.replacements 911417 # number of replacements
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system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use
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system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use
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@ -1377,6 +1383,12 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358
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system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses
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system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses
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system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses
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system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses
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system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses
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system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses
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system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable
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system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable
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system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable
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system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2893 # number of WriteReq MSHR uncacheable
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system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses
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system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3051 # number of overall MSHR uncacheable misses
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system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles
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system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles
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system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles
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system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles
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system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles
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system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles
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@ -1419,12 +1431,12 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913
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system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
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system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
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system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency
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system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency
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system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
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system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392 # average ReadReq mshr uncacheable latency
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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392 # average ReadReq mshr uncacheable latency
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system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160 # average WriteReq mshr uncacheable latency
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system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160 # average WriteReq mshr uncacheable latency
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system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
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system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136 # average overall mshr uncacheable latency
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system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136 # average overall mshr uncacheable latency
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system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.icache.tags.replacements 211356 # number of replacements
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system.cpu1.icache.tags.replacements 211356 # number of replacements
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system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use
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system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use
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@ -1914,6 +1926,15 @@ system.l2c.overall_mshr_misses::cpu0.data 385876 # n
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system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses
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system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable
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system.l2c.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable
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system.l2c.ReadReq_mshr_uncacheable::total 7197 # number of ReadReq MSHR uncacheable
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system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable
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system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable
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system.l2c.WriteReq_mshr_uncacheable::total 12925 # number of WriteReq MSHR uncacheable
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system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses
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system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses
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system.l2c.overall_mshr_uncacheable_misses::total 20122 # number of overall MSHR uncacheable misses
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system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles
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@ -1995,15 +2016,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113
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system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194007.671544 # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171632.911392 # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193516.465194 # average ReadReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 199279.057018 # average WriteReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204473.902523 # average WriteReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 200441.818182 # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 197105.471267 # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 202773.189118 # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::total 197964.839479 # average overall mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.membus.trans_dist::ReadReq 296650 # Transaction distribution
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system.membus.trans_dist::ReadReq 296650 # Transaction distribution
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system.membus.trans_dist::ReadResp 296572 # Transaction distribution
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system.membus.trans_dist::ReadResp 296572 # Transaction distribution
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@ -2032,17 +2053,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568
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system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 10437 # Total snoops (count)
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system.membus.snoops 10437 # Total snoops (count)
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system.membus.snoop_fanout::samples 594010 # Request fanout histogram
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system.membus.snoop_fanout::samples 614132 # Request fanout histogram
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::1 614132 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 1 # Request fanout histogram
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system.membus.snoop_fanout::min_value 1 # Request fanout histogram
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system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.snoop_fanout::total 594010 # Request fanout histogram
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system.membus.snoop_fanout::total 614132 # Request fanout histogram
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system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks)
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system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks)
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system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks)
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@ -2076,19 +2097,19 @@ system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 135
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system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.snoops 72565 # Total snoops (count)
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system.toL2Bus.snoops 72565 # Total snoops (count)
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system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram
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system.toL2Bus.snoop_fanout::samples 3425693 # Request fanout histogram
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system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram
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system.toL2Bus.snoop_fanout::mean 3.012192 # Request fanout histogram
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system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.109741 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::3 3383928 98.78% 98.78% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::4 41765 1.22% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3425693 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.861006 # Nu
|
||||||
sim_ticks 1861005569500 # Number of ticks simulated
|
sim_ticks 1861005569500 # Number of ticks simulated
|
||||||
final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 145313 # Simulator instruction rate (inst/s)
|
host_inst_rate 152837 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 145313 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 152837 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 5108711594 # Simulator tick rate (ticks/s)
|
host_tick_rate 5373256396 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 309496 # Number of bytes of host memory used
|
host_mem_usage 376300 # Number of bytes of host memory used
|
||||||
host_seconds 364.28 # Real time elapsed on the host
|
host_seconds 346.35 # Real time elapsed on the host
|
||||||
sim_insts 52934565 # Number of instructions simulated
|
sim_insts 52934565 # Number of instructions simulated
|
||||||
sim_ops 52934565 # Number of ops (including micro ops) simulated
|
sim_ops 52934565 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -51,7 +51,7 @@ system.physmem.bytesReadSys 25845824 # To
|
||||||
system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 25748 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 25748 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::1 25559 # Per bank write bursts
|
system.physmem.perBankRdBursts::1 25559 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::2 25508 # Per bank write bursts
|
system.physmem.perBankRdBursts::2 25508 # Per bank write bursts
|
||||||
|
|
@ -261,8 +261,8 @@ system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Wr
|
||||||
system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads
|
||||||
system.physmem.totQLat 3741903500 # Total ticks spent queuing
|
system.physmem.totQLat 3741904500 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
|
|
@ -399,15 +399,15 @@ system.cpu.decode.DecodedInsts 68295720 # Nu
|
||||||
system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode
|
system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode
|
||||||
system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full
|
system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full
|
||||||
system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full
|
system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full
|
||||||
system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups
|
||||||
|
|
@ -416,11 +416,11 @@ system.cpu.rename.CommittedMaps 38142428 # Nu
|
||||||
system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing
|
system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing
|
||||||
system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed
|
system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed
|
||||||
system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed
|
system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed
|
||||||
system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer
|
system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer
|
||||||
system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit.
|
system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit.
|
||||||
system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads.
|
system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads.
|
||||||
system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued
|
||||||
|
|
@ -432,13 +432,13 @@ system.cpu.iq.issued_per_cycle::samples 117014009 # Nu
|
||||||
system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
|
|
@ -476,7 +476,7 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # at
|
||||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||||
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
|
||||||
|
|
@ -515,15 +515,15 @@ system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Ty
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued
|
||||||
system.cpu.iq.rate 0.469435 # Inst issue rate
|
system.cpu.iq.rate 0.469435 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
|
|
@ -534,18 +534,18 @@ system.cpu.iew.lsq.thread0.squashedStores 587155 # N
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing
|
||||||
system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking
|
system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking
|
||||||
system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking
|
system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking
|
||||||
system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ
|
system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ
|
||||||
system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch
|
system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch
|
||||||
system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions
|
system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions
|
||||||
system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions
|
system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions
|
||||||
system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions
|
system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions
|
||||||
system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall
|
system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall
|
system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations
|
system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations
|
||||||
system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly
|
||||||
|
|
@ -576,13 +576,13 @@ system.cpu.commit.committed_per_cycle::stdev 1.428292
|
||||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
|
|
@ -632,8 +632,8 @@ system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Cl
|
||||||
system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction
|
system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction
|
||||||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||||
system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
|
system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
|
||||||
system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
|
system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached
|
||||||
system.cpu.rob.rob_reads 177593269 # The number of ROB reads
|
system.cpu.rob.rob_reads 177593268 # The number of ROB reads
|
||||||
system.cpu.rob.rob_writes 130137832 # The number of ROB writes
|
system.cpu.rob.rob_writes 130137832 # The number of ROB writes
|
||||||
system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
|
|
@ -692,16 +692,16 @@ system.cpu.dcache.overall_misses::cpu.data 3751566 #
|
||||||
system.cpu.dcache.overall_misses::total 3751566 # number of overall misses
|
system.cpu.dcache.overall_misses::total 3751566 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles
|
system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses)
|
||||||
|
|
@ -728,21 +728,21 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.246685
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked
|
system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked
|
||||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||||
|
|
@ -770,18 +770,24 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1386351
|
||||||
system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles
|
||||||
|
|
@ -802,22 +808,22 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 1032757 # number of replacements
|
system.cpu.icache.tags.replacements 1032757 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use
|
||||||
|
|
@ -941,14 +947,14 @@ system.cpu.l2cache.UpgradeReq_hits::cpu.data 31
|
||||||
system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits
|
||||||
system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits
|
system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 186337 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 186339 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::total 186337 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.data 1015065 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.data 1015063 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.demand_hits::total 2033290 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::total 2033288 # number of demand (read+write) hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::cpu.data 1015065 # number of overall hits
|
system.cpu.l2cache.overall_hits::cpu.data 1015063 # number of overall hits
|
||||||
system.cpu.l2cache.overall_hits::total 2033290 # number of overall hits
|
system.cpu.l2cache.overall_hits::total 2033288 # number of overall hits
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses
|
||||||
|
|
@ -956,14 +962,14 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 48
|
||||||
system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
|
||||||
system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
|
system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 115274 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 115276 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 115274 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::total 115276 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.data 389205 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.data 389207 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.demand_misses::total 404332 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::total 404334 # number of demand (read+write) misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::cpu.data 389205 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.data 389207 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::total 404332 # number of overall misses
|
system.cpu.l2cache.overall_misses::total 404334 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles
|
||||||
|
|
@ -971,14 +977,14 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271399612 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10271399612 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.data 30291411612 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::total 31556248611 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.data 30291411612 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::total 31556248611 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses)
|
||||||
|
|
@ -1003,14 +1009,14 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382198 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.382198 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277160 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::total 0.165872 # miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277160 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::total 0.165872 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency
|
||||||
|
|
@ -1018,14 +1024,14 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89102.671953 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89102.671953 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::total 78045.003910 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.537544 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::total 78045.003910 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -1049,14 +1055,20 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115276 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 115276 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 389207 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses::total 404333 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 389207 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 404333 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1064,14 +1076,14 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861643888 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861643888 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469539888 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::total 26545366637 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469539888 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::total 26545366637 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles
|
||||||
|
|
@ -1085,14 +1097,14 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382198 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382198 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.165872 # mshr miss rate for demand accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277160 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.165872 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency
|
||||||
|
|
@ -1100,20 +1112,20 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76873.277074 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76873.277074 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.572998 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.238717 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192884.054834 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192884.054834 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196642.961342 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196642.961342 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195066.799782 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195066.799782 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution
|
||||||
|
|
@ -1134,24 +1146,24 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 42097 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 42097 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||||
|
|
@ -1336,19 +1348,19 @@ system.membus.trans_dist::WriteResp 9597 # Tr
|
||||||
system.membus.trans_dist::Writeback 117457 # Transaction distribution
|
system.membus.trans_dist::Writeback 117457 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
|
system.membus.trans_dist::UpgradeReq 187 # Transaction distribution
|
||||||
system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution
|
system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeResp 190 # Transaction distribution
|
system.membus.trans_dist::UpgradeResp 192 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExReq 115137 # Transaction distribution
|
system.membus.trans_dist::ReadExReq 115137 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExResp 115137 # Transaction distribution
|
system.membus.trans_dist::ReadExResp 115137 # Transaction distribution
|
||||||
system.membus.trans_dist::BadAddressError 94 # Transaction distribution
|
system.membus.trans_dist::BadAddressError 94 # Transaction distribution
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
|
@ -1356,24 +1368,24 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 435 # Total snoops (count)
|
system.membus.snoops 435 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 563651 # Request fanout histogram
|
system.membus.snoop_fanout::samples 580180 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 563651 # Request fanout histogram
|
system.membus.snoop_fanout::total 580180 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
||||||
system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks)
|
system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks)
|
system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||||
system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks)
|
system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.841539 # Nu
|
||||||
sim_ticks 1841538755500 # Number of ticks simulated
|
sim_ticks 1841538755500 # Number of ticks simulated
|
||||||
final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 221247 # Simulator instruction rate (inst/s)
|
host_inst_rate 221997 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 221247 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 221997 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 5777125497 # Simulator tick rate (ticks/s)
|
host_tick_rate 5796715531 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 308008 # Number of bytes of host memory used
|
host_mem_usage 374488 # Number of bytes of host memory used
|
||||||
host_seconds 318.76 # Real time elapsed on the host
|
host_seconds 317.69 # Real time elapsed on the host
|
||||||
sim_insts 70525499 # Number of instructions simulated
|
sim_insts 70525499 # Number of instructions simulated
|
||||||
sim_ops 70525499 # Number of ops (including micro ops) simulated
|
sim_ops 70525499 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -681,6 +681,15 @@ system.cpu0.dcache.demand_mshr_misses::total 506836
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 140963 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 140963 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu2.data 365873 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 365873 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 506836 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 506836 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1102 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2114965000 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2114965000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4270329509 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4270329509 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6385294509 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6385294509 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -741,15 +750,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201881.578947 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 211980.806142 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207804.690432 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 212719.971056 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 209384.795870 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 210696.840307 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 207911.634461 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 210483.216026 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 209449.255422 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 964809 # number of replacements
|
system.cpu0.icache.tags.replacements 964809 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 510.919385 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 510.919385 # Cycle average of tags in use
|
||||||
|
|
@ -1734,6 +1743,15 @@ system.l2c.overall_mshr_misses::cpu1.data 33612 # n
|
||||||
system.l2c.overall_mshr_misses::cpu2.inst 4814 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.inst 4814 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu2.data 41256 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.data 41256 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 81979 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 81979 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1102 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 158665250 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 158665250 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 968947500 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 968947500 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 340372000 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 340372000 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1809,15 +1827,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187881.578947 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197980.806142 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193804.690432 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 199719.971056 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196384.795870 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 197696.840307 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 194467.995169 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 197060.097455 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 196017.886047 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 295002 # Transaction distribution
|
system.membus.trans_dist::ReadReq 295002 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 294996 # Transaction distribution
|
system.membus.trans_dist::ReadResp 294996 # Transaction distribution
|
||||||
|
|
@ -1846,17 +1864,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 157 # Total snoops (count)
|
system.membus.snoops 157 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 562136 # Request fanout histogram
|
system.membus.snoop_fanout::samples 579090 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 562136 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 579090 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 562136 # Request fanout histogram
|
system.membus.snoop_fanout::total 579090 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks)
|
||||||
|
|
@ -1886,17 +1904,17 @@ system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 617
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 41934 # Total snoops (count)
|
system.toL2Bus.snoops 41934 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 3236737 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 3253691 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 1.012895 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.012828 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.112822 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.112532 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 3194999 98.71% 98.71% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 3211953 98.72% 98.72% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 41738 1.29% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 41738 1.28% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3236737 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3253691 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.827616 # Nu
|
||||||
sim_ticks 2827616186000 # Number of ticks simulated
|
sim_ticks 2827616186000 # Number of ticks simulated
|
||||||
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 73888 # Simulator instruction rate (inst/s)
|
host_inst_rate 70271 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 89625 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 85238 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1846444734 # Simulator tick rate (ticks/s)
|
host_tick_rate 1756065639 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 556020 # Number of bytes of host memory used
|
host_mem_usage 621588 # Number of bytes of host memory used
|
||||||
host_seconds 1531.38 # Real time elapsed on the host
|
host_seconds 1610.20 # Real time elapsed on the host
|
||||||
sim_insts 113151083 # Number of instructions simulated
|
sim_insts 113151083 # Number of instructions simulated
|
||||||
sim_ops 137250963 # Number of ops (including micro ops) simulated
|
sim_ops 137250963 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -16,9 +16,9 @@ system.clk_domain.clock 1000 # Cl
|
||||||
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
|
system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
|
||||||
|
|
@ -27,18 +27,18 @@ system.physmem.bytes_written::total 8405108 # Nu
|
||||||
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
|
system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
|
system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
|
||||||
|
|
@ -48,19 +48,19 @@ system.physmem.bw_total::writebacks 2966309 # To
|
||||||
system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 176173 # Number of read requests accepted
|
system.physmem.readReqs 176174 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 171661 # Number of write requests accepted
|
system.physmem.writeReqs 171661 # Number of write requests accepted
|
||||||
system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
|
||||||
|
|
@ -100,7 +100,7 @@ system.physmem.numWrRetry 58 # Nu
|
||||||
system.physmem.totGap 2827615975000 # Total gap between requests
|
system.physmem.totGap 2827615975000 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 541 # Read request sizes (log2)
|
system.physmem.readPktSize::2 542 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 14 # Read request sizes (log2)
|
system.physmem.readPktSize::3 14 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 2994 # Read request sizes (log2)
|
system.physmem.readPktSize::4 2994 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
|
|
@ -265,12 +265,12 @@ system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Wr
|
||||||
system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
|
||||||
system.physmem.totQLat 2104910750 # Total ticks spent queuing
|
system.physmem.totQLat 2104913750 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
|
||||||
|
|
@ -285,35 +285,35 @@ system.physmem.readRowHits 145058 # Nu
|
||||||
system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 8129210.99 # Average gap between requests
|
system.physmem.avgGap 8129187.62 # Average gap between requests
|
||||||
system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
|
||||||
system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
|
system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
|
system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
|
system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
|
||||||
system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
|
system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
|
||||||
system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ)
|
system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ)
|
||||||
system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ)
|
system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ)
|
system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ)
|
||||||
system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
|
system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
|
||||||
system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states
|
system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
|
system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states
|
system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
|
system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
|
system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
|
system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
|
||||||
system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
|
system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
|
||||||
system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ)
|
system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ)
|
||||||
system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ)
|
system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ)
|
system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ)
|
||||||
system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
|
system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
|
||||||
system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states
|
system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
|
system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states
|
system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
|
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
|
||||||
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
|
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
|
||||||
|
|
@ -570,7 +570,7 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962
|
||||||
system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
|
system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 25461870 # DTB read hits
|
system.cpu.dtb.read_hits 25461869 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 62291 # DTB read misses
|
system.cpu.dtb.read_misses 62291 # DTB read misses
|
||||||
system.cpu.dtb.write_hits 19915387 # DTB write hits
|
system.cpu.dtb.write_hits 19915387 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 10080 # DTB write misses
|
system.cpu.dtb.write_misses 10080 # DTB write misses
|
||||||
|
|
@ -583,12 +583,12 @@ system.cpu.dtb.align_faults 348 # Nu
|
||||||
system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
|
system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
|
||||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||||
system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
|
system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
|
||||||
system.cpu.dtb.read_accesses 25524161 # DTB read accesses
|
system.cpu.dtb.read_accesses 25524160 # DTB read accesses
|
||||||
system.cpu.dtb.write_accesses 19925467 # DTB write accesses
|
system.cpu.dtb.write_accesses 19925467 # DTB write accesses
|
||||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||||
system.cpu.dtb.hits 45377257 # DTB hits
|
system.cpu.dtb.hits 45377256 # DTB hits
|
||||||
system.cpu.dtb.misses 72371 # DTB misses
|
system.cpu.dtb.misses 72371 # DTB misses
|
||||||
system.cpu.dtb.accesses 45449628 # DTB accesses
|
system.cpu.dtb.accesses 45449627 # DTB accesses
|
||||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||||
|
|
@ -730,15 +730,15 @@ system.cpu.decode.SquashedInsts 3690202 # Nu
|
||||||
system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
|
||||||
system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
|
system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
|
system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
|
||||||
system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full
|
system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full
|
||||||
system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
|
||||||
|
|
@ -754,7 +754,7 @@ system.cpu.memDep0.conflictingLoads 1687720 # Nu
|
||||||
system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
|
|
@ -763,8 +763,8 @@ system.cpu.iq.issued_per_cycle::samples 256876545 # Nu
|
||||||
system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
|
||||||
|
|
@ -840,21 +840,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued
|
||||||
system.cpu.iq.rate 0.544758 # Inst issue rate
|
system.cpu.iq.rate 0.544758 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
|
|
@ -864,7 +864,7 @@ system.cpu.iew.lsq.thread0.memOrderViolation 18357
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
|
||||||
|
|
@ -881,16 +881,16 @@ system.cpu.iew.memOrderViolationEvents 18357 # Nu
|
||||||
system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 201053 # number of nop insts executed
|
system.cpu.iew.exec_nop 201053 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 26530134 # Number of branches executed
|
system.cpu.iew.exec_branches 26530134 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 20877849 # Number of stores executed
|
system.cpu.iew.exec_stores 20877849 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 0.541163 # Inst execution rate
|
system.cpu.iew.exec_rate 0.541163 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 63271750 # num instructions producing a value
|
system.cpu.iew.wb_producers 63271750 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
|
||||||
|
|
@ -975,13 +975,13 @@ system.cpu.cpi 2.325250 # CP
|
||||||
system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
|
system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 155826637 # number of integer regfile reads
|
system.cpu.int_regfile_reads 155826636 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 88633022 # number of integer regfile writes
|
system.cpu.int_regfile_writes 88633022 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 9606 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 9606 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
|
||||||
system.cpu.cc_regfile_reads 502981884 # number of cc regfile reads
|
system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads
|
||||||
system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
|
system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
|
||||||
system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
|
||||||
system.cpu.dcache.tags.replacements 839617 # number of replacements
|
system.cpu.dcache.tags.replacements 839617 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use
|
||||||
|
|
@ -1029,16 +1029,16 @@ system.cpu.dcache.overall_misses::cpu.data 4478306 #
|
||||||
system.cpu.dcache.overall_misses::total 4478306 # number of overall misses
|
system.cpu.dcache.overall_misses::total 4478306 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
|
system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses)
|
||||||
|
|
@ -1069,16 +1069,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.102475
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked
|
||||||
|
|
@ -1113,26 +1113,32 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 714916
|
||||||
system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles
|
||||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses
|
||||||
|
|
@ -1149,24 +1155,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency
|
||||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 1892540 # number of replacements
|
system.cpu.icache.tags.replacements 1892540 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use
|
||||||
|
|
@ -1241,6 +1247,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1893071
|
||||||
system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
|
@ -1263,10 +1273,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 103160 # number of replacements
|
system.cpu.l2cache.tags.replacements 103160 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use
|
||||||
|
|
@ -1350,18 +1360,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses)
|
||||||
|
|
@ -1415,18 +1425,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -1467,6 +1477,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1476,26 +1494,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses
|
||||||
|
|
@ -1526,29 +1544,29 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution
|
||||||
|
|
@ -1559,38 +1577,34 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 #
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 62589 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 62589 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5.010244 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 3526784 98.98% 98.98% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 36501 1.02% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
@ -1796,8 +1810,8 @@ system.iocache.demand_avg_mshr_miss_latency::total 70600.330472
|
||||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
|
||||||
system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
|
system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
|
||||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 68566 # Transaction distribution
|
system.membus.trans_dist::ReadReq 68567 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 68565 # Transaction distribution
|
system.membus.trans_dist::ReadResp 68566 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
|
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
|
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
|
||||||
system.membus.trans_dist::Writeback 131056 # Transaction distribution
|
system.membus.trans_dist::Writeback 131056 # Transaction distribution
|
||||||
|
|
@ -1811,40 +1825,40 @@ system.membus.trans_dist::ReadExResp 138681 # Tr
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 497 # Total snoops (count)
|
system.membus.snoops 497 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 345038 # Request fanout histogram
|
system.membus.snoop_fanout::samples 406751 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 345038 # Request fanout histogram
|
system.membus.snoop_fanout::total 406751 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
|
system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks)
|
system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks)
|
system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
|
system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.827616 # Nu
|
||||||
sim_ticks 2827616186000 # Number of ticks simulated
|
sim_ticks 2827616186000 # Number of ticks simulated
|
||||||
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 94820 # Simulator instruction rate (inst/s)
|
host_inst_rate 97479 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 115016 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 118241 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 2369528287 # Simulator tick rate (ticks/s)
|
host_tick_rate 2435971946 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 555256 # Number of bytes of host memory used
|
host_mem_usage 621864 # Number of bytes of host memory used
|
||||||
host_seconds 1193.32 # Real time elapsed on the host
|
host_seconds 1160.78 # Real time elapsed on the host
|
||||||
sim_insts 113151083 # Number of instructions simulated
|
sim_insts 113151083 # Number of instructions simulated
|
||||||
sim_ops 137250963 # Number of ops (including micro ops) simulated
|
sim_ops 137250963 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -16,9 +16,9 @@ system.clk_domain.clock 1000 # Cl
|
||||||
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
|
system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
|
||||||
|
|
@ -27,18 +27,18 @@ system.physmem.bytes_written::total 8405108 # Nu
|
||||||
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
|
system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
|
system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
|
||||||
system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
|
system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
|
||||||
|
|
@ -48,19 +48,19 @@ system.physmem.bw_total::writebacks 2966309 # To
|
||||||
system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 176173 # Number of read requests accepted
|
system.physmem.readReqs 176174 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 171661 # Number of write requests accepted
|
system.physmem.writeReqs 171661 # Number of write requests accepted
|
||||||
system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
|
||||||
|
|
@ -100,7 +100,7 @@ system.physmem.numWrRetry 58 # Nu
|
||||||
system.physmem.totGap 2827615975000 # Total gap between requests
|
system.physmem.totGap 2827615975000 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 541 # Read request sizes (log2)
|
system.physmem.readPktSize::2 542 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 14 # Read request sizes (log2)
|
system.physmem.readPktSize::3 14 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 2994 # Read request sizes (log2)
|
system.physmem.readPktSize::4 2994 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
|
|
@ -265,12 +265,12 @@ system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Wr
|
||||||
system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
|
||||||
system.physmem.totQLat 2104910750 # Total ticks spent queuing
|
system.physmem.totQLat 2104913750 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
|
||||||
|
|
@ -285,35 +285,35 @@ system.physmem.readRowHits 145058 # Nu
|
||||||
system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 8129210.99 # Average gap between requests
|
system.physmem.avgGap 8129187.62 # Average gap between requests
|
||||||
system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
|
||||||
system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
|
system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
|
system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
|
system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
|
||||||
system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
|
system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
|
||||||
system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ)
|
system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ)
|
||||||
system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ)
|
system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ)
|
system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ)
|
||||||
system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
|
system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
|
||||||
system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states
|
system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
|
system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states
|
system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
|
system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
|
system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
|
||||||
system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
|
system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
|
||||||
system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
|
system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
|
||||||
system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ)
|
system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ)
|
||||||
system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ)
|
system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ)
|
system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ)
|
||||||
system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
|
system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
|
||||||
system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states
|
system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
|
system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states
|
system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states
|
||||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
|
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
|
||||||
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
|
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
|
||||||
|
|
@ -431,7 +431,7 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962
|
||||||
system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
|
system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
|
||||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu.dtb.read_hits 25461870 # DTB read hits
|
system.cpu.dtb.read_hits 25461869 # DTB read hits
|
||||||
system.cpu.dtb.read_misses 62291 # DTB read misses
|
system.cpu.dtb.read_misses 62291 # DTB read misses
|
||||||
system.cpu.dtb.write_hits 19915387 # DTB write hits
|
system.cpu.dtb.write_hits 19915387 # DTB write hits
|
||||||
system.cpu.dtb.write_misses 10080 # DTB write misses
|
system.cpu.dtb.write_misses 10080 # DTB write misses
|
||||||
|
|
@ -444,12 +444,12 @@ system.cpu.dtb.align_faults 348 # Nu
|
||||||
system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
|
system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
|
||||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||||
system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
|
system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
|
||||||
system.cpu.dtb.read_accesses 25524161 # DTB read accesses
|
system.cpu.dtb.read_accesses 25524160 # DTB read accesses
|
||||||
system.cpu.dtb.write_accesses 19925467 # DTB write accesses
|
system.cpu.dtb.write_accesses 19925467 # DTB write accesses
|
||||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||||
system.cpu.dtb.hits 45377257 # DTB hits
|
system.cpu.dtb.hits 45377256 # DTB hits
|
||||||
system.cpu.dtb.misses 72371 # DTB misses
|
system.cpu.dtb.misses 72371 # DTB misses
|
||||||
system.cpu.dtb.accesses 45449628 # DTB accesses
|
system.cpu.dtb.accesses 45449627 # DTB accesses
|
||||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||||
|
|
@ -591,15 +591,15 @@ system.cpu.decode.SquashedInsts 3690202 # Nu
|
||||||
system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
|
system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
|
||||||
system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
|
system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
|
||||||
system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
|
system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
|
||||||
system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst
|
system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
|
system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
|
||||||
system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking
|
system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking
|
||||||
system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
|
system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
|
||||||
system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
|
system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
|
||||||
system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
|
system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
|
||||||
system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
|
system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
|
||||||
system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
|
system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
|
||||||
system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full
|
system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full
|
||||||
system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
|
system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
|
||||||
system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
|
system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
|
||||||
system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
|
system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
|
||||||
|
|
@ -615,7 +615,7 @@ system.cpu.memDep0.conflictingLoads 1687720 # Nu
|
||||||
system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
|
system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
|
||||||
system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
|
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
|
system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
|
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
|
||||||
system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
|
|
@ -624,8 +624,8 @@ system.cpu.iq.issued_per_cycle::samples 256876545 # Nu
|
||||||
system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
|
||||||
system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
|
system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
|
||||||
|
|
@ -701,21 +701,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Ty
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued
|
system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued
|
||||||
system.cpu.iq.rate 0.544758 # Inst issue rate
|
system.cpu.iq.rate 0.544758 # Inst issue rate
|
||||||
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
|
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
|
||||||
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
|
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
|
system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads
|
||||||
system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
|
system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
|
||||||
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
|
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
|
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
|
||||||
system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
|
system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
|
||||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
|
system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses
|
||||||
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
|
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
|
||||||
system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
|
system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
|
||||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
|
|
@ -725,7 +725,7 @@ system.cpu.iew.lsq.thread0.memOrderViolation 18357
|
||||||
system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
|
system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
|
||||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled
|
system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled
|
||||||
system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
|
system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
|
||||||
|
|
@ -742,16 +742,16 @@ system.cpu.iew.memOrderViolationEvents 18357 # Nu
|
||||||
system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
|
system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
|
system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
|
system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
|
||||||
system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions
|
system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions
|
||||||
system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed
|
system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed
|
||||||
system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
|
system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
|
||||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu.iew.exec_nop 201053 # number of nop insts executed
|
system.cpu.iew.exec_nop 201053 # number of nop insts executed
|
||||||
system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed
|
system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed
|
||||||
system.cpu.iew.exec_branches 26530134 # Number of branches executed
|
system.cpu.iew.exec_branches 26530134 # Number of branches executed
|
||||||
system.cpu.iew.exec_stores 20877849 # Number of stores executed
|
system.cpu.iew.exec_stores 20877849 # Number of stores executed
|
||||||
system.cpu.iew.exec_rate 0.541163 # Inst execution rate
|
system.cpu.iew.exec_rate 0.541163 # Inst execution rate
|
||||||
system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit
|
system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit
|
||||||
system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
|
system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
|
||||||
system.cpu.iew.wb_producers 63271750 # num instructions producing a value
|
system.cpu.iew.wb_producers 63271750 # num instructions producing a value
|
||||||
system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
|
system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
|
||||||
|
|
@ -836,13 +836,13 @@ system.cpu.cpi 2.325250 # CP
|
||||||
system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
|
system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
|
||||||
system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
|
system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
|
||||||
system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
|
system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
|
||||||
system.cpu.int_regfile_reads 155826637 # number of integer regfile reads
|
system.cpu.int_regfile_reads 155826636 # number of integer regfile reads
|
||||||
system.cpu.int_regfile_writes 88633021 # number of integer regfile writes
|
system.cpu.int_regfile_writes 88633021 # number of integer regfile writes
|
||||||
system.cpu.fp_regfile_reads 9606 # number of floating regfile reads
|
system.cpu.fp_regfile_reads 9606 # number of floating regfile reads
|
||||||
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
|
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
|
||||||
system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads
|
system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads
|
||||||
system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
|
system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
|
||||||
system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads
|
system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads
|
||||||
system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
|
system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
|
||||||
system.cpu.dcache.tags.replacements 839617 # number of replacements
|
system.cpu.dcache.tags.replacements 839617 # number of replacements
|
||||||
system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use
|
system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use
|
||||||
|
|
@ -890,16 +890,16 @@ system.cpu.dcache.overall_misses::cpu.data 4478306 #
|
||||||
system.cpu.dcache.overall_misses::total 4478306 # number of overall misses
|
system.cpu.dcache.overall_misses::total 4478306 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
|
system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses)
|
||||||
|
|
@ -930,16 +930,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.102475
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked
|
||||||
|
|
@ -974,26 +974,32 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 714916
|
||||||
system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles
|
||||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles
|
||||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
|
||||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses
|
||||||
|
|
@ -1010,24 +1016,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency
|
||||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency
|
||||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency
|
||||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 1892540 # number of replacements
|
system.cpu.icache.tags.replacements 1892540 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use
|
||||||
|
|
@ -1102,6 +1108,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1893071
|
||||||
system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles
|
||||||
|
|
@ -1124,10 +1134,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 103160 # number of replacements
|
system.cpu.l2cache.tags.replacements 103160 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use
|
||||||
|
|
@ -1211,18 +1221,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses)
|
||||||
|
|
@ -1276,18 +1286,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -1328,6 +1338,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1337,26 +1355,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses
|
||||||
|
|
@ -1387,29 +1405,29 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution
|
||||||
|
|
@ -1420,36 +1438,34 @@ system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 #
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 62589 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 62589 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
@ -1655,8 +1671,8 @@ system.iocache.demand_avg_mshr_miss_latency::total 70600.330472
|
||||||
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
|
||||||
system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
|
system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
|
||||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 68566 # Transaction distribution
|
system.membus.trans_dist::ReadReq 68567 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 68565 # Transaction distribution
|
system.membus.trans_dist::ReadResp 68566 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
|
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
|
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
|
||||||
system.membus.trans_dist::Writeback 131056 # Transaction distribution
|
system.membus.trans_dist::Writeback 131056 # Transaction distribution
|
||||||
|
|
@ -1670,40 +1686,40 @@ system.membus.trans_dist::ReadExResp 138681 # Tr
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 497 # Total snoops (count)
|
system.membus.snoops 497 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 345038 # Request fanout histogram
|
system.membus.snoop_fanout::samples 406751 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 345038 # Request fanout histogram
|
system.membus.snoop_fanout::total 406751 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
|
system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks)
|
system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks)
|
system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
|
system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.817778 # Nu
|
||||||
sim_ticks 2817777605000 # Number of ticks simulated
|
sim_ticks 2817777605000 # Number of ticks simulated
|
||||||
final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 278686 # Simulator instruction rate (inst/s)
|
host_inst_rate 294801 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 338399 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 357967 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 6220604315 # Simulator tick rate (ticks/s)
|
host_tick_rate 6580315461 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 555292 # Number of bytes of host memory used
|
host_mem_usage 623656 # Number of bytes of host memory used
|
||||||
host_seconds 452.98 # Real time elapsed on the host
|
host_seconds 428.21 # Real time elapsed on the host
|
||||||
sim_insts 126237777 # Number of instructions simulated
|
sim_insts 126237777 # Number of instructions simulated
|
||||||
sim_ops 153286368 # Number of ops (including micro ops) simulated
|
sim_ops 153286368 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -775,6 +775,15 @@ system.cpu0.dcache.demand_mshr_misses::total 372246
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -844,15 +853,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177408.078231 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196862.425863 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188961.910353 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174550.967181 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 194575.011129 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186450.617284 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176153.849823 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 195857.412961 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 187858.921724 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 1799096 # number of replacements
|
system.cpu0.icache.tags.replacements 1799096 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use
|
||||||
|
|
@ -2270,6 +2279,15 @@ system.l2c.overall_mshr_misses::cpu2.dtb.walker 92
|
||||||
system.l2c.overall_mshr_misses::cpu2.inst 8124 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.inst 8124 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu2.data 64429 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.data 64429 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 91595 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 91595 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 132598250 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 132598250 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 173127242 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 173127242 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -2366,15 +2384,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163404.166667 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182859.169671 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 174958.388010 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161549.228429 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181573.304645 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173448.897707 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162589.876920 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 182294.203938 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 174295.402610 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 74250 # Transaction distribution
|
system.membus.trans_dist::ReadReq 74250 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 74249 # Transaction distribution
|
system.membus.trans_dist::ReadResp 74249 # Transaction distribution
|
||||||
|
|
@ -2405,17 +2423,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642624
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 283 # Total snoops (count)
|
system.membus.snoops 283 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 341064 # Request fanout histogram
|
system.membus.snoop_fanout::samples 408724 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 341064 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 408724 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 341064 # Request fanout histogram
|
system.membus.snoop_fanout::total 408724 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks)
|
system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks)
|
||||||
|
|
@ -2479,19 +2497,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 51752 # Total snoops (count)
|
system.toL2Bus.snoops 51752 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 3427725 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 3495385 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.010649 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.029269 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.102642 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.168561 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 3393077 97.07% 97.07% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 102308 2.93% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 3391224 98.94% 98.94% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 36501 1.06% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3427725 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3495385 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.804323 # Nu
|
||||||
sim_ticks 2804323403500 # Number of ticks simulated
|
sim_ticks 2804323403500 # Number of ticks simulated
|
||||||
final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 105186 # Simulator instruction rate (inst/s)
|
host_inst_rate 111575 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 127668 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 135423 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 2521360773 # Simulator tick rate (ticks/s)
|
host_tick_rate 2674508102 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 559780 # Number of bytes of host memory used
|
host_mem_usage 626368 # Number of bytes of host memory used
|
||||||
host_seconds 1112.23 # Real time elapsed on the host
|
host_seconds 1048.54 # Real time elapsed on the host
|
||||||
sim_insts 116990114 # Number of instructions simulated
|
sim_insts 116990114 # Number of instructions simulated
|
||||||
sim_ops 141995948 # Number of ops (including micro ops) simulated
|
sim_ops 141995948 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -19,9 +19,9 @@ system.physmem.bytes_read::cpu0.inst 690752 # Nu
|
||||||
system.physmem.bytes_read::cpu0.data 4989088 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu0.data 4989088 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu1.dtb.walker 4032 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu1.dtb.walker 4032 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu1.inst 687552 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu1.inst 687552 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::cpu1.data 4838852 # Number of bytes read from this memory
|
system.physmem.bytes_read::cpu1.data 4838856 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_read::total 11215652 # Number of bytes read from this memory
|
system.physmem.bytes_read::total 11215656 # Number of bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu0.inst 690752 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu0.inst 690752 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::cpu1.inst 687552 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::cpu1.inst 687552 # Number of instructions bytes read from this memory
|
||||||
system.physmem.bytes_inst_read::total 1378304 # Number of instructions bytes read from this memory
|
system.physmem.bytes_inst_read::total 1378304 # Number of instructions bytes read from this memory
|
||||||
|
|
@ -35,9 +35,9 @@ system.physmem.num_reads::cpu0.inst 10793 # Nu
|
||||||
system.physmem.num_reads::cpu0.data 78473 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu0.data 78473 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu1.dtb.walker 63 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu1.dtb.walker 63 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu1.inst 10743 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu1.inst 10743 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::cpu1.data 75608 # Number of read requests responded to by this memory
|
system.physmem.num_reads::cpu1.data 75609 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_reads::total 175764 # Number of read requests responded to by this memory
|
system.physmem.num_reads::total 175765 # Number of read requests responded to by this memory
|
||||||
system.physmem.num_writes::writebacks 131657 # Number of write requests responded to by this memory
|
system.physmem.num_writes::writebacks 131657 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
|
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
|
||||||
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
|
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
|
||||||
|
|
@ -48,9 +48,9 @@ system.physmem.bw_read::cpu0.inst 246317 # To
|
||||||
system.physmem.bw_read::cpu0.data 1779070 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu0.data 1779070 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu1.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu1.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu1.inst 245176 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu1.inst 245176 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::cpu1.data 1725497 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::cpu1.data 1725499 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_read::total 3999415 # Total read bandwidth from this memory (bytes/s)
|
system.physmem.bw_read::total 3999416 # Total read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu0.inst 246317 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu0.inst 246317 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::cpu1.inst 245176 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::cpu1.inst 245176 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
system.physmem.bw_inst_read::total 491493 # Instruction read bandwidth from this memory (bytes/s)
|
system.physmem.bw_inst_read::total 491493 # Instruction read bandwidth from this memory (bytes/s)
|
||||||
|
|
@ -65,19 +65,19 @@ system.physmem.bw_total::cpu0.inst 246317 # To
|
||||||
system.physmem.bw_total::cpu0.data 1785316 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu0.data 1785316 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu1.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu1.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu1.inst 245176 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu1.inst 245176 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu1.data 1725500 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu1.data 1725501 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 7010327 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 7010328 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.readReqs 175765 # Number of read requests accepted
|
system.physmem.readReqs 175766 # Number of read requests accepted
|
||||||
system.physmem.writeReqs 172232 # Number of write requests accepted
|
system.physmem.writeReqs 172232 # Number of write requests accepted
|
||||||
system.physmem.readBursts 175765 # Number of DRAM read bursts, including those serviced by the write queue
|
system.physmem.readBursts 175766 # Number of DRAM read bursts, including those serviced by the write queue
|
||||||
system.physmem.writeBursts 172232 # Number of DRAM write bursts, including those merged in the write queue
|
system.physmem.writeBursts 172232 # Number of DRAM write bursts, including those merged in the write queue
|
||||||
system.physmem.bytesReadDRAM 11239872 # Total number of bytes read from DRAM
|
system.physmem.bytesReadDRAM 11239872 # Total number of bytes read from DRAM
|
||||||
system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue
|
system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
|
||||||
system.physmem.bytesWritten 9513088 # Total number of bytes written to DRAM
|
system.physmem.bytesWritten 9513088 # Total number of bytes written to DRAM
|
||||||
system.physmem.bytesReadSys 11215716 # Total read bytes from the system interface side
|
system.physmem.bytesReadSys 11215720 # Total read bytes from the system interface side
|
||||||
system.physmem.bytesWrittenSys 10759988 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 10759988 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 23563 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 23563 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 4633 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 4633 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 11568 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 11568 # Per bank write bursts
|
||||||
|
|
@ -117,7 +117,7 @@ system.physmem.numWrRetry 53 # Nu
|
||||||
system.physmem.totGap 2804323239500 # Total gap between requests
|
system.physmem.totGap 2804323239500 # Total gap between requests
|
||||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::2 541 # Read request sizes (log2)
|
system.physmem.readPktSize::2 542 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::3 14 # Read request sizes (log2)
|
system.physmem.readPktSize::3 14 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||||
|
|
@ -279,12 +279,12 @@ system.physmem.wrPerTurnAround::528-543 1 0.02% 99.89% # Wr
|
||||||
system.physmem.wrPerTurnAround::544-559 6 0.10% 99.98% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::544-559 6 0.10% 99.98% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::608-623 1 0.02% 100.00% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::608-623 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::total 6306 # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::total 6306 # Writes before turning the bus around for reads
|
||||||
system.physmem.totQLat 2686689750 # Total ticks spent queuing
|
system.physmem.totQLat 2686692750 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 5979621000 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 5979624000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 878115000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 878115000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 15298.05 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 15298.07 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 34048.05 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 34048.07 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s
|
||||||
|
|
@ -299,7 +299,7 @@ system.physmem.readRowHits 145297 # Nu
|
||||||
system.physmem.writeRowHits 112992 # Number of row buffer hits during writes
|
system.physmem.writeRowHits 112992 # Number of row buffer hits during writes
|
||||||
system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads
|
system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads
|
||||||
system.physmem.writeRowHitRate 76.00 # Row buffer hit rate for writes
|
system.physmem.writeRowHitRate 76.00 # Row buffer hit rate for writes
|
||||||
system.physmem.avgGap 8058469.58 # Average gap between requests
|
system.physmem.avgGap 8058446.43 # Average gap between requests
|
||||||
system.physmem.pageHitRate 79.65 # Row buffer hit rate, read and write combined
|
system.physmem.pageHitRate 79.65 # Row buffer hit rate, read and write combined
|
||||||
system.physmem_0.actEnergy 264138840 # Energy for activate commands per rank (pJ)
|
system.physmem_0.actEnergy 264138840 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem_0.preEnergy 144123375 # Energy for precharge commands per rank (pJ)
|
system.physmem_0.preEnergy 144123375 # Energy for precharge commands per rank (pJ)
|
||||||
|
|
@ -1054,6 +1054,15 @@ system.cpu0.dcache.demand_mshr_misses::total 724963
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 427411 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 427411 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 420424 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 420424 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 847835 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 847835 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16558 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14569 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16166 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11418 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32724 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 25987 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2911652660 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2911652660 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2946522646 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2946522646 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5858175306 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5858175306 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1076,14 +1085,14 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10800326180
|
||||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10511181656 # number of overall MSHR miss cycles
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10511181656 # number of overall MSHR miss cycles
|
||||||
system.cpu0.dcache.overall_mshr_miss_latency::total 21311507836 # number of overall MSHR miss cycles
|
system.cpu0.dcache.overall_mshr_miss_latency::total 21311507836 # number of overall MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3107181500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3107181500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733312000 # number of ReadReq MSHR uncacheable cycles
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733353000 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840493500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840534500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2374455377 # number of WriteReq MSHR uncacheable cycles
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2374455377 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2136736500 # number of WriteReq MSHR uncacheable cycles
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2136736500 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4511191877 # number of WriteReq MSHR uncacheable cycles
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4511191877 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5481636877 # number of overall MSHR uncacheable cycles
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5481636877 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4870048500 # number of overall MSHR uncacheable cycles
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4870089500 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351685377 # number of overall MSHR uncacheable cycles
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351726377 # number of overall MSHR uncacheable cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for ReadReq accesses
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015934 # mshr miss rate for ReadReq accesses
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015934 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses
|
||||||
|
|
@ -1126,15 +1135,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27090.051611
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 187654.396666 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187614.318073 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187635.637871 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 146879.585364 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187137.545980 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163543.789044 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167511.211252 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187404.837034 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176316.642145 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 1944350 # number of replacements
|
system.cpu0.icache.tags.replacements 1944350 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 511.567211 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 511.567211 # Cycle average of tags in use
|
||||||
|
|
@ -1174,14 +1183,14 @@ system.cpu0.icache.overall_misses::cpu0.inst 1041065
|
||||||
system.cpu0.icache.overall_misses::cpu1.inst 1047869 # number of overall misses
|
system.cpu0.icache.overall_misses::cpu1.inst 1047869 # number of overall misses
|
||||||
system.cpu0.icache.overall_misses::total 2088934 # number of overall misses
|
system.cpu0.icache.overall_misses::total 2088934 # number of overall misses
|
||||||
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016266373 # number of ReadReq miss cycles
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016266373 # number of ReadReq miss cycles
|
||||||
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14162864905 # number of ReadReq miss cycles
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14162867905 # number of ReadReq miss cycles
|
||||||
system.cpu0.icache.ReadReq_miss_latency::total 28179131278 # number of ReadReq miss cycles
|
system.cpu0.icache.ReadReq_miss_latency::total 28179134278 # number of ReadReq miss cycles
|
||||||
system.cpu0.icache.demand_miss_latency::cpu0.inst 14016266373 # number of demand (read+write) miss cycles
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 14016266373 # number of demand (read+write) miss cycles
|
||||||
system.cpu0.icache.demand_miss_latency::cpu1.inst 14162864905 # number of demand (read+write) miss cycles
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 14162867905 # number of demand (read+write) miss cycles
|
||||||
system.cpu0.icache.demand_miss_latency::total 28179131278 # number of demand (read+write) miss cycles
|
system.cpu0.icache.demand_miss_latency::total 28179134278 # number of demand (read+write) miss cycles
|
||||||
system.cpu0.icache.overall_miss_latency::cpu0.inst 14016266373 # number of overall miss cycles
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 14016266373 # number of overall miss cycles
|
||||||
system.cpu0.icache.overall_miss_latency::cpu1.inst 14162864905 # number of overall miss cycles
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 14162867905 # number of overall miss cycles
|
||||||
system.cpu0.icache.overall_miss_latency::total 28179131278 # number of overall miss cycles
|
system.cpu0.icache.overall_miss_latency::total 28179134278 # number of overall miss cycles
|
||||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 20232960 # number of ReadReq accesses(hits+misses)
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 20232960 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu0.icache.ReadReq_accesses::cpu1.inst 20978073 # number of ReadReq accesses(hits+misses)
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 20978073 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu0.icache.ReadReq_accesses::total 41211033 # number of ReadReq accesses(hits+misses)
|
system.cpu0.icache.ReadReq_accesses::total 41211033 # number of ReadReq accesses(hits+misses)
|
||||||
|
|
@ -1201,14 +1210,14 @@ system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051454
|
||||||
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049951 # miss rate for overall accesses
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049951 # miss rate for overall accesses
|
||||||
system.cpu0.icache.overall_miss_rate::total 0.050689 # miss rate for overall accesses
|
system.cpu0.icache.overall_miss_rate::total 0.050689 # miss rate for overall accesses
|
||||||
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173 # average ReadReq miss latency
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173 # average ReadReq miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.873554 # average ReadReq miss latency
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.876417 # average ReadReq miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.718334 # average ReadReq miss latency
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.719770 # average ReadReq miss latency
|
||||||
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency
|
||||||
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.873554 # average overall miss latency
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.876417 # average overall miss latency
|
||||||
system.cpu0.icache.demand_avg_miss_latency::total 13489.718334 # average overall miss latency
|
system.cpu0.icache.demand_avg_miss_latency::total 13489.719770 # average overall miss latency
|
||||||
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency
|
||||||
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.873554 # average overall miss latency
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.876417 # average overall miss latency
|
||||||
system.cpu0.icache.overall_avg_miss_latency::total 13489.718334 # average overall miss latency
|
system.cpu0.icache.overall_avg_miss_latency::total 13489.719770 # average overall miss latency
|
||||||
system.cpu0.icache.blocked_cycles::no_mshrs 10636 # number of cycles access was blocked
|
system.cpu0.icache.blocked_cycles::no_mshrs 10636 # number of cycles access was blocked
|
||||||
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu0.icache.blocked::no_mshrs 597 # number of cycles access was blocked
|
system.cpu0.icache.blocked::no_mshrs 597 # number of cycles access was blocked
|
||||||
|
|
@ -1235,15 +1244,19 @@ system.cpu0.icache.demand_mshr_misses::total 1944951
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu0.inst 969720 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 969720 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu1.inst 975231 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 975231 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::total 1944951 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::total 1944951 # number of overall MSHR misses
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 666 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 666 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 666 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 666 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11896534814 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11896534814 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12012710558 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12012713558 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::total 23909245372 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 23909248372 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11896534814 # number of demand (read+write) MSHR miss cycles
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11896534814 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12012710558 # number of demand (read+write) MSHR miss cycles
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12012713558 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu0.icache.demand_mshr_miss_latency::total 23909245372 # number of demand (read+write) MSHR miss cycles
|
system.cpu0.icache.demand_mshr_miss_latency::total 23909248372 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11896534814 # number of overall MSHR miss cycles
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11896534814 # number of overall MSHR miss cycles
|
||||||
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12012710558 # number of overall MSHR miss cycles
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12012713558 # number of overall MSHR miss cycles
|
||||||
system.cpu0.icache.overall_mshr_miss_latency::total 23909245372 # number of overall MSHR miss cycles
|
system.cpu0.icache.overall_mshr_miss_latency::total 23909248372 # number of overall MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52863250 # number of ReadReq MSHR uncacheable cycles
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52863250 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52863250 # number of ReadReq MSHR uncacheable cycles
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52863250 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52863250 # number of overall MSHR uncacheable cycles
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52863250 # number of overall MSHR uncacheable cycles
|
||||||
|
|
@ -1258,18 +1271,18 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047928
|
||||||
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for overall accesses
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for overall accesses
|
||||||
system.cpu0.icache.overall_mshr_miss_rate::total 0.047195 # mshr miss rate for overall accesses
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.047195 # mshr miss rate for overall accesses
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average ReadReq mshr miss latency
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average ReadReq mshr miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average ReadReq mshr miss latency
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average ReadReq mshr miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.980837 # average ReadReq mshr miss latency
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.982380 # average ReadReq mshr miss latency
|
||||||
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency
|
||||||
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average overall mshr miss latency
|
||||||
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.982380 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.982380 # average overall mshr miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79374.249249 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79374.249249 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu1.branchPred.lookups 27831531 # Number of BP lookups
|
system.cpu1.branchPred.lookups 27831531 # Number of BP lookups
|
||||||
system.cpu1.branchPred.condPredicted 14488346 # Number of conditional branches predicted
|
system.cpu1.branchPred.condPredicted 14488346 # Number of conditional branches predicted
|
||||||
|
|
@ -1372,7 +1385,7 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5226
|
||||||
system.cpu1.dtb.walker.walkRequestOrigin::total 63374 # Table walker requests started/completed, data/inst
|
system.cpu1.dtb.walker.walkRequestOrigin::total 63374 # Table walker requests started/completed, data/inst
|
||||||
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
||||||
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
||||||
system.cpu1.dtb.read_hits 14522718 # DTB read hits
|
system.cpu1.dtb.read_hits 14522717 # DTB read hits
|
||||||
system.cpu1.dtb.read_misses 49745 # DTB read misses
|
system.cpu1.dtb.read_misses 49745 # DTB read misses
|
||||||
system.cpu1.dtb.write_hits 10695995 # DTB write hits
|
system.cpu1.dtb.write_hits 10695995 # DTB write hits
|
||||||
system.cpu1.dtb.write_misses 8403 # DTB write misses
|
system.cpu1.dtb.write_misses 8403 # DTB write misses
|
||||||
|
|
@ -1385,12 +1398,12 @@ system.cpu1.dtb.align_faults 922 # Nu
|
||||||
system.cpu1.dtb.prefetch_faults 1213 # Number of TLB faults due to prefetch
|
system.cpu1.dtb.prefetch_faults 1213 # Number of TLB faults due to prefetch
|
||||||
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||||
system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions
|
system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions
|
||||||
system.cpu1.dtb.read_accesses 14572463 # DTB read accesses
|
system.cpu1.dtb.read_accesses 14572462 # DTB read accesses
|
||||||
system.cpu1.dtb.write_accesses 10704398 # DTB write accesses
|
system.cpu1.dtb.write_accesses 10704398 # DTB write accesses
|
||||||
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
||||||
system.cpu1.dtb.hits 25218713 # DTB hits
|
system.cpu1.dtb.hits 25218712 # DTB hits
|
||||||
system.cpu1.dtb.misses 58148 # DTB misses
|
system.cpu1.dtb.misses 58148 # DTB misses
|
||||||
system.cpu1.dtb.accesses 25276861 # DTB accesses
|
system.cpu1.dtb.accesses 25276860 # DTB accesses
|
||||||
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||||
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||||
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||||
|
|
@ -1502,7 +1515,7 @@ system.cpu1.fetch.icacheStallCycles 40802320 # Nu
|
||||||
system.cpu1.fetch.Insts 108613899 # Number of instructions fetch has processed
|
system.cpu1.fetch.Insts 108613899 # Number of instructions fetch has processed
|
||||||
system.cpu1.fetch.Branches 27831531 # Number of branches that fetch encountered
|
system.cpu1.fetch.Branches 27831531 # Number of branches that fetch encountered
|
||||||
system.cpu1.fetch.predictedBranches 19968612 # Number of branches that fetch has predicted taken
|
system.cpu1.fetch.predictedBranches 19968612 # Number of branches that fetch has predicted taken
|
||||||
system.cpu1.fetch.Cycles 63156516 # Number of cycles fetch has run and was not squashing or blocked
|
system.cpu1.fetch.Cycles 63156510 # Number of cycles fetch has run and was not squashing or blocked
|
||||||
system.cpu1.fetch.SquashCycles 3276855 # Number of cycles fetch has spent squashing
|
system.cpu1.fetch.SquashCycles 3276855 # Number of cycles fetch has spent squashing
|
||||||
system.cpu1.fetch.TlbCycles 120748 # Number of cycles fetch has spent waiting for tlb
|
system.cpu1.fetch.TlbCycles 120748 # Number of cycles fetch has spent waiting for tlb
|
||||||
system.cpu1.fetch.MiscStallCycles 7463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
system.cpu1.fetch.MiscStallCycles 7463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||||
|
|
@ -1513,11 +1526,11 @@ system.cpu1.fetch.IcacheWaitRetryStallCycles 290
|
||||||
system.cpu1.fetch.CacheLines 20978077 # Number of cache lines fetched
|
system.cpu1.fetch.CacheLines 20978077 # Number of cache lines fetched
|
||||||
system.cpu1.fetch.IcacheSquashes 379105 # Number of outstanding Icache misses that were squashed
|
system.cpu1.fetch.IcacheSquashes 379105 # Number of outstanding Icache misses that were squashed
|
||||||
system.cpu1.fetch.ItlbSquashes 3473 # Number of outstanding ITLB misses that were squashed
|
system.cpu1.fetch.ItlbSquashes 3473 # Number of outstanding ITLB misses that were squashed
|
||||||
system.cpu1.fetch.rateDist::samples 106194794 # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::samples 106194788 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::mean 1.229505 # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::mean 1.229505 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::stdev 2.326126 # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::stdev 2.326126 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::0 76382369 71.93% 71.93% # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::0 76382363 71.93% 71.93% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::1 3967856 3.74% 75.66% # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::1 3967856 3.74% 75.66% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::2 2509209 2.36% 78.03% # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::2 2509209 2.36% 78.03% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::3 8248224 7.77% 85.79% # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::3 8248224 7.77% 85.79% # Number of instructions fetched each cycle (Total)
|
||||||
|
|
@ -1529,11 +1542,11 @@ system.cpu1.fetch.rateDist::8 4785005 4.51% 100.00% # Nu
|
||||||
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.rateDist::total 106194794 # Number of instructions fetched each cycle (Total)
|
system.cpu1.fetch.rateDist::total 106194788 # Number of instructions fetched each cycle (Total)
|
||||||
system.cpu1.fetch.branchRate 0.255909 # Number of branch fetches per cycle
|
system.cpu1.fetch.branchRate 0.255909 # Number of branch fetches per cycle
|
||||||
system.cpu1.fetch.rate 0.998697 # Number of inst fetches per cycle
|
system.cpu1.fetch.rate 0.998697 # Number of inst fetches per cycle
|
||||||
system.cpu1.decode.IdleCycles 27865394 # Number of cycles decode is idle
|
system.cpu1.decode.IdleCycles 27865394 # Number of cycles decode is idle
|
||||||
system.cpu1.decode.BlockedCycles 59086639 # Number of cycles decode is blocked
|
system.cpu1.decode.BlockedCycles 59086633 # Number of cycles decode is blocked
|
||||||
system.cpu1.decode.RunCycles 16014101 # Number of cycles decode is running
|
system.cpu1.decode.RunCycles 16014101 # Number of cycles decode is running
|
||||||
system.cpu1.decode.UnblockCycles 1741536 # Number of cycles decode is unblocking
|
system.cpu1.decode.UnblockCycles 1741536 # Number of cycles decode is unblocking
|
||||||
system.cpu1.decode.SquashCycles 1486862 # Number of cycles decode is squashing
|
system.cpu1.decode.SquashCycles 1486862 # Number of cycles decode is squashing
|
||||||
|
|
@ -1544,7 +1557,7 @@ system.cpu1.decode.SquashedInsts 499096 # Nu
|
||||||
system.cpu1.rename.SquashCycles 1486862 # Number of cycles rename is squashing
|
system.cpu1.rename.SquashCycles 1486862 # Number of cycles rename is squashing
|
||||||
system.cpu1.rename.IdleCycles 28829421 # Number of cycles rename is idle
|
system.cpu1.rename.IdleCycles 28829421 # Number of cycles rename is idle
|
||||||
system.cpu1.rename.BlockCycles 4993628 # Number of cycles rename is blocking
|
system.cpu1.rename.BlockCycles 4993628 # Number of cycles rename is blocking
|
||||||
system.cpu1.rename.serializeStallCycles 46364709 # count of cycles rename stalled for serializing inst
|
system.cpu1.rename.serializeStallCycles 46364703 # count of cycles rename stalled for serializing inst
|
||||||
system.cpu1.rename.RunCycles 16784538 # Number of cycles rename is running
|
system.cpu1.rename.RunCycles 16784538 # Number of cycles rename is running
|
||||||
system.cpu1.rename.UnblockCycles 7735362 # Number of cycles rename is unblocking
|
system.cpu1.rename.UnblockCycles 7735362 # Number of cycles rename is unblocking
|
||||||
system.cpu1.rename.RenamedInsts 86665296 # Number of instructions processed by rename
|
system.cpu1.rename.RenamedInsts 86665296 # Number of instructions processed by rename
|
||||||
|
|
@ -1567,17 +1580,17 @@ system.cpu1.memDep0.conflictingLoads 2188376 # Nu
|
||||||
system.cpu1.memDep0.conflictingStores 2888870 # Number of conflicting stores.
|
system.cpu1.memDep0.conflictingStores 2888870 # Number of conflicting stores.
|
||||||
system.cpu1.iq.iqInstsAdded 83375619 # Number of instructions added to the IQ (excludes non-spec)
|
system.cpu1.iq.iqInstsAdded 83375619 # Number of instructions added to the IQ (excludes non-spec)
|
||||||
system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ
|
system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ
|
||||||
system.cpu1.iq.iqInstsIssued 79910900 # Number of instructions issued
|
system.cpu1.iq.iqInstsIssued 79910899 # Number of instructions issued
|
||||||
system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued
|
system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued
|
||||||
system.cpu1.iq.iqSquashedInstsExamined 11441232 # Number of squashed instructions iterated over during squash; mainly for profiling
|
system.cpu1.iq.iqSquashedInstsExamined 11441232 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||||
system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph
|
system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph
|
||||||
system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed
|
system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed
|
||||||
system.cpu1.iq.issued_per_cycle::samples 106194794 # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::samples 106194788 # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::mean 0.752494 # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::mean 0.752494 # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::stdev 1.434563 # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::stdev 1.434563 # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::0 74167078 69.84% 69.84% # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::0 74167073 69.84% 69.84% # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::1 10703730 10.08% 79.92% # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::1 10703729 10.08% 79.92% # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::2 8178605 7.70% 87.62% # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::2 8178605 7.70% 87.62% # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::3 6800959 6.40% 94.03% # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::3 6800959 6.40% 94.03% # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::4 2513016 2.37% 96.39% # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::4 2513016 2.37% 96.39% # Number of insts issued each cycle
|
||||||
|
|
@ -1588,7 +1601,7 @@ system.cpu1.iq.issued_per_cycle::8 243435 0.23% 100.00% # Nu
|
||||||
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||||
system.cpu1.iq.issued_per_cycle::total 106194794 # Number of insts issued each cycle
|
system.cpu1.iq.issued_per_cycle::total 106194788 # Number of insts issued each cycle
|
||||||
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||||
system.cpu1.iq.fu_full::IntAlu 110018 9.66% 9.66% # attempts to use FU when none available
|
system.cpu1.iq.fu_full::IntAlu 110018 9.66% 9.66% # attempts to use FU when none available
|
||||||
system.cpu1.iq.fu_full::IntMult 6 0.00% 9.66% # attempts to use FU when none available
|
system.cpu1.iq.fu_full::IntMult 6 0.00% 9.66% # attempts to use FU when none available
|
||||||
|
|
@ -1653,21 +1666,21 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 4262 0.01% 67.14% # Ty
|
||||||
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.14% # Type of FU issued
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.14% # Type of FU issued
|
||||||
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.14% # Type of FU issued
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.14% # Type of FU issued
|
||||||
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.14% # Type of FU issued
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.14% # Type of FU issued
|
||||||
system.cpu1.iq.FU_type_0::MemRead 14931901 18.69% 85.82% # Type of FU issued
|
system.cpu1.iq.FU_type_0::MemRead 14931900 18.69% 85.82% # Type of FU issued
|
||||||
system.cpu1.iq.FU_type_0::MemWrite 11328871 14.18% 100.00% # Type of FU issued
|
system.cpu1.iq.FU_type_0::MemWrite 11328871 14.18% 100.00% # Type of FU issued
|
||||||
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||||
system.cpu1.iq.FU_type_0::total 79910900 # Type of FU issued
|
system.cpu1.iq.FU_type_0::total 79910899 # Type of FU issued
|
||||||
system.cpu1.iq.rate 0.734775 # Inst issue rate
|
system.cpu1.iq.rate 0.734775 # Inst issue rate
|
||||||
system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested
|
system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested
|
||||||
system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst)
|
system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst)
|
||||||
system.cpu1.iq.int_inst_queue_reads 267236211 # Number of integer instruction queue reads
|
system.cpu1.iq.int_inst_queue_reads 267236203 # Number of integer instruction queue reads
|
||||||
system.cpu1.iq.int_inst_queue_writes 96019084 # Number of integer instruction queue writes
|
system.cpu1.iq.int_inst_queue_writes 96019084 # Number of integer instruction queue writes
|
||||||
system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses
|
||||||
system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads
|
system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads
|
||||||
system.cpu1.iq.fp_inst_queue_writes 6290 # Number of floating instruction queue writes
|
system.cpu1.iq.fp_inst_queue_writes 6290 # Number of floating instruction queue writes
|
||||||
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses
|
||||||
system.cpu1.iq.int_alu_accesses 81043378 # Number of integer alu accesses
|
system.cpu1.iq.int_alu_accesses 81043377 # Number of integer alu accesses
|
||||||
system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses
|
system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses
|
||||||
system.cpu1.iew.lsq.thread0.forwLoads 351971 # Number of loads that had data forwarded from stores
|
system.cpu1.iew.lsq.thread0.forwLoads 351971 # Number of loads that had data forwarded from stores
|
||||||
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||||
|
|
@ -1677,7 +1690,7 @@ system.cpu1.iew.lsq.thread0.memOrderViolation 51509
|
||||||
system.cpu1.iew.lsq.thread0.squashedStores 1138977 # Number of stores squashed
|
system.cpu1.iew.lsq.thread0.squashedStores 1138977 # Number of stores squashed
|
||||||
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||||
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||||
system.cpu1.iew.lsq.thread0.rescheduledLoads 192559 # Number of loads that were rescheduled
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 192557 # Number of loads that were rescheduled
|
||||||
system.cpu1.iew.lsq.thread0.cacheBlocked 108870 # Number of times an access to memory failed due to the cache being blocked
|
system.cpu1.iew.lsq.thread0.cacheBlocked 108870 # Number of times an access to memory failed due to the cache being blocked
|
||||||
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||||
system.cpu1.iew.iewSquashCycles 1486862 # Number of cycles IEW is squashing
|
system.cpu1.iew.iewSquashCycles 1486862 # Number of cycles IEW is squashing
|
||||||
|
|
@ -1691,19 +1704,19 @@ system.cpu1.iew.iewDispNonSpecInsts 585252 # Nu
|
||||||
system.cpu1.iew.iewIQFullEvents 42277 # Number of times the IQ has become full, causing a stall
|
system.cpu1.iew.iewIQFullEvents 42277 # Number of times the IQ has become full, causing a stall
|
||||||
system.cpu1.iew.iewLSQFullEvents 608480 # Number of times the LSQ has become full, causing a stall
|
system.cpu1.iew.iewLSQFullEvents 608480 # Number of times the LSQ has become full, causing a stall
|
||||||
system.cpu1.iew.memOrderViolationEvents 51509 # Number of memory order violations
|
system.cpu1.iew.memOrderViolationEvents 51509 # Number of memory order violations
|
||||||
system.cpu1.iew.predictedTakenIncorrect 260306 # Number of branches that were predicted taken incorrectly
|
system.cpu1.iew.predictedTakenIncorrect 260301 # Number of branches that were predicted taken incorrectly
|
||||||
system.cpu1.iew.predictedNotTakenIncorrect 223242 # Number of branches that were predicted not taken incorrectly
|
system.cpu1.iew.predictedNotTakenIncorrect 223242 # Number of branches that were predicted not taken incorrectly
|
||||||
system.cpu1.iew.branchMispredicts 483548 # Number of branch mispredicts detected at execute
|
system.cpu1.iew.branchMispredicts 483543 # Number of branch mispredicts detected at execute
|
||||||
system.cpu1.iew.iewExecutedInsts 79294807 # Number of executed instructions
|
system.cpu1.iew.iewExecutedInsts 79294806 # Number of executed instructions
|
||||||
system.cpu1.iew.iewExecLoadInsts 14687603 # Number of load instructions executed
|
system.cpu1.iew.iewExecLoadInsts 14687602 # Number of load instructions executed
|
||||||
system.cpu1.iew.iewExecSquashedInsts 558095 # Number of squashed instructions skipped in execute
|
system.cpu1.iew.iewExecSquashedInsts 558095 # Number of squashed instructions skipped in execute
|
||||||
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
||||||
system.cpu1.iew.exec_nop 123637 # number of nop insts executed
|
system.cpu1.iew.exec_nop 123637 # number of nop insts executed
|
||||||
system.cpu1.iew.exec_refs 25906138 # number of memory reference insts executed
|
system.cpu1.iew.exec_refs 25906137 # number of memory reference insts executed
|
||||||
system.cpu1.iew.exec_branches 14775343 # Number of branches executed
|
system.cpu1.iew.exec_branches 14775343 # Number of branches executed
|
||||||
system.cpu1.iew.exec_stores 11218535 # Number of stores executed
|
system.cpu1.iew.exec_stores 11218535 # Number of stores executed
|
||||||
system.cpu1.iew.exec_rate 0.729110 # Inst execution rate
|
system.cpu1.iew.exec_rate 0.729110 # Inst execution rate
|
||||||
system.cpu1.iew.wb_sent 78721985 # cumulative count of insts sent to commit
|
system.cpu1.iew.wb_sent 78721983 # cumulative count of insts sent to commit
|
||||||
system.cpu1.iew.wb_count 77548836 # cumulative count of insts written-back
|
system.cpu1.iew.wb_count 77548836 # cumulative count of insts written-back
|
||||||
system.cpu1.iew.wb_producers 40818570 # num instructions producing a value
|
system.cpu1.iew.wb_producers 40818570 # num instructions producing a value
|
||||||
system.cpu1.iew.wb_consumers 71550295 # num instructions consuming a value
|
system.cpu1.iew.wb_consumers 71550295 # num instructions consuming a value
|
||||||
|
|
@ -1714,11 +1727,11 @@ system.cpu1.iew.wb_penalized_rate 0 # fr
|
||||||
system.cpu1.commit.commitSquashedInsts 11482053 # The number of squashed insts skipped by commit
|
system.cpu1.commit.commitSquashedInsts 11482053 # The number of squashed insts skipped by commit
|
||||||
system.cpu1.commit.commitNonSpecStalls 1050894 # The number of times commit has been forced to stall to communicate backwards
|
system.cpu1.commit.commitNonSpecStalls 1050894 # The number of times commit has been forced to stall to communicate backwards
|
||||||
system.cpu1.commit.branchMispredicts 406174 # The number of times a branch was mispredicted
|
system.cpu1.commit.branchMispredicts 406174 # The number of times a branch was mispredicted
|
||||||
system.cpu1.commit.committed_per_cycle::samples 103612513 # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::samples 103612507 # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::mean 0.706116 # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::mean 0.706116 # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::stdev 1.593552 # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::stdev 1.593552 # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::0 75208985 72.59% 72.59% # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::0 75208979 72.59% 72.59% # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::1 12628786 12.19% 84.78% # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::1 12628786 12.19% 84.78% # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::2 6551089 6.32% 91.10% # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::2 6551089 6.32% 91.10% # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::3 2721278 2.63% 93.72% # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::3 2721278 2.63% 93.72% # Number of insts commited each cycle
|
||||||
|
|
@ -1730,7 +1743,7 @@ system.cpu1.commit.committed_per_cycle::8 1807529 1.74% 100.00% # N
|
||||||
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committed_per_cycle::total 103612513 # Number of insts commited each cycle
|
system.cpu1.commit.committed_per_cycle::total 103612507 # Number of insts commited each cycle
|
||||||
system.cpu1.commit.committedInsts 60426665 # Number of instructions committed
|
system.cpu1.commit.committedInsts 60426665 # Number of instructions committed
|
||||||
system.cpu1.commit.committedOps 73162446 # Number of ops (including micro ops) committed
|
system.cpu1.commit.committedOps 73162446 # Number of ops (including micro ops) committed
|
||||||
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
||||||
|
|
@ -1777,10 +1790,10 @@ system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
||||||
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||||
system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction
|
system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction
|
||||||
system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached
|
system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached
|
||||||
system.cpu1.rob.rob_reads 173729023 # The number of ROB reads
|
system.cpu1.rob.rob_reads 173729017 # The number of ROB reads
|
||||||
system.cpu1.rob.rob_writes 171875858 # The number of ROB writes
|
system.cpu1.rob.rob_writes 171875858 # The number of ROB writes
|
||||||
system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||||
system.cpu1.idleCycles 2560821 # Total number of cycles that the CPU has spent unscheduled due to idling
|
system.cpu1.idleCycles 2560827 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||||
system.cpu1.quiesceCycles 2437360736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
system.cpu1.quiesceCycles 2437360736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||||
system.cpu1.committedInsts 60356761 # Number of Instructions Simulated
|
system.cpu1.committedInsts 60356761 # Number of Instructions Simulated
|
||||||
system.cpu1.committedOps 73092542 # Number of Ops (including micro ops) Simulated
|
system.cpu1.committedOps 73092542 # Number of Ops (including micro ops) Simulated
|
||||||
|
|
@ -1788,13 +1801,13 @@ system.cpu1.cpi 1.801880 # CP
|
||||||
system.cpu1.cpi_total 1.801880 # CPI: Total CPI of All Threads
|
system.cpu1.cpi_total 1.801880 # CPI: Total CPI of All Threads
|
||||||
system.cpu1.ipc 0.554976 # IPC: Instructions Per Cycle
|
system.cpu1.ipc 0.554976 # IPC: Instructions Per Cycle
|
||||||
system.cpu1.ipc_total 0.554976 # IPC: Total IPC of All Threads
|
system.cpu1.ipc_total 0.554976 # IPC: Total IPC of All Threads
|
||||||
system.cpu1.int_regfile_reads 86251315 # number of integer regfile reads
|
system.cpu1.int_regfile_reads 86251314 # number of integer regfile reads
|
||||||
system.cpu1.int_regfile_writes 49415173 # number of integer regfile writes
|
system.cpu1.int_regfile_writes 49415173 # number of integer regfile writes
|
||||||
system.cpu1.fp_regfile_reads 15994 # number of floating regfile reads
|
system.cpu1.fp_regfile_reads 15994 # number of floating regfile reads
|
||||||
system.cpu1.fp_regfile_writes 13022 # number of floating regfile writes
|
system.cpu1.fp_regfile_writes 13022 # number of floating regfile writes
|
||||||
system.cpu1.cc_regfile_reads 279979129 # number of cc regfile reads
|
system.cpu1.cc_regfile_reads 279979126 # number of cc regfile reads
|
||||||
system.cpu1.cc_regfile_writes 29562027 # number of cc regfile writes
|
system.cpu1.cc_regfile_writes 29562027 # number of cc regfile writes
|
||||||
system.cpu1.misc_regfile_reads 195055078 # number of misc regfile reads
|
system.cpu1.misc_regfile_reads 195055071 # number of misc regfile reads
|
||||||
system.cpu1.misc_regfile_writes 795609 # number of misc regfile writes
|
system.cpu1.misc_regfile_writes 795609 # number of misc regfile writes
|
||||||
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
|
||||||
|
|
@ -2109,9 +2122,9 @@ system.l2c.ReadReq_miss_latency::cpu0.itb.walker 68750
|
||||||
system.l2c.ReadReq_miss_latency::cpu0.inst 835233999 # number of ReadReq miss cycles
|
system.l2c.ReadReq_miss_latency::cpu0.inst 835233999 # number of ReadReq miss cycles
|
||||||
system.l2c.ReadReq_miss_latency::cpu0.data 610760750 # number of ReadReq miss cycles
|
system.l2c.ReadReq_miss_latency::cpu0.data 610760750 # number of ReadReq miss cycles
|
||||||
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5497500 # number of ReadReq miss cycles
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5497500 # number of ReadReq miss cycles
|
||||||
system.l2c.ReadReq_miss_latency::cpu1.inst 894308500 # number of ReadReq miss cycles
|
system.l2c.ReadReq_miss_latency::cpu1.inst 894311500 # number of ReadReq miss cycles
|
||||||
system.l2c.ReadReq_miss_latency::cpu1.data 720028000 # number of ReadReq miss cycles
|
system.l2c.ReadReq_miss_latency::cpu1.data 720028000 # number of ReadReq miss cycles
|
||||||
system.l2c.ReadReq_miss_latency::total 3071819249 # number of ReadReq miss cycles
|
system.l2c.ReadReq_miss_latency::total 3071822249 # number of ReadReq miss cycles
|
||||||
system.l2c.UpgradeReq_miss_latency::cpu0.data 436986 # number of UpgradeReq miss cycles
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 436986 # number of UpgradeReq miss cycles
|
||||||
system.l2c.UpgradeReq_miss_latency::cpu1.data 406987 # number of UpgradeReq miss cycles
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 406987 # number of UpgradeReq miss cycles
|
||||||
system.l2c.UpgradeReq_miss_latency::total 843973 # number of UpgradeReq miss cycles
|
system.l2c.UpgradeReq_miss_latency::total 843973 # number of UpgradeReq miss cycles
|
||||||
|
|
@ -2126,17 +2139,17 @@ system.l2c.demand_miss_latency::cpu0.itb.walker 68750
|
||||||
system.l2c.demand_miss_latency::cpu0.inst 835233999 # number of demand (read+write) miss cycles
|
system.l2c.demand_miss_latency::cpu0.inst 835233999 # number of demand (read+write) miss cycles
|
||||||
system.l2c.demand_miss_latency::cpu0.data 6637230290 # number of demand (read+write) miss cycles
|
system.l2c.demand_miss_latency::cpu0.data 6637230290 # number of demand (read+write) miss cycles
|
||||||
system.l2c.demand_miss_latency::cpu1.dtb.walker 5497500 # number of demand (read+write) miss cycles
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 5497500 # number of demand (read+write) miss cycles
|
||||||
system.l2c.demand_miss_latency::cpu1.inst 894308500 # number of demand (read+write) miss cycles
|
system.l2c.demand_miss_latency::cpu1.inst 894311500 # number of demand (read+write) miss cycles
|
||||||
system.l2c.demand_miss_latency::cpu1.data 6424786320 # number of demand (read+write) miss cycles
|
system.l2c.demand_miss_latency::cpu1.data 6424786320 # number of demand (read+write) miss cycles
|
||||||
system.l2c.demand_miss_latency::total 14803047109 # number of demand (read+write) miss cycles
|
system.l2c.demand_miss_latency::total 14803050109 # number of demand (read+write) miss cycles
|
||||||
system.l2c.overall_miss_latency::cpu0.dtb.walker 5921750 # number of overall miss cycles
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 5921750 # number of overall miss cycles
|
||||||
system.l2c.overall_miss_latency::cpu0.itb.walker 68750 # number of overall miss cycles
|
system.l2c.overall_miss_latency::cpu0.itb.walker 68750 # number of overall miss cycles
|
||||||
system.l2c.overall_miss_latency::cpu0.inst 835233999 # number of overall miss cycles
|
system.l2c.overall_miss_latency::cpu0.inst 835233999 # number of overall miss cycles
|
||||||
system.l2c.overall_miss_latency::cpu0.data 6637230290 # number of overall miss cycles
|
system.l2c.overall_miss_latency::cpu0.data 6637230290 # number of overall miss cycles
|
||||||
system.l2c.overall_miss_latency::cpu1.dtb.walker 5497500 # number of overall miss cycles
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 5497500 # number of overall miss cycles
|
||||||
system.l2c.overall_miss_latency::cpu1.inst 894308500 # number of overall miss cycles
|
system.l2c.overall_miss_latency::cpu1.inst 894311500 # number of overall miss cycles
|
||||||
system.l2c.overall_miss_latency::cpu1.data 6424786320 # number of overall miss cycles
|
system.l2c.overall_miss_latency::cpu1.data 6424786320 # number of overall miss cycles
|
||||||
system.l2c.overall_miss_latency::total 14803047109 # number of overall miss cycles
|
system.l2c.overall_miss_latency::total 14803050109 # number of overall miss cycles
|
||||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 36451 # number of ReadReq accesses(hits+misses)
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 36451 # number of ReadReq accesses(hits+misses)
|
||||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 8251 # number of ReadReq accesses(hits+misses)
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 8251 # number of ReadReq accesses(hits+misses)
|
||||||
system.l2c.ReadReq_accesses::cpu0.inst 969612 # number of ReadReq accesses(hits+misses)
|
system.l2c.ReadReq_accesses::cpu0.inst 969612 # number of ReadReq accesses(hits+misses)
|
||||||
|
|
@ -2213,9 +2226,9 @@ system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 68750
|
||||||
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82345.854185 # average ReadReq miss latency
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82345.854185 # average ReadReq miss latency
|
||||||
system.l2c.ReadReq_avg_miss_latency::cpu0.data 86473.276228 # average ReadReq miss latency
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 86473.276228 # average ReadReq miss latency
|
||||||
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average ReadReq miss latency
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average ReadReq miss latency
|
||||||
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83191.488372 # average ReadReq miss latency
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83191.767442 # average ReadReq miss latency
|
||||||
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88520.776985 # average ReadReq miss latency
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88520.776985 # average ReadReq miss latency
|
||||||
system.l2c.ReadReq_avg_miss_latency::total 84805.346171 # average ReadReq miss latency
|
system.l2c.ReadReq_avg_miss_latency::total 84805.428993 # average ReadReq miss latency
|
||||||
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 300.747419 # average UpgradeReq miss latency
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 300.747419 # average UpgradeReq miss latency
|
||||||
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 317.710383 # average UpgradeReq miss latency
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 317.710383 # average UpgradeReq miss latency
|
||||||
system.l2c.UpgradeReq_avg_miss_latency::total 308.695318 # average UpgradeReq miss latency
|
system.l2c.UpgradeReq_avg_miss_latency::total 308.695318 # average UpgradeReq miss latency
|
||||||
|
|
@ -2230,17 +2243,17 @@ system.l2c.demand_avg_miss_latency::cpu0.itb.walker 68750
|
||||||
system.l2c.demand_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency
|
system.l2c.demand_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency
|
||||||
system.l2c.demand_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency
|
system.l2c.demand_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency
|
||||||
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency
|
||||||
system.l2c.demand_avg_miss_latency::cpu1.inst 83191.488372 # average overall miss latency
|
system.l2c.demand_avg_miss_latency::cpu1.inst 83191.767442 # average overall miss latency
|
||||||
system.l2c.demand_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency
|
system.l2c.demand_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency
|
||||||
system.l2c.demand_avg_miss_latency::total 83697.817571 # average overall miss latency
|
system.l2c.demand_avg_miss_latency::total 83697.834533 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 68750 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 68750 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::cpu1.inst 83191.488372 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::cpu1.inst 83191.767442 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency
|
||||||
system.l2c.overall_avg_miss_latency::total 83697.817571 # average overall miss latency
|
system.l2c.overall_avg_miss_latency::total 83697.834533 # average overall miss latency
|
||||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -2299,14 +2312,25 @@ system.l2c.overall_mshr_misses::cpu1.dtb.walker 63
|
||||||
system.l2c.overall_mshr_misses::cpu1.inst 10744 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.inst 10744 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu1.data 76692 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.data 76692 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 176717 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 176717 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 666 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16558 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14569 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 31793 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16166 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11418 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 666 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32724 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 25987 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 59377 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 56250 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 56250 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 708062999 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 708062999 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 518326750 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 518326750 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 759667250 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 759670250 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 614985750 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 614985750 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::total 2610872749 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::total 2610875749 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25946451 # number of UpgradeReq MSHR miss cycles
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25946451 # number of UpgradeReq MSHR miss cycles
|
||||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22749281 # number of UpgradeReq MSHR miss cycles
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22749281 # number of UpgradeReq MSHR miss cycles
|
||||||
system.l2c.UpgradeReq_mshr_miss_latency::total 48695732 # number of UpgradeReq MSHR miss cycles
|
system.l2c.UpgradeReq_mshr_miss_latency::total 48695732 # number of UpgradeReq MSHR miss cycles
|
||||||
|
|
@ -2321,28 +2345,28 @@ system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 56250
|
||||||
system.l2c.demand_mshr_miss_latency::cpu0.inst 708062999 # number of demand (read+write) MSHR miss cycles
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 708062999 # number of demand (read+write) MSHR miss cycles
|
||||||
system.l2c.demand_mshr_miss_latency::cpu0.data 5648283210 # number of demand (read+write) MSHR miss cycles
|
system.l2c.demand_mshr_miss_latency::cpu0.data 5648283210 # number of demand (read+write) MSHR miss cycles
|
||||||
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of demand (read+write) MSHR miss cycles
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of demand (read+write) MSHR miss cycles
|
||||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 759667250 # number of demand (read+write) MSHR miss cycles
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 759670250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.l2c.demand_mshr_miss_latency::cpu1.data 5469024930 # number of demand (read+write) MSHR miss cycles
|
system.l2c.demand_mshr_miss_latency::cpu1.data 5469024930 # number of demand (read+write) MSHR miss cycles
|
||||||
system.l2c.demand_mshr_miss_latency::total 12594868389 # number of demand (read+write) MSHR miss cycles
|
system.l2c.demand_mshr_miss_latency::total 12594871389 # number of demand (read+write) MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of overall MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 56250 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 56250 # number of overall MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::cpu0.inst 708062999 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 708062999 # number of overall MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::cpu0.data 5648283210 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::cpu0.data 5648283210 # number of overall MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of overall MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 759667250 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 759670250 # number of overall MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::cpu1.data 5469024930 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::cpu1.data 5469024930 # number of overall MSHR miss cycles
|
||||||
system.l2c.overall_mshr_miss_latency::total 12594868389 # number of overall MSHR miss cycles
|
system.l2c.overall_mshr_miss_latency::total 12594871389 # number of overall MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 41164749 # number of ReadReq MSHR uncacheable cycles
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 41164749 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2875017500 # number of ReadReq MSHR uncacheable cycles
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2875017500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2529278000 # number of ReadReq MSHR uncacheable cycles
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2529305000 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 5445460249 # number of ReadReq MSHR uncacheable cycles
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 5445487249 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2162093500 # number of WriteReq MSHR uncacheable cycles
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2162093500 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1988256000 # number of WriteReq MSHR uncacheable cycles
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1988256000 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 4150349500 # number of WriteReq MSHR uncacheable cycles
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 4150349500 # number of WriteReq MSHR uncacheable cycles
|
||||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 41164749 # number of overall MSHR uncacheable cycles
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 41164749 # number of overall MSHR uncacheable cycles
|
||||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5037111000 # number of overall MSHR uncacheable cycles
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5037111000 # number of overall MSHR uncacheable cycles
|
||||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4517534000 # number of overall MSHR uncacheable cycles
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4517561000 # number of overall MSHR uncacheable cycles
|
||||||
system.l2c.overall_mshr_uncacheable_latency::total 9595809749 # number of overall MSHR uncacheable cycles
|
system.l2c.overall_mshr_uncacheable_latency::total 9595836749 # number of overall MSHR uncacheable cycles
|
||||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for ReadReq accesses
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for ReadReq accesses
|
||||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for ReadReq accesses
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for ReadReq accesses
|
||||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for ReadReq accesses
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for ReadReq accesses
|
||||||
|
|
@ -2381,9 +2405,9 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56250
|
||||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average ReadReq mshr miss latency
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average ReadReq mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715 # average ReadReq mshr miss latency
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715 # average ReadReq mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average ReadReq mshr miss latency
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average ReadReq mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average ReadReq mshr miss latency
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average ReadReq mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645 # average ReadReq mshr miss latency
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645 # average ReadReq mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.458837 # average ReadReq mshr miss latency
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.541995 # average ReadReq mshr miss latency
|
||||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293 # average UpgradeReq mshr miss latency
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293 # average UpgradeReq mshr miss latency
|
||||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561 # average UpgradeReq mshr miss latency
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561 # average UpgradeReq mshr miss latency
|
||||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520 # average UpgradeReq mshr miss latency
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520 # average UpgradeReq mshr miss latency
|
||||||
|
|
@ -2398,31 +2422,31 @@ system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 56250
|
||||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency
|
||||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency
|
||||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency
|
||||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency
|
||||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency
|
||||||
system.l2c.demand_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency
|
system.l2c.demand_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173633.138060 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173608.689684 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171279.440411 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133743.257454 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174133.473463 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150462.206352 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153927.117712 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173839.265787 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 161608.648955 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 68117 # Transaction distribution
|
system.membus.trans_dist::ReadReq 68118 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 68116 # Transaction distribution
|
system.membus.trans_dist::ReadResp 68117 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
|
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
|
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
|
||||||
system.membus.trans_dist::Writeback 131657 # Transaction distribution
|
system.membus.trans_dist::Writeback 131657 # Transaction distribution
|
||||||
|
|
@ -2436,40 +2460,40 @@ system.membus.trans_dist::ReadExResp 138750 # Tr
|
||||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465311 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465313 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.l2c.mem_side::total 572879 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.l2c.mem_side::total 572881 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108814 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108814 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 108814 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 108814 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 681693 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 681695 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344024 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344028 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.l2c.mem_side::total 17507929 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.l2c.mem_side::total 17507933 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631616 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631616 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4631616 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4631616 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 22139545 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 22139549 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 523 # Total snoops (count)
|
system.membus.snoops 523 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 347614 # Request fanout histogram
|
system.membus.snoop_fanout::samples 406994 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 347614 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 406994 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 347614 # Request fanout histogram
|
system.membus.snoop_fanout::total 406994 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 95655500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 95655500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer2.occupancy 1658000 # Layer occupancy (ticks)
|
system.membus.reqLayer2.occupancy 1658000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer5.occupancy 1067095796 # Layer occupancy (ticks)
|
system.membus.reqLayer5.occupancy 1067096296 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer2.occupancy 1022748121 # Layer occupancy (ticks)
|
system.membus.respLayer2.occupancy 1022750121 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer3.occupancy 37540981 # Layer occupancy (ticks)
|
system.membus.respLayer3.occupancy 37540981 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
@ -2504,8 +2528,8 @@ system.realview.ethernet.totalRxOrn 0 # to
|
||||||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||||
system.toL2Bus.trans_dist::ReadReq 2657013 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadReq 2657014 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::ReadResp 2656927 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadResp 2656928 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
|
system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
|
system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::Writeback 704443 # Transaction distribution
|
system.toL2Bus.trans_dist::Writeback 704443 # Transaction distribution
|
||||||
|
|
@ -2516,36 +2540,34 @@ system.toL2Bus.trans_dist::UpgradeResp 2876 # Tr
|
||||||
system.toL2Bus.trans_dist::ReadExReq 296803 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadExReq 296803 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::ReadExResp 296803 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadExResp 296803 # Transaction distribution
|
||||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891000 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891000 # Packet count per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536659 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536661 # Packet count per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42360 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42360 # Packet count per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169075 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169075 # Packet count per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_count::total 6639094 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count::total 6639096 # Packet count per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124504512 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124504512 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962073 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962077 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 64700 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 64700 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291504 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291504 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 224822789 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 224822793 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 70210 # Total snoops (count)
|
system.toL2Bus.snoops 70210 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 3665576 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 3724954 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.009952 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.042649 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.099262 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.202064 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 3566090 95.74% 95.74% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 158864 4.26% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 3629096 99.00% 99.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 36480 1.00% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3665576 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3724954 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 2562503934 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 2562504434 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.toL2Bus.respLayer0.occupancy 2923288858 # Layer occupancy (ticks)
|
system.toL2Bus.respLayer0.occupancy 2923288858 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.toL2Bus.respLayer1.occupancy 1353662761 # Layer occupancy (ticks)
|
system.toL2Bus.respLayer1.occupancy 1353663761 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
system.toL2Bus.respLayer2.occupancy 26203715 # Layer occupancy (ticks)
|
system.toL2Bus.respLayer2.occupancy 26203715 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 51.609999 # Nu
|
||||||
sim_ticks 51609998980000 # Number of ticks simulated
|
sim_ticks 51609998980000 # Number of ticks simulated
|
||||||
final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 125549 # Simulator instruction rate (inst/s)
|
host_inst_rate 182485 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 147521 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 214421 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 6837484784 # Simulator tick rate (ticks/s)
|
host_tick_rate 9938249935 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 653616 # Number of bytes of host memory used
|
host_mem_usage 720032 # Number of bytes of host memory used
|
||||||
host_seconds 7548.10 # Real time elapsed on the host
|
host_seconds 5193.07 # Real time elapsed on the host
|
||||||
sim_insts 947659008 # Number of instructions simulated
|
sim_insts 947659008 # Number of instructions simulated
|
||||||
sim_ops 1113505098 # Number of ops (including micro ops) simulated
|
sim_ops 1113505098 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -683,6 +683,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 8185275
|
||||||
system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -737,12 +743,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 24538707 # number of replacements
|
system.cpu.icache.tags.replacements 24538707 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use
|
||||||
|
|
@ -810,6 +816,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 24539229
|
||||||
system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 52294 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 52294 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles
|
||||||
|
|
@ -832,10 +842,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11822.574462
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 1594461 # number of replacements
|
system.cpu.l2cache.tags.replacements 1594461 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use
|
||||||
|
|
@ -1048,6 +1058,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5190
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85990 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119695 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1125,14 +1143,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74563.150289
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution
|
||||||
|
|
@ -1157,19 +1175,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 565529 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 565529 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 46009467 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 46129162 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.002514 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.039419 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.050072 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.194589 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 44310813 96.06% 96.06% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 1818349 3.94% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 46009467 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 46129162 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks)
|
||||||
|
|
@ -1440,17 +1456,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 2980 # Total snoops (count)
|
system.membus.snoops 2980 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 3310460 # Request fanout histogram
|
system.membus.snoop_fanout::samples 3430156 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 3430156 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 3310460 # Request fanout histogram
|
system.membus.snoop_fanout::total 3430156 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.320469 # Nu
|
||||||
sim_ticks 51320468905000 # Number of ticks simulated
|
sim_ticks 51320468905000 # Number of ticks simulated
|
||||||
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 88986 # Simulator instruction rate (inst/s)
|
host_inst_rate 81731 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 104557 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 96032 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 5338089020 # Simulator tick rate (ticks/s)
|
host_tick_rate 4902851121 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 657992 # Number of bytes of host memory used
|
host_mem_usage 723872 # Number of bytes of host memory used
|
||||||
host_seconds 9614.02 # Real time elapsed on the host
|
host_seconds 10467.47 # Real time elapsed on the host
|
||||||
sim_insts 855512158 # Number of instructions simulated
|
sim_insts 855512158 # Number of instructions simulated
|
||||||
sim_ops 1005211605 # Number of ops (including micro ops) simulated
|
sim_ops 1005211605 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1140,6 +1140,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 7197092
|
||||||
system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -1194,12 +1200,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 15070815 # number of replacements
|
system.cpu.icache.tags.replacements 15070815 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
|
||||||
|
|
@ -1273,6 +1279,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15071548
|
||||||
system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
|
||||||
|
|
@ -1295,10 +1305,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 1159288 # number of replacements
|
system.cpu.l2cache.tags.replacements 1159288 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
|
||||||
|
|
@ -1510,6 +1520,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1587,14 +1605,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
|
||||||
|
|
@ -1619,21 +1637,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5.003382 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 34071281 99.66% 99.66% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 115623 0.34% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
|
||||||
|
|
@ -1904,17 +1918,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 3023 # Total snoops (count)
|
system.membus.snoops 3023 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 2488136 # Request fanout histogram
|
system.membus.snoop_fanout::samples 2576774 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 2488136 # Request fanout histogram
|
system.membus.snoop_fanout::total 2576774 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 51.320469 # Nu
|
||||||
sim_ticks 51320468905000 # Number of ticks simulated
|
sim_ticks 51320468905000 # Number of ticks simulated
|
||||||
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 112338 # Simulator instruction rate (inst/s)
|
host_inst_rate 115752 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 131995 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 136007 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 6738935517 # Simulator tick rate (ticks/s)
|
host_tick_rate 6943747154 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 657468 # Number of bytes of host memory used
|
host_mem_usage 724128 # Number of bytes of host memory used
|
||||||
host_seconds 7615.52 # Real time elapsed on the host
|
host_seconds 7390.89 # Real time elapsed on the host
|
||||||
sim_insts 855512158 # Number of instructions simulated
|
sim_insts 855512158 # Number of instructions simulated
|
||||||
sim_ops 1005211605 # Number of ops (including micro ops) simulated
|
sim_ops 1005211605 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1001,6 +1001,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 7197092
|
||||||
system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -1055,12 +1061,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 15070815 # number of replacements
|
system.cpu.icache.tags.replacements 15070815 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
|
||||||
|
|
@ -1134,6 +1140,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15071548
|
||||||
system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
|
||||||
|
|
@ -1156,10 +1166,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 1159288 # number of replacements
|
system.cpu.l2cache.tags.replacements 1159288 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
|
||||||
|
|
@ -1371,6 +1381,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1448,14 +1466,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
|
||||||
|
|
@ -1480,19 +1498,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.003382 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 34071281 99.66% 99.66% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 115623 0.34% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
|
||||||
|
|
@ -1763,17 +1779,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 3023 # Total snoops (count)
|
system.membus.snoops 3023 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 2488136 # Request fanout histogram
|
system.membus.snoop_fanout::samples 2576774 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 2488136 # Request fanout histogram
|
system.membus.snoop_fanout::total 2576774 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
|
||||||
sim_ticks 51111152682000 # Number of ticks simulated
|
sim_ticks 51111152682000 # Number of ticks simulated
|
||||||
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 929959 # Simulator instruction rate (inst/s)
|
host_inst_rate 1198732 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1092854 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1408707 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 48276126697 # Simulator tick rate (ticks/s)
|
host_tick_rate 62228718243 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 712572 # Number of bytes of host memory used
|
host_mem_usage 717580 # Number of bytes of host memory used
|
||||||
host_seconds 1058.73 # Real time elapsed on the host
|
host_seconds 821.34 # Real time elapsed on the host
|
||||||
sim_insts 984570519 # Number of instructions simulated
|
sim_insts 984570519 # Number of instructions simulated
|
||||||
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -569,19 +569,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.034933 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.183610 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 1266605 3.49% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram
|
||||||
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
||||||
|
|
@ -724,17 +722,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
|
system.membus.snoop_fanout::samples 3693822 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 3693822 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 3583537 # Request fanout histogram
|
system.membus.snoop_fanout::total 3693822 # Request fanout histogram
|
||||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
|
||||||
sim_ticks 51111152682000 # Number of ticks simulated
|
sim_ticks 51111152682000 # Number of ticks simulated
|
||||||
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1276359 # Simulator instruction rate (inst/s)
|
host_inst_rate 1196191 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1405721 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 66258489115 # Simulator tick rate (ticks/s)
|
host_tick_rate 62096813616 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 712024 # Number of bytes of host memory used
|
host_mem_usage 713636 # Number of bytes of host memory used
|
||||||
host_seconds 771.39 # Real time elapsed on the host
|
host_seconds 823.09 # Real time elapsed on the host
|
||||||
sim_insts 984570519 # Number of instructions simulated
|
sim_insts 984570519 # Number of instructions simulated
|
||||||
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -569,19 +569,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.034933 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.183610 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 1266605 3.49% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram
|
||||||
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
||||||
|
|
@ -724,17 +722,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
|
system.membus.snoop_fanout::samples 3693822 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 3693822 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 3583537 # Request fanout histogram
|
system.membus.snoop_fanout::total 3693822 # Request fanout histogram
|
||||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 51.824462 # Nu
|
||||||
sim_ticks 51824462100500 # Number of ticks simulated
|
sim_ticks 51824462100500 # Number of ticks simulated
|
||||||
final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 723017 # Simulator instruction rate (inst/s)
|
host_inst_rate 684695 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 849578 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 804548 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 41937024652 # Simulator tick rate (ticks/s)
|
host_tick_rate 39714246392 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 712044 # Number of bytes of host memory used
|
host_mem_usage 713112 # Number of bytes of host memory used
|
||||||
host_seconds 1235.77 # Real time elapsed on the host
|
host_seconds 1304.93 # Real time elapsed on the host
|
||||||
sim_insts 893481288 # Number of instructions simulated
|
sim_insts 893481288 # Number of instructions simulated
|
||||||
sim_ops 1049881338 # Number of ops (including micro ops) simulated
|
sim_ops 1049881338 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -731,6 +731,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 7497734
|
||||||
system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -785,12 +791,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 13753173 # number of replacements
|
system.cpu.icache.tags.replacements 13753173 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use
|
||||||
|
|
@ -859,6 +865,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 13753690
|
||||||
system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles
|
||||||
|
|
@ -881,10 +891,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74459.988406 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74459.988406 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 1292250 # number of replacements
|
system.cpu.l2cache.tags.replacements 1292250 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use
|
||||||
|
|
@ -1089,6 +1099,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1166,14 +1184,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
|
||||||
|
|
@ -1198,19 +1216,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 470306 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 470306 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
|
||||||
|
|
@ -1481,17 +1497,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 3324 # Total snoops (count)
|
system.membus.snoops 3324 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 2750930 # Request fanout histogram
|
system.membus.snoop_fanout::samples 2861471 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 2750930 # Request fanout histogram
|
system.membus.snoop_fanout::total 2861471 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
|
||||||
sim_ticks 51111152682000 # Number of ticks simulated
|
sim_ticks 51111152682000 # Number of ticks simulated
|
||||||
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1095499 # Simulator instruction rate (inst/s)
|
host_inst_rate 1028340 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1208468 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 56869697369 # Simulator tick rate (ticks/s)
|
host_tick_rate 53383325140 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 728040 # Number of bytes of host memory used
|
host_mem_usage 714148 # Number of bytes of host memory used
|
||||||
host_seconds 898.74 # Real time elapsed on the host
|
host_seconds 957.44 # Real time elapsed on the host
|
||||||
sim_insts 984570519 # Number of instructions simulated
|
sim_insts 984570519 # Number of instructions simulated
|
||||||
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1018,17 +1018,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 3583531 # Request fanout histogram
|
system.membus.snoop_fanout::samples 3693816 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 3693816 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 3583531 # Request fanout histogram
|
system.membus.snoop_fanout::total 3693816 # Request fanout histogram
|
||||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||||
|
|
@ -1094,18 +1094,16 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 332
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 116338 # Total snoops (count)
|
system.toL2Bus.snoops 116338 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 36350757 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.037391 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.189718 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 34991565 96.26% 96.26% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 1359192 3.74% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 36350757 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.274696 # Nu
|
||||||
sim_ticks 51274696167500 # Number of ticks simulated
|
sim_ticks 51274696167500 # Number of ticks simulated
|
||||||
final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 281052 # Simulator instruction rate (inst/s)
|
host_inst_rate 293957 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 330247 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 345410 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 16260391227 # Simulator tick rate (ticks/s)
|
host_tick_rate 17006997815 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 656704 # Number of bytes of host memory used
|
host_mem_usage 724900 # Number of bytes of host memory used
|
||||||
host_seconds 3153.35 # Real time elapsed on the host
|
host_seconds 3014.92 # Real time elapsed on the host
|
||||||
sim_insts 886256415 # Number of instructions simulated
|
sim_insts 886256415 # Number of instructions simulated
|
||||||
sim_ops 1041383802 # Number of ops (including micro ops) simulated
|
sim_ops 1041383802 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -830,6 +830,15 @@ system.cpu0.dcache.demand_mshr_misses::total 3911848
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1288838 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1288838 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu2.data 3261967 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 3261967 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 4550805 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 4550805 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10846992750 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10846992750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30627833111 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30627833111 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41474825861 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41474825861 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -911,15 +920,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19118.200690
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164300.431351 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 178149.293514 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172652.928608 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166593.057882 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181697.568974 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175590.522688 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165438.799556 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 179883.665144 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174097.912607 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 14550991 # number of replacements
|
system.cpu0.icache.tags.replacements 14550991 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use
|
||||||
|
|
@ -2434,6 +2443,15 @@ system.l2c.overall_mshr_misses::cpu2.itb.walker 1470
|
||||||
system.l2c.overall_mshr_misses::cpu2.inst 34248 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.inst 34248 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu2.data 279438 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.data 279438 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 440923 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 440923 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 44046000 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 44046000 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 809585750 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 809585750 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -2557,15 +2575,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150300.018355 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 164140.053147 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 158647.191666 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 153591.103666 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 168686.141486 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162582.925427 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151934.155808 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 166362.148564 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 160583.154279 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 465050 # Transaction distribution
|
system.membus.trans_dist::ReadReq 465050 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 465050 # Transaction distribution
|
system.membus.trans_dist::ReadResp 465050 # Transaction distribution
|
||||||
|
|
@ -2596,17 +2614,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14192960
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 541 # Total snoops (count)
|
system.membus.snoops 541 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 2749696 # Request fanout histogram
|
system.membus.snoop_fanout::samples 2860073 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 2749696 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 2860073 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 2749696 # Request fanout histogram
|
system.membus.snoop_fanout::total 2860073 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks)
|
||||||
|
|
@ -2684,19 +2702,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 309
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 376855 # Total snoops (count)
|
system.toL2Bus.snoops 376855 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 34241641 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 34352020 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.003374 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.045142 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.057992 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.207615 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 32801302 95.49% 95.49% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 1550718 4.51% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 34126094 99.66% 99.66% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 115547 0.34% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 34241641 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 34352020 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.318118 # Nu
|
||||||
sim_ticks 51318118168000 # Number of ticks simulated
|
sim_ticks 51318118168000 # Number of ticks simulated
|
||||||
final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 135924 # Simulator instruction rate (inst/s)
|
host_inst_rate 134879 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 159711 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 158483 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 7679227340 # Simulator tick rate (ticks/s)
|
host_tick_rate 7620199718 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 666876 # Number of bytes of host memory used
|
host_mem_usage 732720 # Number of bytes of host memory used
|
||||||
host_seconds 6682.72 # Real time elapsed on the host
|
host_seconds 6734.48 # Real time elapsed on the host
|
||||||
sim_insts 908340493 # Number of instructions simulated
|
sim_insts 908340493 # Number of instructions simulated
|
||||||
sim_ops 1067303522 # Number of ops (including micro ops) simulated
|
sim_ops 1067303522 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1100,6 +1100,15 @@ system.cpu0.dcache.demand_mshr_misses::total 7984165
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4712310 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4712310 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4585034 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4585034 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 9297344 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 9297344 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16397 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17283 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17951 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 15746 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34348 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33029 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43556644701 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43556644701 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43095096417 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43095096417 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86651741118 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86651741118 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1181,15 +1190,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20667.469137
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170531.469171 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171562.706127 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171060.651722 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157771.853156 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176775.368792 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166651.853073 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 163863.020729 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174047.752187 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168855.696202 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 16169102 # number of replacements
|
system.cpu0.icache.tags.replacements 16169102 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 511.955735 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 511.955735 # Cycle average of tags in use
|
||||||
|
|
@ -1289,6 +1298,12 @@ system.cpu0.icache.demand_mshr_misses::total 16169736
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8013787 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8013787 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8155949 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8155949 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::total 16169736 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::total 16169736 # number of overall MSHR misses
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12341 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8298 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 20639 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12341 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8298 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 20639 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95968094429 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95968094429 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 97614087232 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 97614087232 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::total 193582181661 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 193582181661 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1322,12 +1337,12 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 11971.882637
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77088.546390 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77014.461316 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77058.760163 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77088.546390 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77014.461316 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77058.760163 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu1.branchPred.lookups 133788555 # Number of BP lookups
|
system.cpu1.branchPred.lookups 133788555 # Number of BP lookups
|
||||||
system.cpu1.branchPred.condPredicted 90573571 # Number of conditional branches predicted
|
system.cpu1.branchPred.condPredicted 90573571 # Number of conditional branches predicted
|
||||||
|
|
@ -2445,6 +2460,19 @@ system.l2c.overall_mshr_misses::cpu1.itb.walker 2269
|
||||||
system.l2c.overall_mshr_misses::cpu1.inst 48527 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.inst 48527 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu1.data 437424 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.data 437424 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 987592 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 987592 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 12341 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16397 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 8298 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17283 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 54319 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17951 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 15746 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 12341 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34348 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 8298 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33029 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 88016 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 175148007 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 175148007 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3515798206 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3515798206 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -2575,19 +2603,19 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156516.496920 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157547.431002 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 120004.326258 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144678.402317 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163761.748762 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153595.705730 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59586.844502 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150329.655293 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 59515.606170 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160509.998668 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 132864.814284 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 483310 # Transaction distribution
|
system.membus.trans_dist::ReadReq 483310 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 483310 # Transaction distribution
|
system.membus.trans_dist::ReadResp 483310 # Transaction distribution
|
||||||
|
|
@ -2618,17 +2646,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14081472
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14081472 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14081472 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 2786 # Total snoops (count)
|
system.membus.snoops 2786 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 2961350 # Request fanout histogram
|
system.membus.snoop_fanout::samples 3049369 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 2961350 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 3049369 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 2961350 # Request fanout histogram
|
system.membus.snoop_fanout::total 3049369 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks)
|
||||||
|
|
@ -2706,19 +2734,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 305
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8762408 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8762408 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 2260875858 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 2260875858 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 669395 # Total snoops (count)
|
system.toL2Bus.snoops 669395 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 37310136 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 37398155 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.003099 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.057385 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.055581 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.232578 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 35252045 94.26% 94.26% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 2146110 5.74% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 37194516 99.69% 99.69% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 115620 0.31% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 37310136 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 37398155 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 51.824541 # Nu
|
||||||
sim_ticks 51824540977500 # Number of ticks simulated
|
sim_ticks 51824540977500 # Number of ticks simulated
|
||||||
final_tick 51824540977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 51824540977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 650287 # Simulator instruction rate (inst/s)
|
host_inst_rate 636803 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 764161 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 748315 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 37795835393 # Simulator tick rate (ticks/s)
|
host_tick_rate 37012113234 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 728296 # Number of bytes of host memory used
|
host_mem_usage 715168 # Number of bytes of host memory used
|
||||||
host_seconds 1371.17 # Real time elapsed on the host
|
host_seconds 1400.21 # Real time elapsed on the host
|
||||||
sim_insts 891654507 # Number of instructions simulated
|
sim_insts 891654507 # Number of instructions simulated
|
||||||
sim_ops 1047794539 # Number of ops (including micro ops) simulated
|
sim_ops 1047794539 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -814,6 +814,15 @@ system.cpu0.dcache.demand_mshr_misses::total 7479901
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4385256 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4385256 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4391055 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4391055 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 8776311 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 8776311 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17713 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15993 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16112 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 17598 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33825 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33591 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37598794000 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37598794000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37923223247 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37923223247 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 75522017247 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 75522017247 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -895,15 +904,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18399.677139
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168981.143793 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172453.964234 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.945885 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175756.144489 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158359.117513 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.184218 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172208.307465 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165069.810366 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168651.447728 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 13976964 # number of replacements
|
system.cpu0.icache.tags.replacements 13976964 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 511.880033 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 511.880033 # Cycle average of tags in use
|
||||||
|
|
@ -995,6 +1004,12 @@ system.cpu0.icache.demand_mshr_misses::total 13977481
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu0.inst 7004074 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 7004074 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu1.inst 6973407 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 6973407 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::total 13977481 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::total 13977481 # number of overall MSHR misses
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 25928 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 17197 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 25928 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 17197 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 83323187568 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 83323187568 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 83088246273 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 83088246273 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::total 166411433841 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 166411433841 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1028,12 +1043,12 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.681277
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.681277 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.681277 # average overall mshr miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74458.556522 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74458.556522 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||||
|
|
@ -1833,6 +1848,19 @@ system.l2c.overall_mshr_misses::cpu1.itb.walker 2035
|
||||||
system.l2c.overall_mshr_misses::cpu1.inst 40460 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.inst 40460 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu1.data 410262 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.data 410262 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 878082 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 878082 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 25928 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17713 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 17197 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15993 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16112 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17598 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 25928 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33825 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 17197 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 33591 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152020000 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152020000 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2697284444 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2697284444 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1963,19 +1991,19 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154974.947778 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158447.133121 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102365.321290 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162747.486346 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145352.227526 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153666.449125 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158677.272727 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151586.838737 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 118009.842502 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 450083 # Transaction distribution
|
system.membus.trans_dist::ReadReq 450083 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 450083 # Transaction distribution
|
system.membus.trans_dist::ReadResp 450083 # Transaction distribution
|
||||||
|
|
@ -2006,17 +2034,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14048000
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 14048000 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 14048000 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 174054362 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 174054362 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 3335 # Total snoops (count)
|
system.membus.snoops 3335 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 2753479 # Request fanout histogram
|
system.membus.snoop_fanout::samples 2864020 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 2753479 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 2864020 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 2753479 # Request fanout histogram
|
system.membus.snoop_fanout::total 2864020 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 107121000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 107121000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
||||||
|
|
@ -2094,19 +2122,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 268
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3951520 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3951520 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 2057658738 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 2057658738 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 492069 # Total snoops (count)
|
system.toL2Bus.snoops 492069 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 33406949 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 33517490 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.003462 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.039407 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.058735 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.194561 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 32196665 96.06% 96.06% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 1320825 3.94% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 33291303 99.65% 99.65% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 115646 0.35% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 33406949 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 33517490 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 25817690750 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 25817690750 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 1207500 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 1207500 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.122213 # Nu
|
||||||
sim_ticks 5122212682000 # Number of ticks simulated
|
sim_ticks 5122212682000 # Number of ticks simulated
|
||||||
final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 132606 # Simulator instruction rate (inst/s)
|
host_inst_rate 178126 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 262116 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 352092 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1665061517 # Simulator tick rate (ticks/s)
|
host_tick_rate 2236626113 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 804736 # Number of bytes of host memory used
|
host_mem_usage 810964 # Number of bytes of host memory used
|
||||||
host_seconds 3076.29 # Real time elapsed on the host
|
host_seconds 2290.15 # Real time elapsed on the host
|
||||||
sim_insts 407934867 # Number of instructions simulated
|
sim_insts 407934867 # Number of instructions simulated
|
||||||
sim_ops 806343968 # Number of ops (including micro ops) simulated
|
sim_ops 806343968 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -717,6 +717,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1259107
|
||||||
system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -753,12 +759,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19997.167509
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161161.122604 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186317.120483 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 161727.134590 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
|
system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
|
||||||
system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
|
system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
|
||||||
|
|
@ -1211,6 +1217,12 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 604701 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 604701 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13919 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1274,12 +1286,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 82571.428571
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 147161.069686 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173241.755873 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 147747.887233 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
|
||||||
|
|
@ -1291,6 +1303,7 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # T
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
|
||||||
|
|
@ -1302,20 +1315,20 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 61672 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 63315 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4387054 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.010870 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103692 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.098766 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 4339366 98.91% 98.91% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::3 4957986 99.01% 99.01% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 47688 1.09% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::4 49331 0.99% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4387054 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 5007317 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
|
||||||
|
|
@ -1560,17 +1573,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 1635 # Total snoops (count)
|
system.membus.snoops 1635 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 385314 # Request fanout histogram
|
system.membus.snoop_fanout::samples 1005577 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.040388 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 385314 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 1003934 99.84% 99.84% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 1643 0.16% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 385314 # Request fanout histogram
|
system.membus.snoop_fanout::total 1005577 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.133731 # Nu
|
||||||
sim_ticks 5133731116500 # Number of ticks simulated
|
sim_ticks 5133731116500 # Number of ticks simulated
|
||||||
final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 201130 # Simulator instruction rate (inst/s)
|
host_inst_rate 268887 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 399856 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 534560 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 4230291451 # Simulator tick rate (ticks/s)
|
host_tick_rate 5655392824 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 1019904 # Number of bytes of host memory used
|
host_mem_usage 1025452 # Number of bytes of host memory used
|
||||||
host_seconds 1213.56 # Real time elapsed on the host
|
host_seconds 907.76 # Real time elapsed on the host
|
||||||
sim_insts 244084329 # Number of instructions simulated
|
sim_insts 244084329 # Number of instructions simulated
|
||||||
sim_ops 485251122 # Number of ops (including micro ops) simulated
|
sim_ops 485251122 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -559,6 +559,15 @@ system.cpu0.dcache.demand_mshr_misses::total 764859
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -613,15 +622,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18052.198644
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163421.889569 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 160883.484080 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162092.138802 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174047.418794 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196782.670455 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186073.497268 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 163614.652061 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 161547.981911 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 162531.827575 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 871419 # number of replacements
|
system.cpu0.icache.tags.replacements 871419 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use
|
||||||
|
|
@ -1630,6 +1639,15 @@ system.l2c.overall_mshr_misses::cpu2.dtb.walker 35
|
||||||
system.l2c.overall_mshr_misses::cpu2.inst 5224 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.inst 5224 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 186614 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 205311 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 391925 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3448 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 7320 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 209183 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1720,15 +1738,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149115.529917 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 146883.437809 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147946.242266 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160916.038283 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 183774.535124 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173007.308743 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 149329.608233 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 147566.296018 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 148405.727060 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 5117226 # Transaction distribution
|
system.membus.trans_dist::ReadReq 5117226 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 5117226 # Transaction distribution
|
system.membus.trans_dist::ReadResp 5117226 # Transaction distribution
|
||||||
|
|
@ -1762,17 +1780,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6011648
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 820 # Total snoops (count)
|
system.membus.snoops 820 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 372049 # Request fanout histogram
|
system.membus.snoop_fanout::samples 5455844 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1.000311 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.017639 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 372049 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 5454146 99.97% 99.97% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 1698 0.03% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 372049 # Request fanout histogram
|
system.membus.snoop_fanout::total 5455844 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks)
|
||||||
|
|
@ -1809,6 +1827,7 @@ system.toL2Bus.trans_dist::UpgradeReq 1672 # Tr
|
||||||
system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution
|
system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution
|
||||||
|
system.toL2Bus.trans_dist::MessageReq 1151 # Transaction distribution
|
||||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes)
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes)
|
||||||
|
|
@ -1819,20 +1838,18 @@ system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2133
|
||||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 72565 # Total snoops (count)
|
system.toL2Bus.snoops 74263 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 4266300 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 9350095 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.011166 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.022573 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.105077 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.148538 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 9139035 97.74% 97.74% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 211060 2.26% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 4218663 98.88% 98.88% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 47637 1.12% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 4266300 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 9350095 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.061594 # Nu
|
||||||
sim_ticks 61594138500 # Number of ticks simulated
|
sim_ticks 61594138500 # Number of ticks simulated
|
||||||
final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 196979 # Simulator instruction rate (inst/s)
|
host_inst_rate 265976 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 197960 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 267300 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 133911114 # Simulator tick rate (ticks/s)
|
host_tick_rate 180817037 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 438496 # Number of bytes of host memory used
|
host_mem_usage 446692 # Number of bytes of host memory used
|
||||||
host_seconds 459.96 # Real time elapsed on the host
|
host_seconds 340.64 # Real time elapsed on the host
|
||||||
sim_insts 90602850 # Number of instructions simulated
|
sim_insts 90602850 # Number of instructions simulated
|
||||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -779,17 +779,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 1894252 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.058203 # Nu
|
||||||
sim_ticks 58203290500 # Number of ticks simulated
|
sim_ticks 58203290500 # Number of ticks simulated
|
||||||
final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 98982 # Simulator instruction rate (inst/s)
|
host_inst_rate 131910 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 99475 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 132567 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 63595388 # Simulator tick rate (ticks/s)
|
host_tick_rate 84750962 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 438244 # Number of bytes of host memory used
|
host_mem_usage 445160 # Number of bytes of host memory used
|
||||||
host_seconds 915.21 # Real time elapsed on the host
|
host_seconds 686.76 # Real time elapsed on the host
|
||||||
sim_insts 90589799 # Number of instructions simulated
|
sim_insts 90589799 # Number of instructions simulated
|
||||||
sim_ops 91041030 # Number of ops (including micro ops) simulated
|
sim_ops 91041030 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1154,17 +1154,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 22116 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 22116 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.002023 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.002023 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 10908954 99.80% 99.80% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 22114 0.20% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 10908954 99.80% 99.80% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 22114 0.20% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.062108 # Nu
|
||||||
sim_ticks 62108139000 # Number of ticks simulated
|
sim_ticks 62108139000 # Number of ticks simulated
|
||||||
final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 88749 # Simulator instruction rate (inst/s)
|
host_inst_rate 114338 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 156272 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 201331 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 34888646 # Simulator tick rate (ticks/s)
|
host_tick_rate 44948395 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 448856 # Number of bytes of host memory used
|
host_mem_usage 455560 # Number of bytes of host memory used
|
||||||
host_seconds 1780.18 # Real time elapsed on the host
|
host_seconds 1381.77 # Real time elapsed on the host
|
||||||
sim_insts 157988547 # Number of instructions simulated
|
sim_insts 157988547 # Number of instructions simulated
|
||||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -946,17 +946,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 4144289 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 4144289 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
|
||||||
sim_ticks 365989065500 # Number of ticks simulated
|
sim_ticks 365989065500 # Number of ticks simulated
|
||||||
final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 638452 # Simulator instruction rate (inst/s)
|
host_inst_rate 678113 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1479007835 # Simulator tick rate (ticks/s)
|
host_tick_rate 1570885616 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 450980 # Number of bytes of host memory used
|
host_mem_usage 451452 # Number of bytes of host memory used
|
||||||
host_seconds 247.46 # Real time elapsed on the host
|
host_seconds 232.98 # Real time elapsed on the host
|
||||||
sim_insts 157988548 # Number of instructions simulated
|
sim_insts 157988548 # Number of instructions simulated
|
||||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -452,17 +452,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.366340 # Nu
|
||||||
sim_ticks 366339500500 # Number of ticks simulated
|
sim_ticks 366339500500 # Number of ticks simulated
|
||||||
final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 174606 # Simulator instruction rate (inst/s)
|
host_inst_rate 237525 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 189122 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 257271 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 126268215 # Simulator tick rate (ticks/s)
|
host_tick_rate 171768388 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 309684 # Number of bytes of host memory used
|
host_mem_usage 317860 # Number of bytes of host memory used
|
||||||
host_seconds 2901.28 # Real time elapsed on the host
|
host_seconds 2132.75 # Real time elapsed on the host
|
||||||
sim_insts 506582156 # Number of instructions simulated
|
sim_insts 506582156 # Number of instructions simulated
|
||||||
sim_ops 548695379 # Number of ops (including micro ops) simulated
|
sim_ops 548695379 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -824,17 +824,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 2232032 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 2232032 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.233457 # Nu
|
||||||
sim_ticks 233457400500 # Number of ticks simulated
|
sim_ticks 233457400500 # Number of ticks simulated
|
||||||
final_tick 233457400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 233457400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 105147 # Simulator instruction rate (inst/s)
|
host_inst_rate 140578 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 113911 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 152296 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 48585649 # Simulator tick rate (ticks/s)
|
host_tick_rate 64957541 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 312624 # Number of bytes of host memory used
|
host_mem_usage 319412 # Number of bytes of host memory used
|
||||||
host_seconds 4805.07 # Real time elapsed on the host
|
host_seconds 3594.00 # Real time elapsed on the host
|
||||||
sim_insts 505237724 # Number of instructions simulated
|
sim_insts 505237724 # Number of instructions simulated
|
||||||
sim_ops 547350945 # Number of ops (including micro ops) simulated
|
sim_ops 547350945 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1159,17 +1159,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 335917632 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 335917632 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 317126 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 317126 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 5565869 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 5565869 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.056971 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.056971 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.231787 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.231787 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 5248777 94.30% 94.30% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 317092 5.70% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 5248777 94.30% 94.30% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 317092 5.70% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 5565869 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 5565869 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 4977148500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 4977148500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu
|
||||||
sim_ticks 279362298000 # Number of ticks simulated
|
sim_ticks 279362298000 # Number of ticks simulated
|
||||||
final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1382525 # Simulator instruction rate (inst/s)
|
host_inst_rate 1944100 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1497457 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2105717 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 762414599 # Simulator tick rate (ticks/s)
|
host_tick_rate 1072104103 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 298924 # Number of bytes of host memory used
|
host_mem_usage 306580 # Number of bytes of host memory used
|
||||||
host_seconds 366.42 # Real time elapsed on the host
|
host_seconds 260.57 # Real time elapsed on the host
|
||||||
sim_insts 506581608 # Number of instructions simulated
|
sim_insts 506581608 # Number of instructions simulated
|
||||||
sim_ops 548694829 # Number of ops (including micro ops) simulated
|
sim_ops 548694829 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325
|
||||||
system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 687930750 # Request fanout histogram
|
system.membus.snoop_fanout::samples 687930750 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.750964 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 171319374 24.90% 24.90% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 516611376 75.10% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 516611376 75.10% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 687930750 # Request fanout histogram
|
system.membus.snoop_fanout::total 687930750 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -593,17 +593,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu
|
||||||
sim_ticks 885229328000 # Number of ticks simulated
|
sim_ticks 885229328000 # Number of ticks simulated
|
||||||
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1229934 # Simulator instruction rate (inst/s)
|
host_inst_rate 1361574 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 2274285 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2517703 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1316729165 # Simulator tick rate (ticks/s)
|
host_tick_rate 1457659146 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 308776 # Number of bytes of host memory used
|
host_mem_usage 313840 # Number of bytes of host memory used
|
||||||
host_seconds 672.29 # Real time elapsed on the host
|
host_seconds 607.30 # Real time elapsed on the host
|
||||||
sim_insts 826877110 # Number of instructions simulated
|
sim_insts 826877110 # Number of instructions simulated
|
||||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -35,33 +35,6 @@ system.physmem.bw_write::total 1120443517 # Wr
|
||||||
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteReq 149160202 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteResp 149160202 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 2.667046 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::2 533262388 33.30% 33.30% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 1068347065 66.70% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 1601609453 # Request fanout histogram
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||||
|
|
@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 1528988702 # Class of executed instruction
|
system.cpu.op_class::total 1528988702 # Class of executed instruction
|
||||||
|
system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteReq 149160202 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteResp 149160202 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0.667046 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 533262388 33.30% 33.30% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 1068347065 66.70% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 1601609453 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
|
||||||
sim_ticks 1647872738500 # Number of ticks simulated
|
sim_ticks 1647872738500 # Number of ticks simulated
|
||||||
final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 730118 # Simulator instruction rate (inst/s)
|
host_inst_rate 720688 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1332632 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1455043701 # Simulator tick rate (ticks/s)
|
host_tick_rate 1436248802 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 323120 # Number of bytes of host memory used
|
host_mem_usage 323576 # Number of bytes of host memory used
|
||||||
host_seconds 1132.52 # Real time elapsed on the host
|
host_seconds 1147.35 # Real time elapsed on the host
|
||||||
sim_insts 826877110 # Number of instructions simulated
|
sim_insts 826877110 # Number of instructions simulated
|
||||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -454,17 +454,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 4844795 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 4844795 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.216744 # Nu
|
||||||
sim_ticks 216744260000 # Number of ticks simulated
|
sim_ticks 216744260000 # Number of ticks simulated
|
||||||
final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 123383 # Simulator instruction rate (inst/s)
|
host_inst_rate 172626 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 148134 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 207257 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 97944157 # Simulator tick rate (ticks/s)
|
host_tick_rate 137034779 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 314844 # Number of bytes of host memory used
|
host_mem_usage 322768 # Number of bytes of host memory used
|
||||||
host_seconds 2212.94 # Real time elapsed on the host
|
host_seconds 1581.67 # Real time elapsed on the host
|
||||||
sim_insts 273037857 # Number of instructions simulated
|
sim_insts 273037857 # Number of instructions simulated
|
||||||
sim_ops 327812214 # Number of ops (including micro ops) simulated
|
sim_ops 327812214 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -783,17 +783,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 44377 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.112557 # Nu
|
||||||
sim_ticks 112556618500 # Number of ticks simulated
|
sim_ticks 112556618500 # Number of ticks simulated
|
||||||
final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 95501 # Simulator instruction rate (inst/s)
|
host_inst_rate 125639 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 114659 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 150843 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 39369115 # Simulator tick rate (ticks/s)
|
host_tick_rate 51793233 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 319836 # Number of bytes of host memory used
|
host_mem_usage 327772 # Number of bytes of host memory used
|
||||||
host_seconds 2859.01 # Real time elapsed on the host
|
host_seconds 2173.19 # Real time elapsed on the host
|
||||||
sim_insts 273037220 # Number of instructions simulated
|
sim_insts 273037220 # Number of instructions simulated
|
||||||
sim_ops 327811602 # Number of ops (including micro ops) simulated
|
sim_ops 327811602 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1134,17 +1134,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 32515 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 32515 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.009730 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3216936 99.03% 99.03% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 31609 0.97% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu
|
||||||
sim_ticks 201717314000 # Number of ticks simulated
|
sim_ticks 201717314000 # Number of ticks simulated
|
||||||
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 854590 # Simulator instruction rate (inst/s)
|
host_inst_rate 1265309 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1026030 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1519144 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 631341281 # Simulator tick rate (ticks/s)
|
host_tick_rate 934796791 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 304088 # Number of bytes of host memory used
|
host_mem_usage 311752 # Number of bytes of host memory used
|
||||||
host_seconds 319.51 # Real time elapsed on the host
|
host_seconds 215.79 # Real time elapsed on the host
|
||||||
sim_insts 273037595 # Number of instructions simulated
|
sim_insts 273037595 # Number of instructions simulated
|
||||||
sim_ops 327811950 # Number of ops (including micro ops) simulated
|
sim_ops 327811950 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979
|
||||||
system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
|
system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 348660274 67.44% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 517024352 # Request fanout histogram
|
system.membus.snoop_fanout::total 517024352 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -591,17 +591,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 21079 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.545048 # Nu
|
||||||
sim_ticks 545048444500 # Number of ticks simulated
|
sim_ticks 545048444500 # Number of ticks simulated
|
||||||
final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 131789 # Simulator instruction rate (inst/s)
|
host_inst_rate 177094 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 162250 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 218026 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 112122004 # Simulator tick rate (ticks/s)
|
host_tick_rate 150665678 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 314432 # Number of bytes of host memory used
|
host_mem_usage 323140 # Number of bytes of host memory used
|
||||||
host_seconds 4861.21 # Real time elapsed on the host
|
host_seconds 3617.60 # Real time elapsed on the host
|
||||||
sim_insts 640655085 # Number of instructions simulated
|
sim_insts 640655085 # Number of instructions simulated
|
||||||
sim_ops 788730744 # Number of ops (including micro ops) simulated
|
sim_ops 788730744 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -808,17 +808,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 899017 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu
|
||||||
sim_ticks 395726778500 # Number of ticks simulated
|
sim_ticks 395726778500 # Number of ticks simulated
|
||||||
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1109777 # Simulator instruction rate (inst/s)
|
host_inst_rate 1575908 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1366282 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1940150 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 685499869 # Simulator tick rate (ticks/s)
|
host_tick_rate 973424664 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 303676 # Number of bytes of host memory used
|
host_mem_usage 311080 # Number of bytes of host memory used
|
||||||
host_seconds 577.28 # Real time elapsed on the host
|
host_seconds 406.53 # Real time elapsed on the host
|
||||||
sim_insts 640654411 # Number of instructions simulated
|
sim_insts 640654411 # Number of instructions simulated
|
||||||
sim_ops 788730070 # Number of ops (including micro ops) simulated
|
sim_ops 788730070 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929
|
||||||
system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
|
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 643377899 62.91% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
|
system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -598,17 +598,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 883911 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.057717 # Nu
|
||||||
sim_ticks 57716694500 # Number of ticks simulated
|
sim_ticks 57716694500 # Number of ticks simulated
|
||||||
final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 141604 # Simulator instruction rate (inst/s)
|
host_inst_rate 194770 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 181090 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 249082 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 115249030 # Simulator tick rate (ticks/s)
|
host_tick_rate 158520150 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 314220 # Number of bytes of host memory used
|
host_mem_usage 322420 # Number of bytes of host memory used
|
||||||
host_seconds 500.80 # Real time elapsed on the host
|
host_seconds 364.10 # Real time elapsed on the host
|
||||||
sim_insts 70915128 # Number of instructions simulated
|
sim_insts 70915128 # Number of instructions simulated
|
||||||
sim_ops 90690084 # Number of ops (including micro ops) simulated
|
sim_ops 90690084 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -809,17 +809,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 333867 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 333867 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.033331 # Nu
|
||||||
sim_ticks 33330913000 # Number of ticks simulated
|
sim_ticks 33330913000 # Number of ticks simulated
|
||||||
final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 93420 # Simulator instruction rate (inst/s)
|
host_inst_rate 123947 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 119473 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 158514 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 43913176 # Simulator tick rate (ticks/s)
|
host_tick_rate 58262578 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 317168 # Number of bytes of host memory used
|
host_mem_usage 323704 # Number of bytes of host memory used
|
||||||
host_seconds 759.02 # Real time elapsed on the host
|
host_seconds 572.08 # Real time elapsed on the host
|
||||||
sim_insts 70907630 # Number of instructions simulated
|
sim_insts 70907630 # Number of instructions simulated
|
||||||
sim_ops 90682585 # Number of ops (including micro ops) simulated
|
sim_ops 90682585 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1158,17 +1158,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 151304 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 151304 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.123542 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.123542 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 1073332 87.65% 87.65% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 151292 12.35% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 1073332 87.65% 87.65% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 151292 12.35% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.121265 # Nu
|
||||||
sim_ticks 1121265462500 # Number of ticks simulated
|
sim_ticks 1121265462500 # Number of ticks simulated
|
||||||
final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 175724 # Simulator instruction rate (inst/s)
|
host_inst_rate 238084 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 189316 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 256500 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 127565822 # Simulator tick rate (ticks/s)
|
host_tick_rate 172835636 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 306448 # Number of bytes of host memory used
|
host_mem_usage 314372 # Number of bytes of host memory used
|
||||||
host_seconds 8789.70 # Real time elapsed on the host
|
host_seconds 6487.47 # Real time elapsed on the host
|
||||||
sim_insts 1544563088 # Number of instructions simulated
|
sim_insts 1544563088 # Number of instructions simulated
|
||||||
sim_ops 1664032481 # Number of ops (including micro ops) simulated
|
sim_ops 1664032481 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -816,17 +816,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 12928956 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 12928956 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.771725 # Nu
|
||||||
sim_ticks 771725169000 # Number of ticks simulated
|
sim_ticks 771725169000 # Number of ticks simulated
|
||||||
final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 109963 # Simulator instruction rate (inst/s)
|
host_inst_rate 137392 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 118469 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 148019 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 54942138 # Simulator tick rate (ticks/s)
|
host_tick_rate 68646343 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 305172 # Number of bytes of host memory used
|
host_mem_usage 311812 # Number of bytes of host memory used
|
||||||
host_seconds 14046.14 # Real time elapsed on the host
|
host_seconds 11242.04 # Real time elapsed on the host
|
||||||
sim_insts 1544563024 # Number of instructions simulated
|
sim_insts 1544563024 # Number of instructions simulated
|
||||||
sim_ops 1664032416 # Number of ops (including micro ops) simulated
|
sim_ops 1664032416 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1153,17 +1153,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 1298291 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 1298291 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.056115 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 21838103 94.39% 94.39% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 1298291 5.61% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu
|
||||||
sim_ticks 832017490500 # Number of ticks simulated
|
sim_ticks 832017490500 # Number of ticks simulated
|
||||||
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1379227 # Simulator instruction rate (inst/s)
|
host_inst_rate 1936914 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1485908 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2086731 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 742955189 # Simulator tick rate (ticks/s)
|
host_tick_rate 1043366913 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 295688 # Number of bytes of host memory used
|
host_mem_usage 303348 # Number of bytes of host memory used
|
||||||
host_seconds 1119.88 # Real time elapsed on the host
|
host_seconds 797.44 # Real time elapsed on the host
|
||||||
sim_insts 1544563042 # Number of instructions simulated
|
sim_insts 1544563042 # Number of instructions simulated
|
||||||
sim_ops 1664032434 # Number of ops (including micro ops) simulated
|
sim_ops 1664032434 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063
|
||||||
system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
|
system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 1544565590 71.11% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
|
system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -590,17 +590,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 12813292 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu
|
||||||
sim_ticks 2846007227500 # Number of ticks simulated
|
sim_ticks 2846007227500 # Number of ticks simulated
|
||||||
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1299561 # Simulator instruction rate (inst/s)
|
host_inst_rate 1464727 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2282177 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1229541445 # Simulator tick rate (ticks/s)
|
host_tick_rate 1385807923 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 299440 # Number of bytes of host memory used
|
host_mem_usage 304512 # Number of bytes of host memory used
|
||||||
host_seconds 2314.69 # Real time elapsed on the host
|
host_seconds 2053.68 # Real time elapsed on the host
|
||||||
sim_insts 3008081022 # Number of instructions simulated
|
sim_insts 3008081022 # Number of instructions simulated
|
||||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -35,33 +35,6 @@ system.physmem.bw_write::total 542745211 # Wr
|
||||||
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||||
|
|
@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||||
|
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.882580 # Nu
|
||||||
sim_ticks 5882580398500 # Number of ticks simulated
|
sim_ticks 5882580398500 # Number of ticks simulated
|
||||||
final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 733187 # Simulator instruction rate (inst/s)
|
host_inst_rate 739516 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1152234 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1433815394 # Simulator tick rate (ticks/s)
|
host_tick_rate 1446192754 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 313792 # Number of bytes of host memory used
|
host_mem_usage 314252 # Number of bytes of host memory used
|
||||||
host_seconds 4102.75 # Real time elapsed on the host
|
host_seconds 4067.63 # Real time elapsed on the host
|
||||||
sim_insts 3008081022 # Number of instructions simulated
|
sim_insts 3008081022 # Number of instructions simulated
|
||||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -449,17 +449,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 12811308 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.131767 # Nu
|
||||||
sim_ticks 131767151500 # Number of ticks simulated
|
sim_ticks 131767151500 # Number of ticks simulated
|
||||||
final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 176753 # Simulator instruction rate (inst/s)
|
host_inst_rate 244794 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 186327 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 258052 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 135158895 # Simulator tick rate (ticks/s)
|
host_tick_rate 187187675 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 309748 # Number of bytes of host memory used
|
host_mem_usage 317932 # Number of bytes of host memory used
|
||||||
host_seconds 974.91 # Real time elapsed on the host
|
host_seconds 703.93 # Real time elapsed on the host
|
||||||
sim_insts 172317810 # Number of instructions simulated
|
sim_insts 172317810 # Number of instructions simulated
|
||||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -783,17 +783,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 6517 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.085032 # Nu
|
||||||
sim_ticks 85032044000 # Number of ticks simulated
|
sim_ticks 85032044000 # Number of ticks simulated
|
||||||
final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 98638 # Simulator instruction rate (inst/s)
|
host_inst_rate 135904 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 103981 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 143266 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 48678127 # Simulator tick rate (ticks/s)
|
host_tick_rate 67069129 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 307440 # Number of bytes of host memory used
|
host_mem_usage 314096 # Number of bytes of host memory used
|
||||||
host_seconds 1746.82 # Real time elapsed on the host
|
host_seconds 1267.83 # Real time elapsed on the host
|
||||||
sim_insts 172303022 # Number of instructions simulated
|
sim_insts 172303022 # Number of instructions simulated
|
||||||
sim_ops 181635954 # Number of ops (including micro ops) simulated
|
sim_ops 181635954 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1113,17 +1113,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 2153 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 2153 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011018 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.011018 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 193263 98.90% 98.90% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 2153 1.10% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 193263 98.90% 98.90% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 2153 1.10% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.081225 # Nu
|
||||||
sim_ticks 81224844500 # Number of ticks simulated
|
sim_ticks 81224844500 # Number of ticks simulated
|
||||||
final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 72712 # Simulator instruction rate (inst/s)
|
host_inst_rate 91947 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 121872 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 154111 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 44718419 # Simulator tick rate (ticks/s)
|
host_tick_rate 56548085 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 340792 # Number of bytes of host memory used
|
host_mem_usage 347388 # Number of bytes of host memory used
|
||||||
host_seconds 1816.36 # Real time elapsed on the host
|
host_seconds 1436.39 # Real time elapsed on the host
|
||||||
sim_insts 132071192 # Number of instructions simulated
|
sim_insts 132071192 # Number of instructions simulated
|
||||||
sim_ops 221363384 # Number of ops (including micro ops) simulated
|
sim_ops 221363384 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -944,17 +944,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 299 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 299 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 10459 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 10459 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.869358 # Nu
|
||||||
sim_ticks 1869358498000 # Number of ticks simulated
|
sim_ticks 1869358498000 # Number of ticks simulated
|
||||||
final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1825215 # Simulator instruction rate (inst/s)
|
host_inst_rate 2576820 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1825215 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2576818 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 52491614317 # Simulator tick rate (ticks/s)
|
host_tick_rate 74107088123 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 318168 # Number of bytes of host memory used
|
host_mem_usage 319644 # Number of bytes of host memory used
|
||||||
host_seconds 35.61 # Real time elapsed on the host
|
host_seconds 25.23 # Real time elapsed on the host
|
||||||
sim_insts 65000470 # Number of instructions simulated
|
sim_insts 65000470 # Number of instructions simulated
|
||||||
sim_ops 65000470 # Number of ops (including micro ops) simulated
|
sim_ops 65000470 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -900,17 +900,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5328064
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 1265678 # Request fanout histogram
|
system.membus.snoop_fanout::samples 1287715 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 1265678 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 1287715 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 1265678 # Request fanout histogram
|
system.membus.snoop_fanout::total 1287715 # Request fanout histogram
|
||||||
system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution
|
system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution
|
||||||
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
|
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||||
|
|
@ -932,19 +932,19 @@ system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 243
|
||||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 41895 # Total snoops (count)
|
system.toL2Bus.snoops 41895 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 3873082 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 3895119 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.010775 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 3.010714 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.103240 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.102951 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 3831351 98.92% 98.92% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::3 3853388 98.93% 98.93% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::4 41731 1.07% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3873082 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3895119 # Request fanout histogram
|
||||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
|
||||||
sim_ticks 1829332273500 # Number of ticks simulated
|
sim_ticks 1829332273500 # Number of ticks simulated
|
||||||
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1690642 # Simulator instruction rate (inst/s)
|
host_inst_rate 2059947 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1690641 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2059945 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 51512796649 # Simulator tick rate (ticks/s)
|
host_tick_rate 62765242809 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 313048 # Number of bytes of host memory used
|
host_mem_usage 317596 # Number of bytes of host memory used
|
||||||
host_seconds 35.51 # Real time elapsed on the host
|
host_seconds 29.15 # Real time elapsed on the host
|
||||||
sim_insts 60038341 # Number of instructions simulated
|
sim_insts 60038341 # Number of instructions simulated
|
||||||
sim_ops 60038341 # Number of ops (including micro ops) simulated
|
sim_ops 60038341 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -441,17 +441,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3838716 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3855738 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.010822 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103690 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.103463 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 3796990 98.91% 98.91% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3814012 98.92% 98.92% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 41726 1.08% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3838716 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3855738 # Request fanout histogram
|
||||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||||
|
|
@ -574,17 +574,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 1215692 # Request fanout histogram
|
system.membus.snoop_fanout::samples 1232714 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 1215692 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 1232714 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 1215692 # Request fanout histogram
|
system.membus.snoop_fanout::total 1232714 # Request fanout histogram
|
||||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.962613 # Nu
|
||||||
sim_ticks 1962612686500 # Number of ticks simulated
|
sim_ticks 1962612686500 # Number of ticks simulated
|
||||||
final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1051716 # Simulator instruction rate (inst/s)
|
host_inst_rate 1118839 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 33894179183 # Simulator tick rate (ticks/s)
|
host_tick_rate 36057415911 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 374244 # Number of bytes of host memory used
|
host_mem_usage 319640 # Number of bytes of host memory used
|
||||||
host_seconds 57.90 # Real time elapsed on the host
|
host_seconds 54.43 # Real time elapsed on the host
|
||||||
sim_insts 60898638 # Number of instructions simulated
|
sim_insts 60898638 # Number of instructions simulated
|
||||||
sim_ops 60898638 # Number of ops (including micro ops) simulated
|
sim_ops 60898638 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -610,6 +610,12 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299
|
||||||
system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses
|
system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10834 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17944 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -652,12 +658,12 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578
|
||||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 698758 # number of replacements
|
system.cpu0.icache.tags.replacements 698758 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use
|
||||||
|
|
@ -1011,6 +1017,12 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698
|
||||||
system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses
|
system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses
|
||||||
system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses
|
||||||
system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses
|
system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses
|
||||||
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3218 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3307 # number of overall MSHR uncacheable misses
|
||||||
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -1053,12 +1065,12 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485
|
||||||
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
|
||||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
|
||||||
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
|
||||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760 # average overall mshr uncacheable latency
|
||||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency
|
||||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu1.icache.tags.replacements 315648 # number of replacements
|
system.cpu1.icache.tags.replacements 315648 # number of replacements
|
||||||
system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use
|
system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use
|
||||||
|
|
@ -1539,6 +1551,15 @@ system.l2c.overall_mshr_misses::cpu0.data 387263 # n
|
||||||
system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 14052 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 21251 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1620,15 +1641,15 @@ system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193372.151899 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197977.528090 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193429.087373 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 198730.893483 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209613.424487 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201223.064332 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 196607.584708 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 209300.272150 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 198582.772575 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 292759 # Transaction distribution
|
system.membus.trans_dist::ReadReq 292759 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 292759 # Transaction distribution
|
system.membus.trans_dist::ReadResp 292759 # Transaction distribution
|
||||||
|
|
@ -1655,17 +1676,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 21558 # Total snoops (count)
|
system.membus.snoops 21558 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 597341 # Request fanout histogram
|
system.membus.snoop_fanout::samples 618592 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 618592 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 597341 # Request fanout histogram
|
system.membus.snoop_fanout::total 618592 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks)
|
||||||
|
|
@ -1696,19 +1717,19 @@ system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 202
|
||||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 98552 # Total snoops (count)
|
system.toL2Bus.snoops 98552 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 3276706 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 3.012746 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.112175 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::3 3234942 98.73% 98.73% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::4 41764 1.27% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3276706 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.922414 # Nu
|
||||||
sim_ticks 1922413663500 # Number of ticks simulated
|
sim_ticks 1922413663500 # Number of ticks simulated
|
||||||
final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1122927 # Simulator instruction rate (inst/s)
|
host_inst_rate 912210 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 912209 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 38428929684 # Simulator tick rate (ticks/s)
|
host_tick_rate 31217732593 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 370248 # Number of bytes of host memory used
|
host_mem_usage 318584 # Number of bytes of host memory used
|
||||||
host_seconds 50.03 # Real time elapsed on the host
|
host_seconds 61.58 # Real time elapsed on the host
|
||||||
sim_insts 56174594 # Number of instructions simulated
|
sim_insts 56174594 # Number of instructions simulated
|
||||||
sim_ops 56174594 # Number of ops (including micro ops) simulated
|
sim_ops 56174594 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -586,6 +586,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1374617
|
||||||
system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -622,12 +628,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 928205 # number of replacements
|
system.cpu.icache.tags.replacements 928205 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use
|
||||||
|
|
@ -842,6 +848,12 @@ system.cpu.l2cache.demand_mshr_misses::total 402112
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -887,12 +899,12 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
|
||||||
|
|
@ -911,17 +923,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 41937 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 41937 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3214755 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.012990 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.113233 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3172994 98.70% 98.70% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 41761 1.30% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3214755 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
||||||
|
|
@ -1130,17 +1142,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 431 # Total snoops (count)
|
system.membus.snoops 431 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 559589 # Request fanout histogram
|
system.membus.snoop_fanout::samples 576169 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 576169 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 559589 # Request fanout histogram
|
system.membus.snoop_fanout::total 576169 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
||||||
sim_ticks 2783867052000 # Number of ticks simulated
|
sim_ticks 2783867052000 # Number of ticks simulated
|
||||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 903946 # Simulator instruction rate (inst/s)
|
host_inst_rate 1057273 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1100409 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1287060 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 17625645989 # Simulator tick rate (ticks/s)
|
host_tick_rate 20615299474 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 615176 # Number of bytes of host memory used
|
host_mem_usage 562992 # Number of bytes of host memory used
|
||||||
host_seconds 157.94 # Real time elapsed on the host
|
host_seconds 135.04 # Real time elapsed on the host
|
||||||
sim_insts 142772879 # Number of instructions simulated
|
sim_insts 142772879 # Number of instructions simulated
|
||||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -548,19 +548,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram
|
||||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||||
|
|
@ -694,17 +692,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 359045 # Request fanout histogram
|
system.membus.snoop_fanout::samples 426678 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 359045 # Request fanout histogram
|
system.membus.snoop_fanout::total 426678 # Request fanout histogram
|
||||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
||||||
sim_ticks 2783867052000 # Number of ticks simulated
|
sim_ticks 2783867052000 # Number of ticks simulated
|
||||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1378466 # Simulator instruction rate (inst/s)
|
host_inst_rate 1032026 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1256326 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 26878113924 # Simulator tick rate (ticks/s)
|
host_tick_rate 20123025378 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 614624 # Number of bytes of host memory used
|
host_mem_usage 560940 # Number of bytes of host memory used
|
||||||
host_seconds 103.57 # Real time elapsed on the host
|
host_seconds 138.34 # Real time elapsed on the host
|
||||||
sim_insts 142772879 # Number of instructions simulated
|
sim_insts 142772879 # Number of instructions simulated
|
||||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -548,19 +548,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram
|
||||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||||
|
|
@ -694,17 +692,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 359045 # Request fanout histogram
|
system.membus.snoop_fanout::samples 426678 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 359045 # Request fanout histogram
|
system.membus.snoop_fanout::total 426678 # Request fanout histogram
|
||||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.903548 # Nu
|
||||||
sim_ticks 2903547931500 # Number of ticks simulated
|
sim_ticks 2903547931500 # Number of ticks simulated
|
||||||
final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 732027 # Simulator instruction rate (inst/s)
|
host_inst_rate 571103 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 882601 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 688575 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 18897780106 # Simulator tick rate (ticks/s)
|
host_tick_rate 14743405801 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 614620 # Number of bytes of host memory used
|
host_mem_usage 560940 # Number of bytes of host memory used
|
||||||
host_seconds 153.65 # Real time elapsed on the host
|
host_seconds 196.94 # Real time elapsed on the host
|
||||||
sim_insts 112472279 # Number of instructions simulated
|
sim_insts 112472279 # Number of instructions simulated
|
||||||
sim_ops 135607130 # Number of ops (including micro ops) simulated
|
sim_ops 135607130 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -687,6 +687,12 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 698894
|
||||||
system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles
|
||||||
|
|
@ -735,12 +741,12 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187331.540240 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187331.540240 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163580.847439 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163580.847439 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176173.846783 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176173.846783 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.icache.tags.replacements 1698619 # number of replacements
|
system.cpu.icache.tags.replacements 1698619 # number of replacements
|
||||||
system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use
|
system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use
|
||||||
|
|
@ -809,6 +815,10 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1699137
|
||||||
system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles
|
||||||
|
|
@ -831,10 +841,10 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.l2cache.tags.replacements 89783 # number of replacements
|
system.cpu.l2cache.tags.replacements 89783 # number of replacements
|
||||||
system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use
|
system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use
|
||||||
|
|
@ -1024,6 +1034,14 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1095,14 +1113,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173318.092042 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147983.478586 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150576.987205 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150576.987205 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162634.686771 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149039.616821 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution
|
||||||
|
|
@ -1126,19 +1144,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_si
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 53413 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 53413 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 3338113 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.019032 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.136637 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 3274582 98.10% 98.10% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 63531 1.90% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 3338113 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
|
||||||
|
|
@ -1380,17 +1396,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 498 # Total snoops (count)
|
system.membus.snoops 498 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 319985 # Request fanout histogram
|
system.membus.snoop_fanout::samples 387734 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 387734 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 319985 # Request fanout histogram
|
system.membus.snoop_fanout::total 387734 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
||||||
sim_ticks 2783867052000 # Number of ticks simulated
|
sim_ticks 2783867052000 # Number of ticks simulated
|
||||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1291395 # Simulator instruction rate (inst/s)
|
host_inst_rate 898221 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1572066 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1093441 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 25180347721 # Simulator tick rate (ticks/s)
|
host_tick_rate 17514028577 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 616688 # Number of bytes of host memory used
|
host_mem_usage 560944 # Number of bytes of host memory used
|
||||||
host_seconds 110.56 # Real time elapsed on the host
|
host_seconds 158.95 # Real time elapsed on the host
|
||||||
sim_insts 142772879 # Number of instructions simulated
|
sim_insts 142772879 # Number of instructions simulated
|
||||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -973,17 +973,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 359033 # Request fanout histogram
|
system.membus.snoop_fanout::samples 426666 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 359033 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 426666 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 359033 # Request fanout histogram
|
system.membus.snoop_fanout::total 426666 # Request fanout histogram
|
||||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||||
|
|
@ -1036,18 +1036,16 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 36631 # Total snoops (count)
|
system.toL2Bus.snoops 36631 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 3272324 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 3339957 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.011143 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.020246 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.140841 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 3272336 97.98% 97.98% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 67621 2.02% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 3235860 98.89% 98.89% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 36464 1.11% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3272324 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3339957 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.903641 # Nu
|
||||||
sim_ticks 2903640922500 # Number of ticks simulated
|
sim_ticks 2903640922500 # Number of ticks simulated
|
||||||
final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 705602 # Simulator instruction rate (inst/s)
|
host_inst_rate 541770 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 850741 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 653210 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 18218787173 # Simulator tick rate (ticks/s)
|
host_tick_rate 13988619879 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 616688 # Number of bytes of host memory used
|
host_mem_usage 561968 # Number of bytes of host memory used
|
||||||
host_seconds 159.38 # Real time elapsed on the host
|
host_seconds 207.57 # Real time elapsed on the host
|
||||||
sim_insts 112456119 # Number of instructions simulated
|
sim_insts 112456119 # Number of instructions simulated
|
||||||
sim_ops 135587804 # Number of ops (including micro ops) simulated
|
sim_ops 135587804 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -755,6 +755,15 @@ system.cpu0.dcache.demand_mshr_misses::total 699973
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses
|
||||||
system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses
|
system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31142 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58736 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -824,15 +833,15 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181268.674931 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193354.234894 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187312.231071 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143051.398911 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191019.922007 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163557.186345 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 162020.531131 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192348.149366 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176152.180945 # average overall mshr uncacheable latency
|
||||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu0.icache.tags.replacements 1701384 # number of replacements
|
system.cpu0.icache.tags.replacements 1701384 # number of replacements
|
||||||
system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use
|
system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use
|
||||||
|
|
@ -924,6 +933,10 @@ system.cpu0.icache.demand_mshr_misses::total 1701902
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses
|
||||||
system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses
|
system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -955,10 +968,10 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency
|
||||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency
|
||||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||||
|
|
@ -1662,6 +1675,17 @@ system.l2c.overall_mshr_misses::cpu1.dtb.walker 4
|
||||||
system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses
|
||||||
system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses
|
system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.ReadReq_mshr_uncacheable::total 40164 # number of ReadReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses
|
||||||
|
system.l2c.overall_mshr_uncacheable_misses::total 67758 # number of overall MSHR uncacheable misses
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles
|
||||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles
|
||||||
|
|
@ -1769,17 +1793,17 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency
|
||||||
system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency
|
system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167244.026591 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179351.891094 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147970.993925 # average ReadReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 130046.334979 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178017.166836 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150553.109372 # average WriteReq mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148509.396818 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 178776.626841 # average overall mshr uncacheable latency
|
||||||
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 149022.543464 # average overall mshr uncacheable latency
|
||||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.membus.trans_dist::ReadReq 70492 # Transaction distribution
|
system.membus.trans_dist::ReadReq 70492 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadResp 70492 # Transaction distribution
|
system.membus.trans_dist::ReadResp 70492 # Transaction distribution
|
||||||
|
|
@ -1810,17 +1834,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 498 # Total snoops (count)
|
system.membus.snoops 498 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 313389 # Request fanout histogram
|
system.membus.snoop_fanout::samples 381147 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 313389 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 381147 100.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 313389 # Request fanout histogram
|
system.membus.snoop_fanout::total 381147 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
||||||
|
|
@ -1886,19 +1910,17 @@ system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2
|
||||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes)
|
system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.toL2Bus.snoops 52269 # Total snoops (count)
|
system.toL2Bus.snoops 52269 # Total snoops (count)
|
||||||
system.toL2Bus.snoop_fanout::samples 3285526 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::samples 3353284 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::mean 3.011103 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::mean 1.021354 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::stdev 0.104785 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::stdev 0.144561 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::1 3281678 97.86% 97.86% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::2 71606 2.14% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::3 3249046 98.89% 98.89% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::4 36480 1.11% 100.00% # Request fanout histogram
|
|
||||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.toL2Bus.snoop_fanout::total 3285526 # Request fanout histogram
|
system.toL2Bus.snoop_fanout::total 3353284 # Request fanout histogram
|
||||||
system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks)
|
system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks)
|
||||||
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks)
|
system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu
|
||||||
sim_ticks 5112152301500 # Number of ticks simulated
|
sim_ticks 5112152301500 # Number of ticks simulated
|
||||||
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1049184 # Simulator instruction rate (inst/s)
|
host_inst_rate 1219492 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 2147909 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2496566 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 26808985343 # Simulator tick rate (ticks/s)
|
host_tick_rate 31160731508 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 640900 # Number of bytes of host memory used
|
host_mem_usage 598628 # Number of bytes of host memory used
|
||||||
host_seconds 190.69 # Real time elapsed on the host
|
host_seconds 164.06 # Real time elapsed on the host
|
||||||
sim_insts 200066731 # Number of instructions simulated
|
sim_insts 200066731 # Number of instructions simulated
|
||||||
sim_ops 409580371 # Number of ops (including micro ops) simulated
|
sim_ops 409580371 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -368,8 +368,8 @@ system.cpu.l2cache.ReadReq_hits::cpu.data 1275199 # n
|
||||||
system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
|
||||||
system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits
|
||||||
|
|
@ -387,8 +387,8 @@ system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32163 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.data 32163 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::total 45524 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::total 45524 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1807 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses::total 1807 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134650 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 134650 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 134650 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::total 134650 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
||||||
|
|
@ -427,8 +427,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001724
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987972 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987972 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
|
||||||
|
|
@ -471,20 +471,20 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 48002 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 49698 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4017264 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 17890240 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011855 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 3.002757 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.108231 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.052432 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3969641 98.81% 98.81% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::3 17840921 99.72% 99.72% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 47623 1.19% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::4 49319 0.28% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4017264 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 17890240 # Request fanout histogram
|
||||||
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
||||||
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
||||||
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
||||||
|
|
@ -596,8 +596,8 @@ system.membus.trans_dist::WriteResp 13943 # Tr
|
||||||
system.membus.trans_dist::Writeback 144777 # Transaction distribution
|
system.membus.trans_dist::Writeback 144777 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeReq 2545 # Transaction distribution
|
system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeResp 2093 # Transaction distribution
|
system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExReq 134369 # Transaction distribution
|
system.membus.trans_dist::ReadExReq 134369 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExResp 134364 # Transaction distribution
|
system.membus.trans_dist::ReadExResp 134364 # Transaction distribution
|
||||||
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||||
|
|
@ -606,11 +606,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav
|
||||||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462529 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462531 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205089 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205091 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141913 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141913 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 141913 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 141913 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 28350394 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 28350396 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
|
@ -621,17 +621,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034560
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 6034560 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 6034560 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 49257977 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 49257977 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 374838 # Request fanout histogram
|
system.membus.snoop_fanout::samples 14247815 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.010910 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 374838 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 14246119 99.99% 99.99% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 374838 # Request fanout histogram
|
system.membus.snoop_fanout::total 14247815 # Request fanout histogram
|
||||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.184750 # Nu
|
||||||
sim_ticks 5184749789500 # Number of ticks simulated
|
sim_ticks 5184749789500 # Number of ticks simulated
|
||||||
final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 858252 # Simulator instruction rate (inst/s)
|
host_inst_rate 812427 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1566083 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 34581252938 # Simulator tick rate (ticks/s)
|
host_tick_rate 32734861616 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 653812 # Number of bytes of host memory used
|
host_mem_usage 599680 # Number of bytes of host memory used
|
||||||
host_seconds 149.93 # Real time elapsed on the host
|
host_seconds 158.39 # Real time elapsed on the host
|
||||||
sim_insts 128677191 # Number of instructions simulated
|
sim_insts 128677191 # Number of instructions simulated
|
||||||
sim_ops 248045844 # Number of ops (including micro ops) simulated
|
sim_ops 248045844 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -55,7 +55,7 @@ system.physmem.bytesReadSys 9871616 # To
|
||||||
system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side
|
system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side
|
||||||
system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue
|
system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue
|
||||||
system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one
|
system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one
|
||||||
system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write
|
system.physmem.neitherReadNorWriteReqs 1619 # Number of requests that are neither read nor write
|
||||||
system.physmem.perBankRdBursts::0 9927 # Per bank write bursts
|
system.physmem.perBankRdBursts::0 9927 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::1 9220 # Per bank write bursts
|
system.physmem.perBankRdBursts::1 9220 # Per bank write bursts
|
||||||
system.physmem.perBankRdBursts::2 9906 # Per bank write bursts
|
system.physmem.perBankRdBursts::2 9906 # Per bank write bursts
|
||||||
|
|
@ -259,12 +259,12 @@ system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Wr
|
||||||
system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads
|
||||||
system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
|
system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
|
||||||
system.physmem.totQLat 1425327951 # Total ticks spent queuing
|
system.physmem.totQLat 1425306951 # Total ticks spent queuing
|
||||||
system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM
|
system.physmem.totMemAccLat 4315600701 # Total ticks spent from burst creation until serviced by the DRAM
|
||||||
system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers
|
system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers
|
||||||
system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst
|
system.physmem.avgQLat 9246.29 # Average queueing delay per DRAM burst
|
||||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||||
system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst
|
system.physmem.avgMemAccLat 27996.29 # Average memory access latency per DRAM burst
|
||||||
system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
|
system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
|
||||||
system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s
|
system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s
|
||||||
system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
|
system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
|
||||||
|
|
@ -286,14 +286,14 @@ system.physmem_0.preEnergy 115846500 # En
|
||||||
system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ)
|
system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ)
|
||||||
system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ)
|
system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ)
|
||||||
system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ)
|
system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ)
|
||||||
system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ)
|
system.physmem_0.actBackEnergy 133930593495 # Energy for active background per rank (pJ)
|
||||||
system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ)
|
system.physmem_0.preBackEnergy 2993365419750 # Energy for precharge background per rank (pJ)
|
||||||
system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ)
|
system.physmem_0.totalEnergy 3467346235185 # Total energy per rank (pJ)
|
||||||
system.physmem_0.averagePower 668.758961 # Core power per rank (mW)
|
system.physmem_0.averagePower 668.758961 # Core power per rank (mW)
|
||||||
system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states
|
system.physmem_0.memoryStateTime::IDLE 4979642480610 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states
|
system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states
|
system.physmem_0.memoryStateTime::ACT 31977087390 # Time in different power states
|
||||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||||
system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ)
|
system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ)
|
||||||
system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ)
|
system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ)
|
||||||
|
|
@ -411,12 +411,12 @@ system.cpu.dcache.overall_misses::cpu.data 1634737 #
|
||||||
system.cpu.dcache.overall_misses::total 1634737 # number of overall misses
|
system.cpu.dcache.overall_misses::total 1634737 # number of overall misses
|
||||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles
|
system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149973597 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles
|
system.cpu.dcache.WriteReq_miss_latency::total 12149973597 # number of WriteReq miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::cpu.data 24985949815 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles
|
system.cpu.dcache.demand_miss_latency::total 24985949815 # number of demand (read+write) miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::cpu.data 24985949815 # number of overall miss cycles
|
||||||
system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles
|
system.cpu.dcache.overall_miss_latency::total 24985949815 # number of overall miss cycles
|
||||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses)
|
system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses)
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses)
|
||||||
|
|
@ -439,12 +439,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.075037
|
||||||
system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses
|
system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.737593 # average WriteReq miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.737593 # average WriteReq miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.785581 # average overall miss latency
|
||||||
system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency
|
system.cpu.dcache.demand_avg_miss_latency::total 20287.785581 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.385082 # average overall miss latency
|
||||||
system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency
|
system.cpu.dcache.overall_avg_miss_latency::total 15284.385082 # average overall miss latency
|
||||||
system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked
|
system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked
|
||||||
|
|
@ -473,16 +473,22 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1222124
|
||||||
system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses
|
system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses
|
||||||
system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses
|
system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117329359 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117329359 # number of WriteReq MSHR miss cycles
|
||||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles
|
||||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586088141 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles
|
system.cpu.dcache.demand_mshr_miss_latency::total 22586088141 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213385641 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles
|
system.cpu.dcache.overall_mshr_miss_latency::total 28213385641 # number of overall MSHR miss cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles
|
||||||
|
|
@ -501,20 +507,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602
|
||||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.793240 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.793240 # average WriteReq mshr miss latency
|
||||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency
|
||||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18481.011862 # average overall mshr miss latency
|
||||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18481.011862 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.423474 # average overall mshr miss latency
|
||||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.423474 # average overall mshr miss latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 164165.785509 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164165.785509 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186353.370221 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186353.370221 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 164690.242353 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 164690.242353 # average overall mshr uncacheable latency
|
||||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements
|
system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements
|
||||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use
|
||||||
|
|
@ -632,12 +638,12 @@ system.cpu.icache.demand_misses::cpu.inst 794984 # n
|
||||||
system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses
|
system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses
|
||||||
system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses
|
system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses
|
||||||
system.cpu.icache.overall_misses::total 794984 # number of overall misses
|
system.cpu.icache.overall_misses::total 794984 # number of overall misses
|
||||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253068237 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles
|
system.cpu.icache.ReadReq_miss_latency::total 11253068237 # number of ReadReq miss cycles
|
||||||
system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency::cpu.inst 11253068237 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles
|
system.cpu.icache.demand_miss_latency::total 11253068237 # number of demand (read+write) miss cycles
|
||||||
system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency::cpu.inst 11253068237 # number of overall miss cycles
|
||||||
system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles
|
system.cpu.icache.overall_miss_latency::total 11253068237 # number of overall miss cycles
|
||||||
system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses)
|
system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses
|
system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses
|
||||||
|
|
@ -650,12 +656,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.005454
|
||||||
system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses
|
system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses
|
||||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses
|
||||||
system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses
|
system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.087696 # average ReadReq miss latency
|
||||||
system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14155.087696 # average ReadReq miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency
|
||||||
system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency
|
system.cpu.icache.demand_avg_miss_latency::total 14155.087696 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency
|
||||||
system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency
|
system.cpu.icache.overall_avg_miss_latency::total 14155.087696 # average overall miss latency
|
||||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -670,24 +676,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 794984
|
||||||
system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses
|
system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses
|
||||||
system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses
|
system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055806763 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 10055806763 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055806763 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles
|
system.cpu.icache.demand_mshr_miss_latency::total 10055806763 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055806763 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles
|
system.cpu.icache.overall_mshr_miss_latency::total 10055806763 # number of overall MSHR miss cycles
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses
|
system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses
|
system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.068111 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.068111 # average ReadReq mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency
|
||||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency
|
||||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency
|
||||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements
|
system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements
|
||||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use
|
||||||
|
|
@ -812,8 +818,8 @@ system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # n
|
||||||
system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits
|
system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits
|
||||||
system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits
|
||||||
system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits
|
system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits
|
system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits
|
system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits
|
||||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits
|
||||||
|
|
@ -830,8 +836,8 @@ system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses
|
||||||
system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses
|
system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1358 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses
|
system.cpu.l2cache.UpgradeReq_misses::total 1358 # number of UpgradeReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses
|
system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses
|
||||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||||
|
|
@ -843,21 +849,21 @@ system.cpu.l2cache.overall_misses::cpu.inst 12937 #
|
||||||
system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses
|
system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses
|
||||||
system.cpu.l2cache.overall_misses::total 154732 # number of overall misses
|
system.cpu.l2cache.overall_misses::total 154732 # number of overall misses
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049428751 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles
|
system.cpu.l2cache.ReadReq_miss_latency::total 3391229783 # number of ReadReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21365858 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 21365858 # number of UpgradeReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1049428751 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles
|
system.cpu.l2cache.demand_miss_latency::total 12043716754 # number of demand (read+write) miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1049428751 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles
|
||||||
system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles
|
system.cpu.l2cache.overall_miss_latency::total 12043716754 # number of overall miss cycles
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses)
|
||||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses)
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses)
|
||||||
|
|
@ -883,8 +889,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811231 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811231 # miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses
|
||||||
|
|
@ -896,21 +902,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274
|
||||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses
|
system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81118.400788 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.219079 # average ReadReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15733.326951 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15733.326951 # average UpgradeReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency
|
||||||
system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency
|
system.cpu.l2cache.demand_avg_miss_latency::total 77835.979332 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency
|
||||||
system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency
|
system.cpu.l2cache.overall_avg_miss_latency::total 77835.979332 # average overall miss latency
|
||||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||||
|
|
@ -925,8 +931,8 @@ system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses
|
system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1358 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1358 # number of UpgradeReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses
|
||||||
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
||||||
|
|
@ -937,22 +943,28 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses
|
||||||
system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses
|
system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses
|
||||||
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887274749 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872160717 # number of ReadReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24705840 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24705840 # number of UpgradeReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887274749 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles
|
system.cpu.l2cache.demand_mshr_miss_latency::total 10108385746 # number of demand (read+write) MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887274749 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles
|
system.cpu.l2cache.overall_mshr_miss_latency::total 10108385746 # number of overall MSHR miss cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles
|
||||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles
|
||||||
|
|
@ -963,8 +975,8 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811231 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811231 # mshr miss rate for UpgradeReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses
|
||||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses
|
||||||
|
|
@ -976,27 +988,27 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68584.273711 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507 # average ReadReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18192.812960 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18192.812960 # average UpgradeReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625 # average ReadReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173260.311871 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871 # average WriteReq mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604 # average overall mshr uncacheable latency
|
||||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||||
system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution
|
||||||
|
|
@ -1008,6 +1020,7 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # T
|
||||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution
|
||||||
system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution
|
system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution
|
||||||
|
system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes)
|
||||||
|
|
@ -1018,27 +1031,27 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 54167 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 55819 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 4616997 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 3.010670 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.102742 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::3 4567735 98.93% 98.93% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::4 49262 1.07% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 4616997 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer1.occupancy 3047835587 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||||
system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
@ -1249,8 +1262,8 @@ system.membus.trans_dist::WriteResp 13916 # Tr
|
||||||
system.membus.trans_dist::Writeback 126970 # Transaction distribution
|
system.membus.trans_dist::Writeback 126970 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
||||||
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
|
system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
|
||||||
system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution
|
system.membus.trans_dist::UpgradeResp 1637 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExReq 112993 # Transaction distribution
|
system.membus.trans_dist::ReadExReq 112993 # Transaction distribution
|
||||||
system.membus.trans_dist::ReadExResp 112993 # Transaction distribution
|
system.membus.trans_dist::ReadExResp 112993 # Transaction distribution
|
||||||
system.membus.trans_dist::MessageReq 1652 # Transaction distribution
|
system.membus.trans_dist::MessageReq 1652 # Transaction distribution
|
||||||
|
|
@ -1259,11 +1272,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav
|
||||||
system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392332 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569788 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes)
|
system.membus.pkt_count::total 1714479 # Packet count per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
|
@ -1274,28 +1287,28 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120
|
||||||
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 1583 # Total snoops (count)
|
system.membus.snoops 1583 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 331203 # Request fanout histogram
|
system.membus.snoop_fanout::samples 921584 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
system.membus.snoop_fanout::mean 1.001793 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.042301 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 919932 99.82% 99.82% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 331203 # Request fanout histogram
|
system.membus.snoop_fanout::total 921584 # Request fanout histogram
|
||||||
system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks)
|
system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks)
|
system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks)
|
system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks)
|
system.membus.reqLayer3.occupancy 1034075968 # Layer occupancy (ticks)
|
||||||
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks)
|
system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks)
|
system.membus.respLayer2.occupancy 2159262414 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||||
system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks)
|
system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks)
|
||||||
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu
|
||||||
sim_ticks 200409271000 # Number of ticks simulated
|
sim_ticks 200409271000 # Number of ticks simulated
|
||||||
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 10268281 # Simulator instruction rate (inst/s)
|
host_inst_rate 20752053 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 10268278 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 20752044 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 3928851236 # Simulator tick rate (ticks/s)
|
host_tick_rate 7940152278 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 533084 # Number of bytes of host memory used
|
host_mem_usage 485568 # Number of bytes of host memory used
|
||||||
host_seconds 51.01 # Real time elapsed on the host
|
host_seconds 25.24 # Real time elapsed on the host
|
||||||
sim_insts 523780905 # Number of instructions simulated
|
sim_insts 523780905 # Number of instructions simulated
|
||||||
sim_ops 523780905 # Number of ops (including micro ops) simulated
|
sim_ops 523780905 # Number of ops (including micro ops) simulated
|
||||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -244,16 +244,16 @@ drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 572
|
||||||
drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes)
|
drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes)
|
||||||
drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes)
|
drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes)
|
||||||
drivesys.membus.snoops 0 # Total snoops (count)
|
drivesys.membus.snoops 0 # Total snoops (count)
|
||||||
drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram
|
drivesys.membus.snoop_fanout::samples 27247410 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram
|
drivesys.membus.snoop_fanout::mean 0.786764 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram
|
drivesys.membus.snoop_fanout::stdev 0.409593 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram
|
drivesys.membus.snoop_fanout::0 5810141 21.32% 21.32% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram
|
drivesys.membus.snoop_fanout::1 21437269 78.68% 100.00% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram
|
drivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram
|
||||||
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
||||||
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
|
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
|
||||||
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
|
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
|
||||||
|
|
@ -551,16 +551,16 @@ testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 572613
|
||||||
testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes)
|
testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes)
|
||||||
testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes)
|
testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes)
|
||||||
testsys.membus.snoops 0 # Total snoops (count)
|
testsys.membus.snoops 0 # Total snoops (count)
|
||||||
testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram
|
testsys.membus.snoop_fanout::samples 28885173 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram
|
testsys.membus.snoop_fanout::mean 0.784032 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram
|
testsys.membus.snoop_fanout::stdev 0.411493 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram
|
testsys.membus.snoop_fanout::0 6238286 21.60% 21.60% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram
|
testsys.membus.snoop_fanout::1 22646887 78.40% 100.00% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram
|
testsys.membus.snoop_fanout::total 28885173 # Request fanout histogram
|
||||||
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
||||||
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
|
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
|
||||||
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
|
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
|
||||||
|
|
@ -619,11 +619,11 @@ sim_seconds 0.000407 # Nu
|
||||||
sim_ticks 407341500 # Number of ticks simulated
|
sim_ticks 407341500 # Number of ticks simulated
|
||||||
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 5226750004 # Simulator instruction rate (inst/s)
|
host_inst_rate 10415397218 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 5225740576 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 10413013630 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 4062718512 # Simulator tick rate (ticks/s)
|
host_tick_rate 8095289719 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 533084 # Number of bytes of host memory used
|
host_mem_usage 485568 # Number of bytes of host memory used
|
||||||
host_seconds 0.10 # Real time elapsed on the host
|
host_seconds 0.05 # Real time elapsed on the host
|
||||||
sim_insts 523853183 # Number of instructions simulated
|
sim_insts 523853183 # Number of instructions simulated
|
||||||
sim_ops 523853183 # Number of ops (including micro ops) simulated
|
sim_ops 523853183 # Number of ops (including micro ops) simulated
|
||||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -838,16 +838,16 @@ drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 1
|
||||||
drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes)
|
drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes)
|
||||||
drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes)
|
drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes)
|
||||||
drivesys.membus.snoops 0 # Total snoops (count)
|
drivesys.membus.snoops 0 # Total snoops (count)
|
||||||
drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram
|
drivesys.membus.snoop_fanout::samples 52004 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram
|
drivesys.membus.snoop_fanout::mean 0.788439 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram
|
drivesys.membus.snoop_fanout::stdev 0.408419 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram
|
drivesys.membus.snoop_fanout::0 11002 21.16% 21.16% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram
|
drivesys.membus.snoop_fanout::1 41002 78.84% 100.00% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram
|
drivesys.membus.snoop_fanout::total 52004 # Request fanout histogram
|
||||||
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
||||||
drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA
|
drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA
|
||||||
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
|
|
@ -1092,16 +1092,16 @@ testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 1163
|
||||||
testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes)
|
testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes)
|
||||||
testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes)
|
testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes)
|
||||||
testsys.membus.snoops 0 # Total snoops (count)
|
testsys.membus.snoops 0 # Total snoops (count)
|
||||||
testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram
|
testsys.membus.snoop_fanout::samples 51975 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram
|
testsys.membus.snoop_fanout::mean 0.788360 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram
|
testsys.membus.snoop_fanout::stdev 0.408475 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram
|
testsys.membus.snoop_fanout::0 11000 21.16% 21.16% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram
|
testsys.membus.snoop_fanout::1 40975 78.84% 100.00% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
testsys.membus.snoop_fanout::total 51694 # Request fanout histogram
|
testsys.membus.snoop_fanout::total 51975 # Request fanout histogram
|
||||||
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
||||||
testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
|
testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
|
||||||
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||||
|
|
|
||||||
|
|
@ -744,17 +744,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
||||||
sim_ticks 17398000 # Number of ticks simulated
|
sim_ticks 17398000 # Number of ticks simulated
|
||||||
final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 32773 # Simulator instruction rate (inst/s)
|
host_inst_rate 57922 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 38377 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 67825 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 124135140 # Simulator tick rate (ticks/s)
|
host_tick_rate 219380871 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 303432 # Number of bytes of host memory used
|
host_mem_usage 310080 # Number of bytes of host memory used
|
||||||
host_seconds 0.14 # Real time elapsed on the host
|
host_seconds 0.08 # Real time elapsed on the host
|
||||||
sim_insts 4592 # Number of instructions simulated
|
sim_insts 4592 # Number of instructions simulated
|
||||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -1162,19 +1162,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -1074,17 +1074,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 64 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 64 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1.127237 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 439 87.28% 87.28% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 64 12.72% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
||||||
sim_ticks 2695000 # Number of ticks simulated
|
sim_ticks 2695000 # Number of ticks simulated
|
||||||
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 88081 # Simulator instruction rate (inst/s)
|
host_inst_rate 803078 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 103121 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 938405 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 51657705 # Simulator tick rate (ticks/s)
|
host_tick_rate 469266934 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 292672 # Number of bytes of host memory used
|
host_mem_usage 299548 # Number of bytes of host memory used
|
||||||
host_seconds 0.05 # Real time elapsed on the host
|
host_seconds 0.01 # Real time elapsed on the host
|
||||||
sim_insts 4592 # Number of instructions simulated
|
sim_insts 4592 # Number of instructions simulated
|
||||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -347,16 +347,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139
|
||||||
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
|
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 6532 # Request fanout histogram
|
system.membus.snoop_fanout::total 6532 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
||||||
sim_ticks 2695000 # Number of ticks simulated
|
sim_ticks 2695000 # Number of ticks simulated
|
||||||
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 99386 # Simulator instruction rate (inst/s)
|
host_inst_rate 829930 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 116351 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 969708 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 58281162 # Simulator tick rate (ticks/s)
|
host_tick_rate 484799424 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 291652 # Number of bytes of host memory used
|
host_mem_usage 298800 # Number of bytes of host memory used
|
||||||
host_seconds 0.05 # Real time elapsed on the host
|
host_seconds 0.01 # Real time elapsed on the host
|
||||||
sim_insts 4592 # Number of instructions simulated
|
sim_insts 4592 # Number of instructions simulated
|
||||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -228,16 +228,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139
|
||||||
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
|
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 6532 # Request fanout histogram
|
system.membus.snoop_fanout::total 6532 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -549,17 +549,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -896,17 +896,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu
|
||||||
sim_ticks 5615000 # Number of ticks simulated
|
sim_ticks 5615000 # Number of ticks simulated
|
||||||
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 365210 # Simulator instruction rate (inst/s)
|
host_inst_rate 96804 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 661016 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 175298 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 380445830 # Simulator tick rate (ticks/s)
|
host_tick_rate 100934348 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 292780 # Number of bytes of host memory used
|
host_mem_usage 242164 # Number of bytes of host memory used
|
||||||
host_seconds 0.01 # Real time elapsed on the host
|
host_seconds 0.06 # Real time elapsed on the host
|
||||||
sim_insts 5381 # Number of instructions simulated
|
sim_insts 5381 # Number of instructions simulated
|
||||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -35,33 +35,6 @@ system.physmem.bw_write::total 1266607302 # Wr
|
||||||
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.membus.trans_dist::ReadReq 7917 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadResp 7917 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteReq 935 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteResp 935 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 8852 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 8852 # Request fanout histogram
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||||
|
|
@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 9748 # Class of executed instruction
|
system.cpu.op_class::total 9748 # Class of executed instruction
|
||||||
|
system.membus.trans_dist::ReadReq 7917 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 7917 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteReq 935 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteResp 935 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 8852 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0.775418 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 8852 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
|
||||||
sim_ticks 28358500 # Number of ticks simulated
|
sim_ticks 28358500 # Number of ticks simulated
|
||||||
final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 312703 # Simulator instruction rate (inst/s)
|
host_inst_rate 97635 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 566020 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 176805 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1645401799 # Simulator tick rate (ticks/s)
|
host_tick_rate 514168344 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 307640 # Number of bytes of host memory used
|
host_mem_usage 251928 # Number of bytes of host memory used
|
||||||
host_seconds 0.02 # Real time elapsed on the host
|
host_seconds 0.06 # Real time elapsed on the host
|
||||||
sim_insts 5381 # Number of instructions simulated
|
sim_insts 5381 # Number of instructions simulated
|
||||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -423,17 +423,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu
|
||||||
sim_ticks 54141000500 # Number of ticks simulated
|
sim_ticks 54141000500 # Number of ticks simulated
|
||||||
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1362402 # Simulator instruction rate (inst/s)
|
host_inst_rate 1892320 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1369187 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1901744 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 814125846 # Simulator tick rate (ticks/s)
|
host_tick_rate 1130787212 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 428768 # Number of bytes of host memory used
|
host_mem_usage 435148 # Number of bytes of host memory used
|
||||||
host_seconds 66.50 # Real time elapsed on the host
|
host_seconds 47.88 # Real time elapsed on the host
|
||||||
sim_insts 90602408 # Number of instructions simulated
|
sim_insts 90602408 # Number of instructions simulated
|
||||||
sim_ops 91053639 # Number of ops (including micro ops) simulated
|
sim_ops 91053639 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736
|
||||||
system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
|
system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 107830771 79.86% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 135031171 # Request fanout histogram
|
system.membus.snoop_fanout::total 135031171 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -589,17 +589,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 1889731 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
|
||||||
sim_ticks 168950040000 # Number of ticks simulated
|
sim_ticks 168950040000 # Number of ticks simulated
|
||||||
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1180838 # Simulator instruction rate (inst/s)
|
host_inst_rate 1204419 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2120788 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1262766288 # Simulator tick rate (ticks/s)
|
host_tick_rate 1287982979 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 436624 # Number of bytes of host memory used
|
host_mem_usage 383444 # Number of bytes of host memory used
|
||||||
host_seconds 133.79 # Real time elapsed on the host
|
host_seconds 131.17 # Real time elapsed on the host
|
||||||
sim_insts 157988548 # Number of instructions simulated
|
sim_insts 157988548 # Number of instructions simulated
|
||||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -35,33 +35,6 @@ system.physmem.bw_write::total 1439319677 # Wr
|
||||||
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 339915363 # Request fanout histogram
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||||
|
|
@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 278192465 # Class of executed instruction
|
system.cpu.op_class::total 278192465 # Class of executed instruction
|
||||||
|
system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 339915363 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu
|
||||||
sim_ticks 48960011500 # Number of ticks simulated
|
sim_ticks 48960011500 # Number of ticks simulated
|
||||||
final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1111911 # Simulator instruction rate (inst/s)
|
host_inst_rate 1547474 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1421979 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1979004 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 767686935 # Simulator tick rate (ticks/s)
|
host_tick_rate 1068409192 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 303468 # Number of bytes of host memory used
|
host_mem_usage 311136 # Number of bytes of host memory used
|
||||||
host_seconds 63.78 # Real time elapsed on the host
|
host_seconds 45.83 # Real time elapsed on the host
|
||||||
sim_insts 70913182 # Number of instructions simulated
|
sim_insts 70913182 # Number of instructions simulated
|
||||||
sim_ops 90688137 # Number of ops (including micro ops) simulated
|
sim_ops 90688137 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556
|
||||||
system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 120930619 # Request fanout histogram
|
system.membus.snoop_fanout::samples 120930619 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 78145069 64.62% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 120930619 # Request fanout histogram
|
system.membus.snoop_fanout::total 120930619 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -597,17 +597,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu
|
||||||
sim_ticks 99596491500 # Number of ticks simulated
|
sim_ticks 99596491500 # Number of ticks simulated
|
||||||
final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1304038 # Simulator instruction rate (inst/s)
|
host_inst_rate 1968226 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1374666 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 2074827 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 753711187 # Simulator tick rate (ticks/s)
|
host_tick_rate 1137600357 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 298984 # Number of bytes of host memory used
|
host_mem_usage 306644 # Number of bytes of host memory used
|
||||||
host_seconds 132.14 # Real time elapsed on the host
|
host_seconds 87.55 # Real time elapsed on the host
|
||||||
sim_insts 172317410 # Number of instructions simulated
|
sim_insts 172317410 # Number of instructions simulated
|
||||||
sim_ops 181650342 # Number of ops (including micro ops) simulated
|
sim_ops 181650342 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601
|
||||||
system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes)
|
system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
system.membus.snoop_fanout::samples 230024467 # Request fanout histogram
|
system.membus.snoop_fanout::samples 230024467 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram
|
system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
|
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 189860052 82.54% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.membus.snoop_fanout::total 230024467 # Request fanout histogram
|
system.membus.snoop_fanout::total 230024467 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -585,17 +585,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 4856 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
|
||||||
sim_ticks 131393279000 # Number of ticks simulated
|
sim_ticks 131393279000 # Number of ticks simulated
|
||||||
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 1264426 # Simulator instruction rate (inst/s)
|
host_inst_rate 851639 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 1427424 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1257935779 # Simulator tick rate (ticks/s)
|
host_tick_rate 847267215 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 324376 # Number of bytes of host memory used
|
host_mem_usage 272248 # Number of bytes of host memory used
|
||||||
host_seconds 104.45 # Real time elapsed on the host
|
host_seconds 155.08 # Real time elapsed on the host
|
||||||
sim_insts 132071193 # Number of instructions simulated
|
sim_insts 132071193 # Number of instructions simulated
|
||||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -35,33 +35,6 @@ system.physmem.bw_write::total 759720678 # Wr
|
||||||
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
|
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
|
||||||
system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
|
|
||||||
system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
|
|
||||||
system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
|
|
||||||
system.membus.snoops 0 # Total snoops (count)
|
|
||||||
system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
||||||
system.membus.snoop_fanout::total 250692103 # Request fanout histogram
|
|
||||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||||
|
|
@ -125,5 +98,30 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl
|
||||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||||
system.cpu.op_class::total 221363385 # Class of executed instruction
|
system.cpu.op_class::total 221363385 # Class of executed instruction
|
||||||
|
system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
|
||||||
|
system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
|
||||||
|
system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
|
||||||
|
system.membus.snoops 0 # Total snoops (count)
|
||||||
|
system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
|
system.membus.snoop_fanout::total 250692103 # Request fanout histogram
|
||||||
|
|
||||||
---------- End Simulation Statistics ----------
|
---------- End Simulation Statistics ----------
|
||||||
|
|
|
||||||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
|
||||||
sim_ticks 250953957500 # Number of ticks simulated
|
sim_ticks 250953957500 # Number of ticks simulated
|
||||||
final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||||
host_inst_rate 722726 # Simulator instruction rate (inst/s)
|
host_inst_rate 582427 # Simulator instruction rate (inst/s)
|
||||||
host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s)
|
host_op_rate 976201 # Simulator op (including micro ops) rate (op/s)
|
||||||
host_tick_rate 1373280924 # Simulator tick rate (ticks/s)
|
host_tick_rate 1106694320 # Simulator tick rate (ticks/s)
|
||||||
host_mem_usage 338728 # Number of bytes of host memory used
|
host_mem_usage 282016 # Number of bytes of host memory used
|
||||||
host_seconds 182.74 # Real time elapsed on the host
|
host_seconds 226.76 # Real time elapsed on the host
|
||||||
sim_insts 132071193 # Number of instructions simulated
|
sim_insts 132071193 # Number of instructions simulated
|
||||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||||
|
|
@ -446,17 +446,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
||||||
system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
|
system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||||
system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
||||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
|
system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
|
||||||
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
|
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
|
||||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue