1938 lines
228 KiB
Plaintext
1938 lines
228 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.903641 # Number of seconds simulated
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sim_ticks 2903640922500 # Number of ticks simulated
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final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 541770 # Simulator instruction rate (inst/s)
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host_op_rate 653210 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 13988619879 # Simulator tick rate (ticks/s)
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host_mem_usage 561968 # Number of bytes of host memory used
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host_seconds 207.57 # Real time elapsed on the host
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sim_insts 112456119 # Number of instructions simulated
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sim_ops 135587804 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 582564 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 3808480 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 602944 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 5025476 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10021000 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 582564 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 602944 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1185508 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7434688 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7452212 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 17556 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 60026 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 9421 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 78524 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 165551 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 116167 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 120548 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 200632 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1311622 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 207651 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 1730750 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3451184 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 200632 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 207651 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 408283 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2560471 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2566506 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2560471 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 200632 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 1317655 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 207651 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 1730753 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6017690 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 165551 # Number of read requests accepted
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system.physmem.writeReqs 156772 # Number of write requests accepted
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system.physmem.readBursts 165551 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 156772 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 10588736 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue
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system.physmem.bytesWritten 8522624 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 10021000 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 9770548 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 23601 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4489 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9899 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9526 # Per bank write bursts
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system.physmem.perBankRdBursts::2 9759 # Per bank write bursts
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system.physmem.perBankRdBursts::3 9793 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18999 # Per bank write bursts
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system.physmem.perBankRdBursts::5 10033 # Per bank write bursts
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system.physmem.perBankRdBursts::6 10462 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10803 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9925 # Per bank write bursts
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system.physmem.perBankRdBursts::9 10243 # Per bank write bursts
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system.physmem.perBankRdBursts::10 9858 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9250 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9247 # Per bank write bursts
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system.physmem.perBankRdBursts::13 9475 # Per bank write bursts
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system.physmem.perBankRdBursts::14 9028 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9149 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8258 # Per bank write bursts
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system.physmem.perBankWrBursts::1 8244 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8572 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8149 # Per bank write bursts
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system.physmem.perBankWrBursts::4 8563 # Per bank write bursts
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system.physmem.perBankWrBursts::5 8536 # Per bank write bursts
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system.physmem.perBankWrBursts::6 8718 # Per bank write bursts
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system.physmem.perBankWrBursts::7 9117 # Per bank write bursts
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system.physmem.perBankWrBursts::8 8657 # Per bank write bursts
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system.physmem.perBankWrBursts::9 8771 # Per bank write bursts
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system.physmem.perBankWrBursts::10 8610 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7990 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7949 # Per bank write bursts
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system.physmem.perBankWrBursts::13 7964 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7531 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7537 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 32 # Number of times write queue was full causing retry
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system.physmem.totGap 2903640597500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 9558 # Read request sizes (log2)
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system.physmem.readPktSize::3 14 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 155979 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 4381 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 152391 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 164623 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 272 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 190 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 183 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 177 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 172 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 163 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1852 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5181 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5271 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5453 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5489 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5477 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5778 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 6926 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 6108 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 7269 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 6043 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6071 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 7760 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6386 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5989 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 1272 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 2214 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 2179 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 1803 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 1883 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 2499 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 1797 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1557 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1747 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 1424 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 1124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 1057 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 786 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 394 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 308 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 312 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 128 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 140 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 152 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 57876 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 330.211072 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 191.290947 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 346.940345 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 20714 35.79% 35.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 14256 24.63% 60.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5208 9.00% 69.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3123 5.40% 74.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2440 4.22% 79.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1489 2.57% 81.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1071 1.85% 83.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1111 1.92% 85.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8464 14.62% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 57876 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5262 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 31.441087 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 579.786182 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 5260 99.96% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5262 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5262 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 25.307108 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.699141 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 47.946490 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::0-15 45 0.86% 0.86% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-31 4897 93.06% 93.92% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-47 79 1.50% 95.42% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::48-63 16 0.30% 95.72% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::64-79 14 0.27% 95.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::80-95 19 0.36% 96.35% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::96-111 31 0.59% 96.94% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::112-127 27 0.51% 97.45% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::128-143 13 0.25% 97.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-159 8 0.15% 97.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-175 3 0.06% 97.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-191 23 0.44% 98.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-207 14 0.27% 98.61% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-223 10 0.19% 98.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-239 3 0.06% 98.86% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::240-255 3 0.06% 98.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-271 3 0.06% 98.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::272-287 4 0.08% 99.05% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::288-303 8 0.15% 99.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::304-319 4 0.08% 99.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::320-335 3 0.06% 99.33% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::336-351 5 0.10% 99.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::352-367 8 0.15% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::368-383 1 0.02% 99.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::384-399 1 0.02% 99.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::416-431 1 0.02% 99.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::432-447 1 0.02% 99.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::464-479 1 0.02% 99.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::496-511 3 0.06% 99.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::512-527 1 0.02% 99.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::528-543 3 0.06% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::544-559 3 0.06% 99.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::560-575 1 0.02% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::608-623 1 0.02% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::672-687 1 0.02% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::688-703 1 0.02% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::720-735 2 0.04% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5262 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1437662314 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4539831064 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 827245000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 8689.46 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 27439.46 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 3.65 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.94 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 3.45 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 10.50 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 136363 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 104375 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 78.38 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 9008480.93 # Average gap between requests
|
|
system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 229453560 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 125197875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 696337200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 441657360 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 86953063950 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1665909868500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1944007265085 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 669.506799 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 2771232360210 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 96958940000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 35449523540 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 208089000 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 113540625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 594157200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 421258320 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 84877892595 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1667730194250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1943596818630 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 669.365444 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 2774279366726 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 96958940000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 32402517024 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.walker.walks 6899 # Table walker walks requested
|
|
system.cpu0.dtb.walker.walksShort 6899 # Table walker walks initiated with short descriptors
|
|
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2220 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4679 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.dtb.walker.walkWaitTime::samples 6899 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::0 6899 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::total 6899 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::samples 5841 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::stdev 6688.963614 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::0-16383 4458 76.32% 76.32% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1381 23.64% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::total 5841 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walkPageSizes::4K 3645 62.40% 62.40% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::1M 2196 37.60% 100.00% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::total 5841 # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6899 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5841 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5841 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin::total 12740 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 12462635 # DTB read hits
|
|
system.cpu0.dtb.read_misses 5988 # DTB read misses
|
|
system.cpu0.dtb.write_hits 9832923 # DTB write hits
|
|
system.cpu0.dtb.write_misses 911 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 4660 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 940 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 12468623 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 9833834 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 22295558 # DTB hits
|
|
system.cpu0.dtb.misses 6899 # DTB misses
|
|
system.cpu0.dtb.accesses 22302457 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.walks 3577 # Table walker walks requested
|
|
system.cpu0.itb.walker.walksShort 3577 # Table walker walks initiated with short descriptors
|
|
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 835 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2742 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu0.itb.walker.walkWaitTime::samples 3577 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0 3577 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 3577 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::stdev 6704.748097 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::0-8191 633 23.22% 23.22% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1408 51.65% 74.87% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::16384-24575 683 25.06% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 1891 69.37% 69.37% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::1M 835 30.63% 100.00% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::total 2726 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3577 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3577 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2726 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 6303 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 58414032 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3577 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2760 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 58417609 # ITB inst accesses
|
|
system.cpu0.itb.hits 58414032 # DTB hits
|
|
system.cpu0.itb.misses 3577 # DTB misses
|
|
system.cpu0.itb.accesses 58417609 # DTB accesses
|
|
system.cpu0.numCycles 2904051621 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 56844590 # Number of instructions committed
|
|
system.cpu0.committedOps 68476862 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 60556147 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5891 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 5072041 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 7664286 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 60556147 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5891 # number of float instructions
|
|
system.cpu0.num_int_register_reads 110162183 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 41899351 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 4609 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1284 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 247668564 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 26017746 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 22952183 # number of memory refs
|
|
system.cpu0.num_load_insts 12628752 # Number of load instructions
|
|
system.cpu0.num_store_insts 10323431 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 2690582406.498001 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 213469214.501999 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.073507 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.926493 # Percentage of idle cycles
|
|
system.cpu0.Branches 13135796 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2207 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 47055843 67.15% 67.15% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 59396 0.08% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.24% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 4431 0.01% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.25% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 12628752 18.02% 85.27% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 10323431 14.73% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 70074060 # Class of executed instruction
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 3032 # number of quiesce instructions executed
|
|
system.cpu0.dcache.tags.replacements 821716 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.827808 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 43234238 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 822228 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 52.581812 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 1008982250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 377.484524 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 134.343284 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.737274 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.262389 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 177115546 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 177115546 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 11742107 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 11368313 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 23110420 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 9438605 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 9386535 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 18825140 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200385 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191808 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 392193 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230728 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212742 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 443470 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239351 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220930 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 21180712 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 20754848 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 41935560 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 21381097 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 20946656 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 42327753 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 202379 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 199779 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 402158 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 143306 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 155169 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 298475 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 60388 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58192 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 118580 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11633 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 10971 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 22604 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 345685 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 354948 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 700633 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 406073 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 413140 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 819213 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2998718242 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2978169130 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5976887372 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5523492960 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6886936529 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 12410429489 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144593750 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 135344000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 279937750 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 164000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 8522211202 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 9865105659 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 18387316861 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 8522211202 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 9865105659 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 18387316861 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11944486 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 11568092 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 23512578 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9581911 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 9541704 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 19123615 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 260773 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 250000 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 510773 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 242361 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 223713 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 466074 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 239353 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 220930 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 21526397 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 21109796 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 42636193 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 21787170 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 21359796 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 43146966 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016943 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017270 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.017104 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014956 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016262 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.015608 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.231573 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.232768 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232158 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047999 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049041 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048499 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016059 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016814 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.016433 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018638 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019342 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.018987 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14817.338963 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14907.318237 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14862.037736 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38543.347522 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44383.456290 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41579.460554 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12429.618327 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12336.523562 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12384.434171 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24653.112522 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27793.101127 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 26243.863565 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20986.894480 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23878.360021 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 22445.098968 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 687030 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 687030 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 373 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 660 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7066 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7026 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14092 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 373 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 373 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202092 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199406 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 401498 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 143306 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155169 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 298475 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 59468 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 57033 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 116501 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4567 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 3945 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8512 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 345398 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 354575 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 699973 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31142 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58736 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5284681040 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6621405971 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11906087011 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 749127008 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 719245636 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1468372644 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 55884250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 49619250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 105503500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 161000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7972531040 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9293189221 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 17265720261 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8721658048 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10012434857 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 18734092905 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2822172000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3011105500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5833277500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2259926000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2253271000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4513197000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5082098000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5264376500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10346474500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016919 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017238 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017076 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014956 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016262 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015608 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228045 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228132 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228088 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018844 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.017634 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018263 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016045 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016797 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018583 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019270 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13349.090780 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36876.900060 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42672.221713 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39889.729495 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12597.144817 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12611.043361 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12603.948842 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12236.533830 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.756654 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181268.674931 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193354.234894 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187312.231071 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143051.398911 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191019.922007 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163557.186345 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 162020.531131 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192348.149366 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176152.180945 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1701384 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 113852033 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1701896 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 66.897174 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 25697074250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 399.197143 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 111.536926 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.779682 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.217846 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.997527 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 117255837 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 117255837 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 57557381 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 56294652 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 113852033 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 57557381 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 56294652 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 113852033 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 57557381 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 56294652 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 113852033 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 856651 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 845251 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1701902 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 856651 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 845251 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1701902 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 856651 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 845251 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1701902 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730914498 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11646451999 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 23377366497 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 11730914498 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 11646451999 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 23377366497 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 11730914498 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 11646451999 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 23377366497 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 58414032 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 57139903 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 115553935 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 58414032 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 57139903 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 115553935 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 58414032 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 57139903 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 115553935 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014665 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014793 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014728 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014665 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014793 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.014728 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014665 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014793 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.014728 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13736.023870 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13736.023870 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856651 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 845251 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 1701902 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 856651 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 845251 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 1701902 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10442855002 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10375133501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 20817988503 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10442855002 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10375133501 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 20817988503 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 677067750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 677067750 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014728 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.014728 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.014728 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 6646 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksShort 6646 # Table walker walks initiated with short descriptors
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1848 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4797 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 6645 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 6645 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 6645 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::samples 5540 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::stdev 6654.820556 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::0-8191 1371 24.75% 24.75% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2761 49.84% 74.58% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1405 25.36% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::total 5540 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walksPending::samples -586099820 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::mean 2.706592 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 1000233500 -170.66% -170.66% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::1 -1586333320 270.66% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total -586099820 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 3714 67.05% 67.05% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::1M 1825 32.95% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 5539 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6646 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6646 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5539 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5539 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 12185 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 12057381 # DTB read hits
|
|
system.cpu1.dtb.read_misses 5757 # DTB read misses
|
|
system.cpu1.dtb.write_hits 9774636 # DTB write hits
|
|
system.cpu1.dtb.write_misses 889 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 4087 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 1001 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 205 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 12063138 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 9775525 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 21832017 # DTB hits
|
|
system.cpu1.dtb.misses 6646 # DTB misses
|
|
system.cpu1.dtb.accesses 21838663 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 3230 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksShort 3230 # Table walker walks initiated with short descriptors
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 673 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu1.itb.walker.walkWaitTime::samples 3230 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 3230 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 3230 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::samples 2426 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::stdev 6275.492791 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::2048-4095 541 22.30% 22.30% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.74% 50.04% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::12288-14335 619 25.52% 75.56% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::20480-22527 528 21.76% 97.32% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::22528-24575 65 2.68% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::total 2426 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walksPending::samples 1000198000 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 1000198000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total 1000198000 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 1753 72.26% 72.26% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::1M 673 27.74% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 2426 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3230 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3230 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2426 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2426 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 5656 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 57139903 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 3230 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 2427 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 57143133 # ITB inst accesses
|
|
system.cpu1.itb.hits 57139903 # DTB hits
|
|
system.cpu1.itb.misses 3230 # DTB misses
|
|
system.cpu1.itb.accesses 57143133 # DTB accesses
|
|
system.cpu1.numCycles 2903230224 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 55611529 # Number of instructions committed
|
|
system.cpu1.committedOps 67110942 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 59336824 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 5270 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 4819801 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 7566653 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 59336824 # number of integer instructions
|
|
system.cpu1.num_fp_insts 5270 # number of float instructions
|
|
system.cpu1.num_int_register_reads 107900734 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 40745080 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 3840 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 1432 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 242074272 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 25879956 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 22456627 # number of memory refs
|
|
system.cpu1.num_load_insts 12214155 # Number of load instructions
|
|
system.cpu1.num_store_insts 10242472 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 2696428184.778518 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 206802039.221482 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.071232 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.928768 # Percentage of idle cycles
|
|
system.cpu1.Branches 12781357 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 130 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 46119057 67.20% 67.20% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 54779 0.08% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 4036 0.01% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.28% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 12214155 17.80% 85.08% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 10242472 14.92% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 68634629 # Class of executed instruction
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 198848287 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36807005 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36424 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.134606 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 299121172000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 1.134606 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328122 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 234 # number of overall misses
|
|
system.iocache.overall_misses::total 234 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 29267377 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 29267377 # number of ReadReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6633096905 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 6633096905 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 29267377 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 29267377 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 29267377 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 29267377 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 125074.260684 # average ReadReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 125074.260684 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 125074.260684 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 22198 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3387 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6.553882 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16965377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 16965377 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4749438915 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4749438915 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 16965377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 16965377 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 16965377 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 16965377 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72501.611111 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 72501.611111 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131113.044252 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131113.044252 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 86345 # number of replacements
|
|
system.l2c.tags.tagsinuse 64916.534496 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 2772933 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 151598 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 18.291356 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 50295.187878 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.860187 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965052 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 4502.634002 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2814.628972 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.894234 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 5158.115832 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 2140.248339 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.767444 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.068705 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.042948 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.078707 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.032658 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.990548 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65248 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 6724 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 56346 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 26318997 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 26318997 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 6505 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 3514 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 848098 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 260151 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 6217 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 3258 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 835810 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 254237 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 2217790 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 687030 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 687030 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 87471 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 80339 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 167810 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 6505 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 3514 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 848098 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 347622 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 6217 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 3258 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 835810 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 334576 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2385600 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 6505 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 3514 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 848098 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 347622 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 6217 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 3258 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 835810 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 334576 # number of overall hits
|
|
system.l2c.overall_hits::total 2385600 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 8541 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 5976 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 9421 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 6147 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 30094 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1338 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2703 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 54481 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 73452 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 127933 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 8541 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 60457 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 9421 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 79599 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 158027 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 8541 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 60457 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 9421 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 79599 # number of overall misses
|
|
system.l2c.overall_misses::total 158027 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 261750 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 166000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 681157002 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 494631258 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 330000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 753847500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 510531136 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 2440924646 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 341989 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 434486 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 776475 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 159000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 4180870378 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 5579789336 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 9760659714 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 261750 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 681157002 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 4675501636 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 330000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 753847500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 6090320472 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 12201584360 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 261750 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 681157002 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 4675501636 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 330000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 753847500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 6090320472 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 12201584360 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 6508 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 3516 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 856639 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 266127 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 6221 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 3258 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 845231 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 260384 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2247884 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 687030 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 687030 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1354 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1378 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2732 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 141952 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 153791 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 295743 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 6508 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 3516 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 856639 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 408079 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 6221 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 3258 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 845231 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 414175 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2543627 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 6508 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 3516 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 856639 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 408079 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 6221 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 3258 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 845231 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 414175 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2543627 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000569 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.009970 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.022455 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.011146 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.023607 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::total 0.013388 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988183 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990566 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.989385 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.383799 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.477609 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.432582 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for demand accesses
|
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system.l2c.demand_miss_rate::cpu0.itb.walker 0.000569 # miss rate for demand accesses
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|
system.l2c.demand_miss_rate::cpu0.inst 0.009970 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.148150 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for demand accesses
|
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system.l2c.demand_miss_rate::cpu1.inst 0.011146 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.192187 # miss rate for demand accesses
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system.l2c.demand_miss_rate::total 0.062127 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu0.itb.walker 0.000569 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.009970 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu0.data 0.148150 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.011146 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.192187 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.062127 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87250 # average ReadReq miss latency
|
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system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadReq miss latency
|
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system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79751.434492 # average ReadReq miss latency
|
|
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system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80017.779429 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 83053.706849 # average ReadReq miss latency
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|
system.l2c.ReadReq_avg_miss_latency::total 81110.010168 # average ReadReq miss latency
|
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system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 255.597160 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 318.304762 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 287.264151 # average UpgradeReq miss latency
|
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system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
|
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system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76739.971329 # average ReadExReq miss latency
|
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system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75965.111039 # average ReadExReq miss latency
|
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system.l2c.ReadExReq_avg_miss_latency::total 76295.089727 # average ReadExReq miss latency
|
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system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency
|
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system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
|
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system.l2c.demand_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency
|
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system.l2c.demand_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency
|
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system.l2c.demand_avg_miss_latency::total 77212.023009 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency
|
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system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
|
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system.l2c.overall_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency
|
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system.l2c.overall_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency
|
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system.l2c.overall_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 77212.023009 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
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system.l2c.cache_copies 0 # number of cache copies performed
|
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system.l2c.writebacks::writebacks 79977 # number of writebacks
|
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system.l2c.writebacks::total 79977 # number of writebacks
|
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|
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|
|
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|
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|
|
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system.l2c.ReadReq_mshr_misses::total 30094 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::cpu0.data 1338 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 2703 # number of UpgradeReq MSHR misses
|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses
|
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system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
|
|
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|
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|
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system.l2c.ReadReq_mshr_uncacheable::total 40164 # number of ReadReq MSHR uncacheable
|
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|
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|
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|
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system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 135000 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2793047000 # number of ReadReq MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::total 5943107000 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2054472000 # number of WriteReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2099890500 # number of WriteReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::total 4154362500 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::total 10097469500 # number of overall MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for ReadReq accesses
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|
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|
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system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for ReadReq accesses
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|
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system.l2c.ReadReq_mshr_miss_rate::total 0.013388 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988183 # mshr miss rate for UpgradeReq accesses
|
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|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.989385 # mshr miss rate for UpgradeReq accesses
|
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system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
|
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|
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|
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|
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|
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|
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|
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|
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|
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system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for demand accesses
|
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system.l2c.demand_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for demand accesses
|
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|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for overall accesses
|
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system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for overall accesses
|
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|
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system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for overall accesses
|
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|
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system.l2c.overall_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for overall accesses
|
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|
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average ReadReq mshr miss latency
|
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784 # average ReadReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency
|
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average ReadReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827 # average ReadReq mshr miss latency
|
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system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697 # average ReadReq mshr miss latency
|
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504 # average UpgradeReq mshr miss latency
|
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531 # average UpgradeReq mshr miss latency
|
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency
|
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
|
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845 # average ReadExReq mshr miss latency
|
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167244.026591 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179351.891094 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147970.993925 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 130046.334979 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178017.166836 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150553.109372 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148509.396818 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 178776.626841 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 149022.543464 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 70492 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 70492 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27594 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27594 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 116167 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4489 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4491 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 126147 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 126147 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 429068 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 536678 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 645565 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15156092 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 15319481 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 498 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 381147 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 381147 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 381147 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 1721500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 960656101 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 947025657 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 37465995 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.toL2Bus.trans_dist::ReadReq 2303937 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2303837 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 687030 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateReq 36246 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2732 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2734 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 295743 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 295743 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3421816 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2454612 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18880 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35749 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 5931057 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108955768 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96785921 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 52269 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3353284 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.021354 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.144561 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 3281678 97.86% 97.86% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 71606 2.14% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3353284 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 2567253247 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1309775845 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 12106000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 23020250 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|