CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
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3 changed files with 6 additions and 1 deletions
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@ -143,6 +143,9 @@ let {{
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case MISCREG_L2LATENCY:
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return new WarnUnimplemented(
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isRead ? "mrc l2latency" : "mcr l2latency", machInst);
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case MISCREG_CRN15:
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return new WarnUnimplemented(
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isRead ? "mrc crn15" : "mcr crn15", machInst);
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// Write only.
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case MISCREG_TLBIALLIS:
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@ -463,7 +463,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
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break;
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case 15:
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// Implementation defined
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break;
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return MISCREG_CRN15;
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}
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// Unrecognized register
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return NUM_MISCREGS;
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@ -196,6 +196,7 @@ namespace ArmISA
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MISCREG_ISR,
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MISCREG_FCEIDR,
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MISCREG_L2LATENCY,
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MISCREG_CRN15,
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MISCREG_CP15_END,
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@ -249,6 +250,7 @@ namespace ArmISA
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"dccmvau",
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"nsacr",
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"vbar", "mvbar", "isr", "fceidr", "l2latency",
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"crn15",
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"nop", "raz"
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};
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