diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 4a9200504..54482864a 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -143,6 +143,9 @@ let {{
           case MISCREG_L2LATENCY:
             return new WarnUnimplemented(
                     isRead ? "mrc l2latency" : "mcr l2latency", machInst);
+          case MISCREG_CRN15:
+            return new WarnUnimplemented(
+                    isRead ? "mrc crn15" : "mcr crn15", machInst);
 
             // Write only.
           case MISCREG_TLBIALLIS:
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 1fecaa38d..db097c653 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -463,7 +463,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
         break;
       case 15:
         // Implementation defined
-        break;
+        return MISCREG_CRN15;
     }
     // Unrecognized register
     return NUM_MISCREGS;
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f99748622..5e5735de7 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -196,6 +196,7 @@ namespace ArmISA
         MISCREG_ISR,
         MISCREG_FCEIDR,
         MISCREG_L2LATENCY,
+        MISCREG_CRN15,
 
 
         MISCREG_CP15_END,
@@ -249,6 +250,7 @@ namespace ArmISA
         "dccmvau",
         "nsacr",
         "vbar", "mvbar", "isr", "fceidr", "l2latency",
+        "crn15",
         "nop", "raz"
     };