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mem: Rename SimpleDRAM to a more suitable DRAMCtrl

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This patch renames the not-so-simple SimpleDRAM to a more suitable
DRAMCtrl. The name change is intended to ensure that we do not send
the wrong message (although the "simple" in SimpleDRAM was originally
intended as in cleverly simple, or elegant).

As the DRAM controller modelling work is being presented at ISPASS'14
our hope is that a broader audience will use the model in the future.

--HG--
rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py
rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc
rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
This commit is contained in:
Andreas Hansson 2014-03-23 11:12:12 -04:00
parent 3dd1587afc
commit 7c18691db1
6 changed files with 78 additions and 78 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
configs/common/MemConfig.py
View file

@ -160,7 +160,7 @@ def config_mem(options, system):
ctrl = cls() ctrl = cls()
# Only do this for DRAMs # Only do this for DRAMs
if issubclass(cls, m5.objects.SimpleDRAM): if issubclass(cls, m5.objects.DRAMCtrl):
# Inform each controller how many channels to account # Inform each controller how many channels to account
# for # for
ctrl.channels = nbr_mem_ctrls ctrl.channels = nbr_mem_ctrls

4
configs/dram/sweep.py
View file

@ -86,8 +86,8 @@ MemConfig.config_mem(options, system)
# the following assumes that we are using the native DRAM # the following assumes that we are using the native DRAM
# controller, check to be sure # controller, check to be sure
if not isinstance(system.mem_ctrls[0], m5.objects.SimpleDRAM): if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
fatal("This script assumes the memory is a SimpleDRAM subclass") fatal("This script assumes the memory is a DRAMCtrl subclass")
# for now the generator assumes a single rank # for now the generator assumes a single rank
system.mem_ctrls[0].ranks_per_channel = 1 system.mem_ctrls[0].ranks_per_channel = 1

24
src/mem/SimpleDRAM.py → src/mem/DRAMCtrl.py
View file

@ -59,13 +59,13 @@ class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
class PageManage(Enum): vals = ['open', 'open_adaptive', 'close', class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
'close_adaptive'] 'close_adaptive']
# SimpleDRAM is a single-channel single-ported DRAM controller model # DRAMCtrl is a single-channel single-ported DRAM controller model
# that aims to model the most important system-level performance # that aims to model the most important system-level performance
# effects of a DRAM without getting into too much detail of the DRAM # effects of a DRAM without getting into too much detail of the DRAM
# itself. # itself.
class SimpleDRAM(AbstractMemory): class DRAMCtrl(AbstractMemory):
type = 'SimpleDRAM' type = 'DRAMCtrl'
cxx_header = "mem/simple_dram.hh" cxx_header = "mem/dram_ctrl.hh"
# single-ported on the system interface side, instantiate with a # single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports # bus in front of the controller for multiple ports
@ -137,7 +137,7 @@ class SimpleDRAM(AbstractMemory):
# it is easier to also evaluate SDR memories like WideIO. # it is easier to also evaluate SDR memories like WideIO.
# This parameter has to account for burst length. # This parameter has to account for burst length.
# Read/Write requests with data size larger than one full burst are broken # Read/Write requests with data size larger than one full burst are broken
# down into multiple requests in the SimpleDRAM controller # down into multiple requests in the controller
tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
# time taken to complete one refresh cycle (N rows in all banks) # time taken to complete one refresh cycle (N rows in all banks)
@ -166,7 +166,7 @@ class SimpleDRAM(AbstractMemory):
# A single DDR3 x64 interface (one command and address bus), with # A single DDR3 x64 interface (one command and address bus), with
# default timings based on DDR3-1600 4 Gbit parts in an 8x8 # default timings based on DDR3-1600 4 Gbit parts in an 8x8
# configuration, which would amount to 4 Gbyte of memory. # configuration, which would amount to 4 Gbyte of memory.
class DDR3_1600_x64(SimpleDRAM): class DDR3_1600_x64(DRAMCtrl):
# 8x8 configuration, 8 devices each with an 8-bit interface # 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8 device_bus_width = 8
@ -222,7 +222,7 @@ class DDR3_1600_x64(SimpleDRAM):
# to be manually set, depending on size of the memory to be # to be manually set, depending on size of the memory to be
# simulated. By default DRAMSim2 has 2048MB of memory with a single # simulated. By default DRAMSim2 has 2048MB of memory with a single
# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 # rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
class DDR3_1333_x64_DRAMSim2(SimpleDRAM): class DDR3_1333_x64_DRAMSim2(DRAMCtrl):
# 8x8 configuration, 8 devices each with an 8-bit interface # 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8 device_bus_width = 8
@ -268,7 +268,7 @@ class DDR3_1333_x64_DRAMSim2(SimpleDRAM):
# A single LPDDR2-S4 x32 interface (one command/address bus), with # A single LPDDR2-S4 x32 interface (one command/address bus), with
# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 # default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
# configuration. # configuration.
class LPDDR2_S4_1066_x32(SimpleDRAM): class LPDDR2_S4_1066_x32(DRAMCtrl):
# 1x32 configuration, 1 device with a 32-bit interface # 1x32 configuration, 1 device with a 32-bit interface
device_bus_width = 32 device_bus_width = 32
@ -302,7 +302,7 @@ class LPDDR2_S4_1066_x32(SimpleDRAM):
# 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
# Note this is a BL8 DDR device. # Note this is a BL8 DDR device.
# Requests larger than 32 bytes are broken down into multiple requests # Requests larger than 32 bytes are broken down into multiple requests
# in the SimpleDRAM controller # in the controller
tBURST = '7.5ns' tBURST = '7.5ns'
# LPDDR2-S4, 4 Gbit # LPDDR2-S4, 4 Gbit
@ -321,7 +321,7 @@ class LPDDR2_S4_1066_x32(SimpleDRAM):
# A single WideIO x128 interface (one command and address bus), with # A single WideIO x128 interface (one command and address bus), with
# default timings based on an estimated WIO-200 8 Gbit part. # default timings based on an estimated WIO-200 8 Gbit part.
class WideIO_200_x128(SimpleDRAM): class WideIO_200_x128(DRAMCtrl):
# 1x128 configuration, 1 device with a 128-bit interface # 1x128 configuration, 1 device with a 128-bit interface
device_bus_width = 128 device_bus_width = 128
@ -370,7 +370,7 @@ class WideIO_200_x128(SimpleDRAM):
# A single LPDDR3 x32 interface (one command/address bus), with # A single LPDDR3 x32 interface (one command/address bus), with
# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 # default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
# configuration # configuration
class LPDDR3_1600_x32(SimpleDRAM): class LPDDR3_1600_x32(DRAMCtrl):
# 1x32 configuration, 1 device with a 32-bit interface # 1x32 configuration, 1 device with a 32-bit interface
device_bus_width = 32 device_bus_width = 32
@ -403,7 +403,7 @@ class LPDDR3_1600_x32(SimpleDRAM):
# 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
# Note this is a BL8 DDR device. # Note this is a BL8 DDR device.
# Requests larger than 32 bytes are broken down into multiple requests # Requests larger than 32 bytes are broken down into multiple requests
# in the SimpleDRAM controller # in the controller
tBURST = '5ns' tBURST = '5ns'
# LPDDR3, 4 Gb # LPDDR3, 4 Gb

4
src/mem/SConscript
View file

@ -40,15 +40,16 @@ SimObject('AbstractMemory.py')
SimObject('AddrMapper.py') SimObject('AddrMapper.py')
SimObject('Bridge.py') SimObject('Bridge.py')
SimObject('Bus.py') SimObject('Bus.py')
SimObject('DRAMCtrl.py')
SimObject('MemObject.py') SimObject('MemObject.py')
SimObject('SimpleMemory.py') SimObject('SimpleMemory.py')
SimObject('SimpleDRAM.py')
Source('abstract_mem.cc') Source('abstract_mem.cc')
Source('addr_mapper.cc') Source('addr_mapper.cc')
Source('bridge.cc') Source('bridge.cc')
Source('bus.cc') Source('bus.cc')
Source('coherent_bus.cc') Source('coherent_bus.cc')
Source('dram_ctrl.cc')
Source('mem_object.cc') Source('mem_object.cc')
Source('mport.cc') Source('mport.cc')
Source('noncoherent_bus.cc') Source('noncoherent_bus.cc')
@ -59,7 +60,6 @@ Source('tport.cc')
Source('port_proxy.cc') Source('port_proxy.cc')
Source('simple_mem.cc') Source('simple_mem.cc')
Source('physical.cc') Source('physical.cc')
Source('simple_dram.cc')
if env['TARGET_ISA'] != 'null': if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc') Source('fs_translating_port_proxy.cc')

90
src/mem/simple_dram.cc → src/mem/dram_ctrl.cc
View file

@ -42,16 +42,16 @@
* Neha Agarwal * Neha Agarwal
*/ */
#include "base/trace.hh"
#include "base/bitfield.hh" #include "base/bitfield.hh"
#include "debug/Drain.hh" #include "base/trace.hh"
#include "debug/DRAM.hh" #include "debug/DRAM.hh"
#include "mem/simple_dram.hh" #include "debug/Drain.hh"
#include "mem/dram_ctrl.hh"
#include "sim/system.hh" #include "sim/system.hh"
using namespace std; using namespace std;
SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) : DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
AbstractMemory(p), AbstractMemory(p),
port(name() + ".port", *this), port(name() + ".port", *this),
retryRdReq(false), retryWrReq(false), retryRdReq(false), retryWrReq(false),
@ -133,17 +133,17 @@ SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) :
} }
void void
SimpleDRAM::init() DRAMCtrl::init()
{ {
if (!port.isConnected()) { if (!port.isConnected()) {
fatal("SimpleDRAM %s is unconnected!\n", name()); fatal("DRAMCtrl %s is unconnected!\n", name());
} else { } else {
port.sendRangeChange(); port.sendRangeChange();
} }
} }
void void
SimpleDRAM::startup() DRAMCtrl::startup()
{ {
// update the start tick for the precharge accounting to the // update the start tick for the precharge accounting to the
// current tick // current tick
@ -157,7 +157,7 @@ SimpleDRAM::startup()
} }
Tick Tick
SimpleDRAM::recvAtomic(PacketPtr pkt) DRAMCtrl::recvAtomic(PacketPtr pkt)
{ {
DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
@ -174,7 +174,7 @@ SimpleDRAM::recvAtomic(PacketPtr pkt)
} }
bool bool
SimpleDRAM::readQueueFull(unsigned int neededEntries) const DRAMCtrl::readQueueFull(unsigned int neededEntries) const
{ {
DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n",
readBufferSize, readQueue.size() + respQueue.size(), readBufferSize, readQueue.size() + respQueue.size(),
@ -185,15 +185,15 @@ SimpleDRAM::readQueueFull(unsigned int neededEntries) const
} }
bool bool
SimpleDRAM::writeQueueFull(unsigned int neededEntries) const DRAMCtrl::writeQueueFull(unsigned int neededEntries) const
{ {
DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n",
writeBufferSize, writeQueue.size(), neededEntries); writeBufferSize, writeQueue.size(), neededEntries);
return (writeQueue.size() + neededEntries) > writeBufferSize; return (writeQueue.size() + neededEntries) > writeBufferSize;
} }
SimpleDRAM::DRAMPacket* DRAMCtrl::DRAMPacket*
SimpleDRAM::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
bool isRead) bool isRead)
{ {
// decode the address based on the address mapping scheme, with // decode the address based on the address mapping scheme, with
@ -293,7 +293,7 @@ SimpleDRAM::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
} }
void void
SimpleDRAM::addToReadQueue(PacketPtr pkt, unsigned int pktCount) DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
{ {
// only add to the read queue here. whenever the request is // only add to the read queue here. whenever the request is
// eventually done, set the readyTime, and call schedule() // eventually done, set the readyTime, and call schedule()
@ -382,7 +382,7 @@ SimpleDRAM::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
} }
void void
SimpleDRAM::processWriteEvent() DRAMCtrl::processWriteEvent()
{ {
assert(!writeQueue.empty()); assert(!writeQueue.empty());
@ -439,7 +439,7 @@ SimpleDRAM::processWriteEvent()
void void
SimpleDRAM::triggerWrites() DRAMCtrl::triggerWrites()
{ {
DPRINTF(DRAM, "Writes triggered at %lld\n", curTick()); DPRINTF(DRAM, "Writes triggered at %lld\n", curTick());
// Flag variable to stop any more read scheduling // Flag variable to stop any more read scheduling
@ -455,7 +455,7 @@ SimpleDRAM::triggerWrites()
} }
void void
SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
{ {
// only add to the write queue here. whenever the request is // only add to the write queue here. whenever the request is
// eventually done, set the readyTime, and call schedule() // eventually done, set the readyTime, and call schedule()
@ -567,7 +567,7 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
} }
void void
SimpleDRAM::printParams() const DRAMCtrl::printParams() const
{ {
// Sanity check print of important parameters // Sanity check print of important parameters
DPRINTF(DRAM, DPRINTF(DRAM,
@ -618,7 +618,7 @@ SimpleDRAM::printParams() const
} }
void void
SimpleDRAM::printQs() const { DRAMCtrl::printQs() const {
DPRINTF(DRAM, "===READ QUEUE===\n\n"); DPRINTF(DRAM, "===READ QUEUE===\n\n");
for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) {
DPRINTF(DRAM, "Read %lu\n", (*i)->addr); DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
@ -634,7 +634,7 @@ SimpleDRAM::printQs() const {
} }
bool bool
SimpleDRAM::recvTimingReq(PacketPtr pkt) DRAMCtrl::recvTimingReq(PacketPtr pkt)
{ {
/// @todo temporary hack to deal with memory corruption issues until /// @todo temporary hack to deal with memory corruption issues until
/// 4-phase transactions are complete /// 4-phase transactions are complete
@ -705,7 +705,7 @@ SimpleDRAM::recvTimingReq(PacketPtr pkt)
} }
void void
SimpleDRAM::processRespondEvent() DRAMCtrl::processRespondEvent()
{ {
DPRINTF(DRAM, DPRINTF(DRAM,
"processRespondEvent(): Some req has reached its readyTime\n"); "processRespondEvent(): Some req has reached its readyTime\n");
@ -755,7 +755,7 @@ SimpleDRAM::processRespondEvent()
} }
void void
SimpleDRAM::chooseNextWrite() DRAMCtrl::chooseNextWrite()
{ {
// This method does the arbitration between write requests. The // This method does the arbitration between write requests. The
// chosen packet is simply moved to the head of the write // chosen packet is simply moved to the head of the write
@ -779,7 +779,7 @@ SimpleDRAM::chooseNextWrite()
} }
bool bool
SimpleDRAM::chooseNextRead() DRAMCtrl::chooseNextRead()
{ {
// This method does the arbitration between read requests. The // This method does the arbitration between read requests. The
// chosen packet is simply moved to the head of the queue. The // chosen packet is simply moved to the head of the queue. The
@ -807,7 +807,7 @@ SimpleDRAM::chooseNextRead()
} }
void void
SimpleDRAM::reorderQueue(std::deque<DRAMPacket*>& queue) DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue)
{ {
// Only determine this when needed // Only determine this when needed
uint64_t earliest_banks = 0; uint64_t earliest_banks = 0;
@ -847,7 +847,7 @@ SimpleDRAM::reorderQueue(std::deque<DRAMPacket*>& queue)
} }
void void
SimpleDRAM::accessAndRespond(PacketPtr pkt, Tick static_latency) DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
{ {
DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr());
@ -879,7 +879,7 @@ SimpleDRAM::accessAndRespond(PacketPtr pkt, Tick static_latency)
} }
pair<Tick, Tick> pair<Tick, Tick>
SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime) DRAMCtrl::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
{ {
// If a request reaches a bank at tick 'inTime', how much time // If a request reaches a bank at tick 'inTime', how much time
// *after* that does it take to finish the request, depending // *after* that does it take to finish the request, depending
@ -963,13 +963,13 @@ SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
} }
void void
SimpleDRAM::processNextReqEvent() DRAMCtrl::processNextReqEvent()
{ {
scheduleNextReq(); scheduleNextReq();
} }
void void
SimpleDRAM::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank) DRAMCtrl::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank)
{ {
assert(0 <= rank && rank < ranksPerChannel); assert(0 <= rank && rank < ranksPerChannel);
assert(actTicks[rank].size() == activationLimit); assert(actTicks[rank].size() == activationLimit);
@ -1035,7 +1035,7 @@ SimpleDRAM::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank)
} }
void void
SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt) DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
{ {
DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
@ -1237,7 +1237,7 @@ SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
} }
void void
SimpleDRAM::moveToRespQ() DRAMCtrl::moveToRespQ()
{ {
// Remove from read queue // Remove from read queue
DRAMPacket* dram_pkt = readQueue.front(); DRAMPacket* dram_pkt = readQueue.front();
@ -1278,7 +1278,7 @@ SimpleDRAM::moveToRespQ()
} }
void void
SimpleDRAM::scheduleNextReq() DRAMCtrl::scheduleNextReq()
{ {
DPRINTF(DRAM, "Reached scheduleNextReq()\n"); DPRINTF(DRAM, "Reached scheduleNextReq()\n");
@ -1297,7 +1297,7 @@ SimpleDRAM::scheduleNextReq()
} }
Tick Tick
SimpleDRAM::maxBankFreeAt() const DRAMCtrl::maxBankFreeAt() const
{ {
Tick banksFree = 0; Tick banksFree = 0;
@ -1309,7 +1309,7 @@ SimpleDRAM::maxBankFreeAt() const
} }
uint64_t uint64_t
SimpleDRAM::minBankFreeAt(const deque<DRAMPacket*>& queue) const DRAMCtrl::minBankFreeAt(const deque<DRAMPacket*>& queue) const
{ {
uint64_t bank_mask = 0; uint64_t bank_mask = 0;
Tick freeAt = MaxTick; Tick freeAt = MaxTick;
@ -1341,7 +1341,7 @@ SimpleDRAM::minBankFreeAt(const deque<DRAMPacket*>& queue) const
} }
void void
SimpleDRAM::processRefreshEvent() DRAMCtrl::processRefreshEvent()
{ {
DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick()); DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick());
@ -1361,7 +1361,7 @@ SimpleDRAM::processRefreshEvent()
} }
void void
SimpleDRAM::regStats() DRAMCtrl::regStats()
{ {
using namespace Stats; using namespace Stats;
@ -1624,14 +1624,14 @@ SimpleDRAM::regStats()
} }
void void
SimpleDRAM::recvFunctional(PacketPtr pkt) DRAMCtrl::recvFunctional(PacketPtr pkt)
{ {
// rely on the abstract memory // rely on the abstract memory
functionalAccess(pkt); functionalAccess(pkt);
} }
BaseSlavePort& BaseSlavePort&
SimpleDRAM::getSlavePort(const string &if_name, PortID idx) DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
{ {
if (if_name != "port") { if (if_name != "port") {
return MemObject::getSlavePort(if_name, idx); return MemObject::getSlavePort(if_name, idx);
@ -1641,7 +1641,7 @@ SimpleDRAM::getSlavePort(const string &if_name, PortID idx)
} }
unsigned int unsigned int
SimpleDRAM::drain(DrainManager *dm) DRAMCtrl::drain(DrainManager *dm)
{ {
unsigned int count = port.drain(dm); unsigned int count = port.drain(dm);
@ -1670,13 +1670,13 @@ SimpleDRAM::drain(DrainManager *dm)
return count; return count;
} }
SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory) DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
: QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
memory(_memory) memory(_memory)
{ } { }
AddrRangeList AddrRangeList
SimpleDRAM::MemoryPort::getAddrRanges() const DRAMCtrl::MemoryPort::getAddrRanges() const
{ {
AddrRangeList ranges; AddrRangeList ranges;
ranges.push_back(memory.getAddrRange()); ranges.push_back(memory.getAddrRange());
@ -1684,7 +1684,7 @@ SimpleDRAM::MemoryPort::getAddrRanges() const
} }
void void
SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt) DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
{ {
pkt->pushLabel(memory.name()); pkt->pushLabel(memory.name());
@ -1699,20 +1699,20 @@ SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt)
} }
Tick Tick
SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt) DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
{ {
return memory.recvAtomic(pkt); return memory.recvAtomic(pkt);
} }
bool bool
SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt) DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
{ {
// pass it to the memory controller // pass it to the memory controller
return memory.recvTimingReq(pkt); return memory.recvTimingReq(pkt);
} }
SimpleDRAM* DRAMCtrl*
SimpleDRAMParams::create() DRAMCtrlParams::create()
{ {
return new SimpleDRAM(this); return new DRAMCtrl(this);
} }

32
src/mem/simple_dram.hh → src/mem/dram_ctrl.hh
View file

@ -44,11 +44,11 @@
/** /**
* @file * @file
* SimpleDRAM declaration * DRAMCtrl declaration
*/ */
#ifndef __MEM_SIMPLE_DRAM_HH__ #ifndef __MEM_DRAM_CTRL_HH__
#define __MEM_SIMPLE_DRAM_HH__ #define __MEM_DRAM_CTRL_HH__
#include <deque> #include <deque>
@ -58,13 +58,13 @@
#include "enums/PageManage.hh" #include "enums/PageManage.hh"
#include "mem/abstract_mem.hh" #include "mem/abstract_mem.hh"
#include "mem/qport.hh" #include "mem/qport.hh"
#include "params/SimpleDRAM.hh" #include "params/DRAMCtrl.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"
/** /**
* The simple DRAM is a basic single-channel memory controller aiming * The DRAM controller is a basic single-channel memory controller
* to mimic a high-level DRAM controller and the most important timing * aiming to mimic a high-level DRAM controller and the most important
* constraints associated with the DRAM. The focus is really on * timing constraints associated with the DRAM. The focus is really on
* modelling the impact on the system rather than the DRAM itself, * modelling the impact on the system rather than the DRAM itself,
* hence the focus is on the controller model and not on the * hence the focus is on the controller model and not on the
* memory. By adhering to the correct timing constraints, ultimately * memory. By adhering to the correct timing constraints, ultimately
@ -80,7 +80,7 @@
* wide range of memory technologies, and also collect statistics * wide range of memory technologies, and also collect statistics
* about the use of the memory. * about the use of the memory.
*/ */
class SimpleDRAM : public AbstractMemory class DRAMCtrl : public AbstractMemory
{ {
private: private:
@ -91,11 +91,11 @@ class SimpleDRAM : public AbstractMemory
{ {
SlavePacketQueue queue; SlavePacketQueue queue;
SimpleDRAM& memory; DRAMCtrl& memory;
public: public:
MemoryPort(const std::string& name, SimpleDRAM& _memory); MemoryPort(const std::string& name, DRAMCtrl& _memory);
protected: protected:
@ -255,16 +255,16 @@ class SimpleDRAM : public AbstractMemory
* in these methods * in these methods
*/ */
void processWriteEvent(); void processWriteEvent();
EventWrapper<SimpleDRAM, &SimpleDRAM::processWriteEvent> writeEvent; EventWrapper<DRAMCtrl, &DRAMCtrl::processWriteEvent> writeEvent;
void processRespondEvent(); void processRespondEvent();
EventWrapper<SimpleDRAM, &SimpleDRAM::processRespondEvent> respondEvent; EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
void processRefreshEvent(); void processRefreshEvent();
EventWrapper<SimpleDRAM, &SimpleDRAM::processRefreshEvent> refreshEvent; EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
void processNextReqEvent(); void processNextReqEvent();
EventWrapper<SimpleDRAM,&SimpleDRAM::processNextReqEvent> nextReqEvent; EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
/** /**
@ -623,7 +623,7 @@ class SimpleDRAM : public AbstractMemory
void regStats(); void regStats();
SimpleDRAM(const SimpleDRAMParams* p); DRAMCtrl(const DRAMCtrlParams* p);
unsigned int drain(DrainManager* dm); unsigned int drain(DrainManager* dm);
@ -641,4 +641,4 @@ class SimpleDRAM : public AbstractMemory
}; };
#endif //__MEM_SIMPLE_DRAM_HH__ #endif //__MEM_DRAM_CTRL_HH__