Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
This commit is contained in:
Ali Saidi
commit
7be58fd5f4
4 changed files with 387 additions and 11 deletions
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@ -30,6 +30,9 @@
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/* @file
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* Device model for Intel's 8254x line of gigabit ethernet controllers.
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* In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
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* fewest workarounds in the driver. It will probably work with most of the
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* other MACs with slight modifications.
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*/
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#include "base/inet.hh"
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@ -39,10 +42,38 @@
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#include "sim/stats.hh"
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#include "sim/system.hh"
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using namespace iGbReg;
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IGbE::IGbE(Params *p)
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: PciDev(p), etherInt(NULL)
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{
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// Initialized internal registers per Intel documentation
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regs.tctl.reg = 0;
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regs.rctl.reg = 0;
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regs.ctrl.reg = 0;
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regs.ctrl.fd = 1;
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regs.ctrl.lrst = 1;
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regs.ctrl.speed = 2;
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regs.ctrl.frcspd = 1;
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regs.sts.reg = 0;
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regs.eecd.reg = 0;
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regs.eecd.fwe = 1;
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regs.eecd.ee_type = 1;
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regs.eerd.reg = 0;
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regs.icd.reg = 0;
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regs.imc.reg = 0;
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regs.rctl.reg = 0;
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regs.tctl.reg = 0;
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regs.manc.reg = 0;
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eeOpBits = 0;
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eeAddrBits = 0;
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eeDataBits = 0;
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eeOpcode = 0;
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memset(&flash, 0, EEPROM_SIZE);
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// Magic happy checksum value
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flash[0] = 0xBABA;
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}
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@ -74,15 +105,49 @@ IGbE::read(PacketPtr pkt)
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// Only Memory register BAR is allowed
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assert(bar == 0);
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DPRINTF(Ethernet, "Accessed devie register %#X\n", daddr);
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// Only 32bit accesses allowed
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assert(pkt->getSize() == 4);
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DPRINTF(Ethernet, "Read device register %#X\n", daddr);
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pkt->allocate();
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///
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/// Handle read of register here
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///
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switch (daddr) {
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case CTRL:
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pkt->set<uint32_t>(regs.ctrl.reg);
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break;
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case STATUS:
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pkt->set<uint32_t>(regs.sts.reg);
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break;
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case EECD:
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pkt->set<uint32_t>(regs.eecd.reg);
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break;
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case EERD:
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pkt->set<uint32_t>(regs.eerd.reg);
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break;
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case ICR:
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pkt->set<uint32_t>(regs.icd.reg);
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break;
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case IMC:
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pkt->set<uint32_t>(regs.imc.reg);
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break;
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case RCTL:
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pkt->set<uint32_t>(regs.rctl.reg);
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break;
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case TCTL:
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pkt->set<uint32_t>(regs.tctl.reg);
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break;
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case MANC:
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pkt->set<uint32_t>(regs.manc.reg);
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break;
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default:
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panic("Read request to unknown register number: %#x\n", daddr);
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};
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pkt->result = Packet::Success;
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return pioDelay;
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}
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@ -93,17 +158,100 @@ IGbE::write(PacketPtr pkt)
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int bar;
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Addr daddr;
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if (!getBAR(pkt->getAddr(), bar, daddr))
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panic("Invalid PCI memory access to unmapped memory.\n");
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// Only Memory register BAR is allowed
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assert(bar == 0);
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DPRINTF(Ethernet, "Accessed devie register %#X\n", daddr);
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// Only 32bit accesses allowed
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assert(pkt->getSize() == sizeof(uint32_t));
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DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>());
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///
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/// Handle write of register here
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///
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uint32_t val = pkt->get<uint32_t>();
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switch (daddr) {
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case CTRL:
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regs.ctrl.reg = val;
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break;
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case STATUS:
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regs.sts.reg = val;
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break;
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case EECD:
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int oldClk;
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oldClk = regs.eecd.sk;
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regs.eecd.reg = val;
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// See if this is a eeprom access and emulate accordingly
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if (!oldClk && regs.eecd.sk) {
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if (eeOpBits < 8) {
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eeOpcode = eeOpcode << 1 | regs.eecd.din;
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eeOpBits++;
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} else if (eeAddrBits < 8 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
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eeAddr = eeAddr << 1 | regs.eecd.din;
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eeAddrBits++;
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} else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) {
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assert(eeAddr < EEPROM_SIZE);
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DPRINTF(Ethernet, "EEPROM bit read: %d word: %#X\n",
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flash[eeAddr] >> eeDataBits & 0x1, flash[eeAddr]);
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regs.eecd.dout = (flash[eeAddr] >> eeDataBits) & 0x1;
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eeDataBits++;
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} else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) {
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regs.eecd.dout = 0;
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eeDataBits++;
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} else
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panic("What's going on with eeprom interface? opcode:"
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" %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode,
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(uint32_t)eeOpBits, (uint32_t)eeAddr,
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(uint32_t)eeAddrBits, (uint32_t)eeDataBits);
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// Reset everything for the next command
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if ((eeDataBits == 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) ||
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(eeDataBits == 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI)) {
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eeOpBits = 0;
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eeAddrBits = 0;
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eeDataBits = 0;
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eeOpcode = 0;
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eeAddr = 0;
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}
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DPRINTF(Ethernet, "EEPROM: opcode: %#X:%d\n",
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(uint32_t)eeOpcode, (uint32_t) eeOpBits);
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if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI ||
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eeOpcode == EEPROM_RDSR_OPCODE_SPI ))
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panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode,
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(uint32_t)eeOpBits);
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}
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// If driver requests eeprom access, immediately give it to it
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regs.eecd.ee_gnt = regs.eecd.ee_req;
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break;
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case EERD:
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regs.eerd.reg = val;
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break;
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case ICR:
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regs.icd.reg = val;
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break;
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case IMC:
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regs.imc.reg = val;
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break;
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case RCTL:
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regs.rctl.reg = val;
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break;
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case TCTL:
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regs.tctl.reg = val;
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break;
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case MANC:
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regs.manc.reg = val;
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break;
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default:
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panic("Write request to unknown register number: %#x\n", daddr);
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};
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pkt->result = Packet::Success;
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return pioDelay;
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@ -39,6 +39,7 @@
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#include "base/statistics.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/i8254xGBe_defs.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "sim/eventq.hh"
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@ -49,6 +50,12 @@ class IGbE : public PciDev
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{
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private:
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IGbEInt *etherInt;
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iGbReg::Regs regs;
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int eeOpBits, eeAddrBits, eeDataBits;
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uint8_t eeOpcode, eeAddr;
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uint16_t flash[iGbReg::EEPROM_SIZE];
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public:
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struct Params : public PciDev::Params
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@ -34,17 +34,18 @@
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namespace iGbReg {
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const uint32_t CTRL = 0x00000;
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const uint32_t STATUS = 0x00008;
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const uint32_t EECD = 0x00010;
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const uint32_t CTRL = 0x00000; //*
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const uint32_t STATUS = 0x00008; //*
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const uint32_t EECD = 0x00010; //*
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const uint32_t EERD = 0x00014; //*
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const uint32_t CTRL_EXT = 0x00018;
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const uint32_t PBA = 0x01000;
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const uint32_t ICR = 0x000C0;
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const uint32_t ICR = 0x000C0; //*
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const uint32_t ITR = 0x000C4;
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const uint32_t ICS = 0x000C8;
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const uint32_t IMS = 0x000D0;
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const uint32_t IMC = 0x000D8;
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const uint32_t RCTL = 0x00100;
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const uint32_t IMC = 0x000D8; //*
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const uint32_t RCTL = 0x00100; //*
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const uint32_t RDBAL = 0x02800;
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const uint32_t RDBAH = 0x02804;
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const uint32_t RDLEN = 0x02808;
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@ -53,7 +54,7 @@ const uint32_t RDT = 0x02818;
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const uint32_t RDTR = 0x02820;
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const uint32_t RADV = 0x0282C;
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const uint32_t RSRPD = 0x02C00;
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const uint32_t TCTL = 0x00400;
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const uint32_t TCTL = 0x00400; //*
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const uint32_t TDBAL = 0x03800;
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const uint32_t TDBAH = 0x03804;
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const uint32_t TDLEN = 0x03808;
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@ -66,6 +67,11 @@ const uint32_t TADV = 0x0282C;
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const uint32_t TSPMT = 0x03830;
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const uint32_t RXDCTL = 0x02828;
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const uint32_t RXCSUM = 0x05000;
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const uint32_t MANC = 0x05820;//*
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const uint8_t EEPROM_READ_OPCODE_SPI = 0x03;
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const uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05;
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const uint8_t EEPROM_SIZE = 64;
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struct RxDesc {
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Addr buf;
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@ -239,4 +245,219 @@ union TxDesc {
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} type;
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};
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struct Regs {
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union { // 0x0000 CTRL Register
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uint32_t reg;
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struct {
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uint8_t fd:1; // full duplex
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uint8_t bem:1; // big endian mode
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uint8_t pcipr:1; // PCI priority
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uint8_t lrst:1; // link reset
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uint8_t tme:1; // test mode enable
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uint8_t asde:1; // Auto-speed detection
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uint8_t slu:1; // Set link up
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uint8_t ilos:1; // invert los-of-signal
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uint8_t speed:2; // speed selection bits
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uint8_t be32:1; // big endian mode 32
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uint8_t frcspd:1; // force speed
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uint8_t frcdpx:1; // force duplex
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uint8_t duden:1; // dock/undock enable
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uint8_t dudpol:1; // dock/undock polarity
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uint8_t fphyrst:1; // force phy reset
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uint8_t extlen:1; // external link status enable
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uint8_t rsvd:1; // reserved
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uint8_t sdp0d:1; // software controlled pin data
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uint8_t sdp1d:1; // software controlled pin data
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uint8_t sdp2d:1; // software controlled pin data
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uint8_t sdp3d:1; // software controlled pin data
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uint8_t sdp0i:1; // software controlled pin dir
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uint8_t sdp1i:1; // software controlled pin dir
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uint8_t sdp2i:1; // software controlled pin dir
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uint8_t sdp3i:1; // software controlled pin dir
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uint8_t rst:1; // reset
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uint8_t rfce:1; // receive flow control enable
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uint8_t tfce:1; // transmit flow control enable
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uint8_t rte:1; // routing tag enable
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uint8_t vme:1; // vlan enable
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uint8_t phyrst:1; // phy reset
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} ;
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} ctrl;
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union { // 0x0008 STATUS
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uint32_t reg;
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struct {
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uint8_t fd:1; // full duplex
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uint8_t lu:1; // link up
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uint8_t func:2; // function id
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uint8_t txoff:1; // transmission paused
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uint8_t tbimode:1; // tbi mode
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uint8_t speed:2; // link speed
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uint8_t asdv:2; // auto speed detection value
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uint8_t mtxckok:1; // mtx clock running ok
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uint8_t pci66:1; // In 66Mhz pci slot
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uint8_t bus64:1; // in 64 bit slot
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uint8_t pcix:1; // Pci mode
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uint8_t pcixspd:1; // pci x speed
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uint8_t reserved; // reserved
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} ;
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} sts;
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union { // 0x0010 EECD
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uint32_t reg;
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struct {
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uint8_t sk:1; // clack input to the eeprom
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uint8_t cs:1; // chip select to eeprom
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uint8_t din:1; // data input to eeprom
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uint8_t dout:1; // data output bit
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uint8_t fwe:2; // flash write enable
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uint8_t ee_req:1; // request eeprom access
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uint8_t ee_gnt:1; // grant eeprom access
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uint8_t ee_pres:1; // eeprom present
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uint8_t ee_size:1; // eeprom size
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uint8_t ee_sz1:1; // eeprom size
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uint8_t rsvd:2; // reserved
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uint8_t ee_type:1; // type of eeprom
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} ;
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} eecd;
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union { // 0x0014 EERD
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uint32_t reg;
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struct {
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uint8_t start:1; // start read
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uint8_t done:1; // done read
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uint16_t addr:14; // address
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uint16_t data; // data
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};
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} eerd;
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union { // 0x00C0 ICR
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uint32_t reg;
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struct {
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uint8_t txdw:1; // tx descr witten back
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uint8_t txqe:1; // tx queue empty
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uint8_t lsc:1; // link status change
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uint8_t rxseq:1; // rcv sequence error
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uint8_t rxdmt0:1; // rcv descriptor min thresh
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uint8_t rsvd1:1; // reserved
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uint8_t rxo:1; // receive overrunn
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uint8_t rxt0:1; // receiver timer interrupt
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uint8_t rsvd2:1; // reserved
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uint8_t mdac:1; // mdi/o access complete
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uint8_t rxcfg:1; // recv /c/ ordered sets
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uint8_t rsvd3:1; // reserved
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uint8_t phyint:1; // phy interrupt
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uint8_t gpi1:1; // gpi int 1
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uint8_t gpi2:1; // gpi int 2
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uint8_t txdlow:1; // transmit desc low thresh
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uint8_t srpd:1; // small receive packet detected
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uint16_t rsvd4:15; // reserved
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} ;
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} icd;
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union { // 0x00C0 IMC
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uint32_t reg;
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struct {
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uint8_t txdw:1; // tx descr witten back
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uint8_t txqe:1; // tx queue empty
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uint8_t lsc:1; // link status change
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uint8_t rxseq:1; // rcv sequence error
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uint8_t rxdmt0:1; // rcv descriptor min thresh
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uint8_t rsvd1:1; // reserved
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uint8_t rxo:1; // receive overrunn
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uint8_t rxt0:1; // receiver timer interrupt
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uint8_t rsvd2:1; // reserved
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uint8_t mdac:1; // mdi/o access complete
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uint8_t rxcfg:1; // recv /c/ ordered sets
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uint8_t rsvd3:1; // reserved
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uint8_t phyint:1; // phy interrupt
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uint8_t gpi1:1; // gpi int 1
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uint8_t gpi2:1; // gpi int 2
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uint8_t txdlow:1; // transmit desc low thresh
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uint8_t srpd:1; // small receive packet detected
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uint16_t rsvd4:15; // reserved
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} ;
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} imc;
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union { // 0x0100 RCTL
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uint32_t reg;
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struct {
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uint8_t rst:1; // Reset
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uint8_t en:1; // Enable
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uint8_t sbp:1; // Store bad packets
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uint8_t upe:1; // Unicast Promiscuous enabled
|
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uint8_t mpe:1; // Multicast promiscuous enabled
|
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uint8_t lpe:1; // long packet reception enabled
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uint8_t lbm:2; //
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uint8_t rdmts:2; //
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uint8_t rsvd:2; //
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uint8_t mo:2; //
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uint8_t mdr:1; //
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uint8_t bam:1; //
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uint8_t bsize:2; //
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||||
uint8_t vpe:1; //
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uint8_t cfien:1; //
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uint8_t cfi:1; //
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uint8_t rsvd2:1; //
|
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uint8_t dpf:1; // discard pause frames
|
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uint8_t pmcf:1; // pass mac control frames
|
||||
uint8_t rsvd3:1; // reserved
|
||||
uint8_t bsex:1; // buffer size extension
|
||||
uint8_t secrc:1; // strip ethernet crc from incoming packet
|
||||
uint8_t rsvd1:5; // reserved
|
||||
} ;
|
||||
} rctl;
|
||||
|
||||
union { // 0x0400 TCTL
|
||||
uint32_t reg;
|
||||
struct {
|
||||
uint8_t rst:1; // Reset
|
||||
uint8_t en:1; // Enable
|
||||
uint8_t bce:1; // busy check enable
|
||||
uint8_t psp:1; // pad short packets
|
||||
uint8_t ct:8; // collision threshold
|
||||
uint16_t cold:10; // collision distance
|
||||
uint8_t swxoff:1; // software xoff transmission
|
||||
uint8_t pbe:1; // packet burst enable
|
||||
uint8_t rtlc:1; // retransmit late collisions
|
||||
uint8_t nrtu:1; // on underrun no TX
|
||||
uint8_t mulr:1; // multiple request
|
||||
uint8_t rsvd:5; // reserved
|
||||
} ;
|
||||
} tctl;
|
||||
|
||||
union { // 0x5820 MANC
|
||||
uint32_t reg;
|
||||
struct {
|
||||
uint8_t smbus:1; // SMBus enabled #####
|
||||
uint8_t asf:1; // ASF enabled #####
|
||||
uint8_t ronforce:1; // reset of force
|
||||
uint8_t rsvd:5; // reserved
|
||||
uint8_t rmcp1:1; // rcmp1 filtering
|
||||
uint8_t rmcp2:1; // rcmp2 filtering
|
||||
uint8_t ipv4:1; // enable ipv4
|
||||
uint8_t ipv6:1; // enable ipv6
|
||||
uint8_t snap:1; // accept snap
|
||||
uint8_t arp:1; // filter arp #####
|
||||
uint8_t neighbor:1; // neighbor discovery
|
||||
uint8_t arp_resp:1; // arp response
|
||||
uint8_t tcorst:1; // tco reset happened
|
||||
uint8_t rcvtco:1; // receive tco enabled ######
|
||||
uint8_t blkphyrst:1;// block phy resets ########
|
||||
uint8_t rcvall:1; // receive all
|
||||
uint8_t macaddrfltr:1; // mac address filtering ######
|
||||
uint8_t mng2host:1; // mng2 host packets #######
|
||||
uint8_t ipaddrfltr:1; // ip address filtering
|
||||
uint8_t xsumfilter:1; // checksum filtering
|
||||
uint8_t brfilter:1; // broadcast filtering
|
||||
uint8_t smbreq:1; // smb request
|
||||
uint8_t smbgnt:1; // smb grant
|
||||
uint8_t smbclkin:1; // smbclkin
|
||||
uint8_t smbdatain:1; // smbdatain
|
||||
uint8_t smbdataout:1; // smb data out
|
||||
uint8_t smbclkout:1; // smb clock out
|
||||
uint8_t rsvd2:2;
|
||||
};
|
||||
} manc;
|
||||
};
|
||||
|
||||
}; // iGbReg namespace
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ class IGbE(PciDevice):
|
|||
|
||||
class IGbEPciData(PciConfigData):
|
||||
VendorID = 0x8086
|
||||
DeviceID = 0x1026
|
||||
DeviceID = 0x1075
|
||||
SubsystemID = 0x1008
|
||||
SubsystemVendorID = 0x8086
|
||||
Status = 0x0000
|
||||
|
|
|
|||
Loading…
Reference in a new issue