inorder: init internal debug cpu counters
- cpuEventNum - resReqCount
This commit is contained in:
parent
ab2f864af2
commit
7b3b362ba5
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@ -115,7 +115,8 @@ InOrderCPU::CPUEvent::process()
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cpu->activateThread(tid);
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cpu->activateThread(tid);
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break;
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break;
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//@TODO: Consider Implementing "Suspend Thread" as Separate from Deallocate
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//@TODO: Consider Implementing "Suspend Thread" as Separate from
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//Deallocate
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case SuspendThread: // Suspend & Deallocate are same for now.
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case SuspendThread: // Suspend & Deallocate are same for now.
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//cpu->suspendThread(tid);
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//cpu->suspendThread(tid);
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//break;
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//break;
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@ -145,11 +146,14 @@ InOrderCPU::CPUEvent::process()
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default:
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default:
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fatal("Unrecognized Event Type %d", cpuEventType);
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fatal("Unrecognized Event Type %d", cpuEventType);
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}
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}
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cpu->cpuEventRemoveList.push(this);
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cpu->cpuEventRemoveList.push(this);
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}
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}
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const char *
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const char *
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InOrderCPU::CPUEvent::description()
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InOrderCPU::CPUEvent::description()
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{
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{
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@ -185,6 +189,10 @@ InOrderCPU::InOrderCPU(Params *params)
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system(params->system),
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system(params->system),
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physmem(system->physmem),
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physmem(system->physmem),
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#endif // FULL_SYSTEM
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#endif // FULL_SYSTEM
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#ifdef DEBUG
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cpuEventNum(0),
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resReqCount(0),
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#endif // DEBUG
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switchCount(0),
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switchCount(0),
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deferRegistration(false/*params->deferRegistration*/),
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deferRegistration(false/*params->deferRegistration*/),
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stageTracing(params->stageTracing),
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stageTracing(params->stageTracing),
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@ -301,7 +309,7 @@ InOrderCPU::InOrderCPU(Params *params)
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// Define dummy instructions and resource requests to be used.
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// Define dummy instructions and resource requests to be used.
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DynInstPtr dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0);
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DynInstPtr dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0);
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dummyReq = new ResourceRequest(NULL, NULL, 0, 0, 0, 0);
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dummyReq = new ResourceRequest(resPool->getResource(0), NULL, 0, 0, 0, 0);
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// Reset CPU to reset state.
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// Reset CPU to reset state.
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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@ -322,6 +330,13 @@ InOrderCPU::regStats()
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/* Register the Resource Pool's stats here.*/
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/* Register the Resource Pool's stats here.*/
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resPool->regStats();
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resPool->regStats();
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#ifdef DEBUG
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maxResReqCount
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.name(name() + ".maxResReqCount")
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.desc("Maximum number of live resource requests in CPU")
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.prereq(maxResReqCount);
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#endif
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/* Register any of the InOrderCPU's stats here.*/
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/* Register any of the InOrderCPU's stats here.*/
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timesIdled
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timesIdled
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.name(name() + ".timesIdled")
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.name(name() + ".timesIdled")
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@ -342,7 +357,7 @@ InOrderCPU::regStats()
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smtCycles
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smtCycles
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.name(name() + ".smtCycles")
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.name(name() + ".smtCycles")
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.desc("Total number of cycles that the CPU was simultaneous multithreading.(SMT)");
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.desc("Total number of cycles that the CPU was in SMT-mode");
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committedInsts
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committedInsts
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.init(numThreads)
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.init(numThreads)
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@ -435,7 +450,8 @@ InOrderCPU::tick()
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//Tick next_tick = curTick + cycles(1);
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//Tick next_tick = curTick + cycles(1);
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//tickEvent.schedule(next_tick);
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//tickEvent.schedule(next_tick);
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mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
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mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
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DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n", nextCycle(curTick + 1));
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DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
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nextCycle(curTick + 1));
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}
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}
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}
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}
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@ -640,8 +656,8 @@ void
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InOrderCPU::addToCurrentThreads(ThreadID tid)
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InOrderCPU::addToCurrentThreads(ThreadID tid)
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{
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{
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if (!isThreadInCPU(tid)) {
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if (!isThreadInCPU(tid)) {
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DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU.\n",
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DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU."
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tid);
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"\n", tid);
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currentThreads.push_back(tid);
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currentThreads.push_back(tid);
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}
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}
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}
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}
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@ -1002,9 +1018,11 @@ InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
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tid = TheISA::getTargetThread(tcBase(tid));
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tid = TheISA::getTargetThread(tcBase(tid));
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}
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}
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if (reg_idx < FP_Base_DepTag) { // Integer Register File
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if (reg_idx < FP_Base_DepTag) {
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// Integer Register File
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return readIntReg(reg_idx, tid);
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return readIntReg(reg_idx, tid);
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} else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
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} else if (reg_idx < Ctrl_Base_DepTag) {
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// Float Register File
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reg_idx -= FP_Base_DepTag;
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reg_idx -= FP_Base_DepTag;
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return readFloatRegBits(reg_idx, tid);
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return readFloatRegBits(reg_idx, tid);
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} else {
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} else {
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@ -1070,9 +1088,12 @@ InOrderCPU::addInst(DynInstPtr &inst)
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void
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void
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InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
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InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
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{
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{
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// Set the CPU's PCs - This contributes to the precise state of the CPU which can be used
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// Set the CPU's PCs - This contributes to the precise state of the CPU
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// when restoring a thread to the CPU after a fork or after an exception
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// which can be used when restoring a thread to the CPU after a fork or
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// @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if it's a branch or not
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// after an exception
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// =================
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// @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if
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// it's a branch or not
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setPC(inst->readPC(), tid);
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setPC(inst->readPC(), tid);
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setNextPC(inst->readNextPC(), tid);
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setNextPC(inst->readNextPC(), tid);
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setNextNPC(inst->readNextNPC(), tid);
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setNextNPC(inst->readNextNPC(), tid);
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@ -1112,7 +1133,8 @@ InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
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// Broadcast to other resources an instruction
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// Broadcast to other resources an instruction
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// has been completed
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// has been completed
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resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst, tid);
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resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
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tid);
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// Finally, remove instruction from CPU
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// Finally, remove instruction from CPU
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removeInst(inst);
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removeInst(inst);
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@ -1380,7 +1402,8 @@ InOrderCPU::read(DynInstPtr inst, Addr addr, T &data, unsigned flags)
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{
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{
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//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
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//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
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// you want to run w/out caches?
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// you want to run w/out caches?
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CacheUnit *cache_res = dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
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CacheUnit *cache_res =
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dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
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return cache_res->read(inst, addr, data, flags);
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return cache_res->read(inst, addr, data, flags);
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}
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}
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@ -1483,14 +1506,16 @@ InOrderCPU::write(DynInstPtr inst, uint8_t data, Addr addr,
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template<>
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template<>
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Fault
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Fault
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InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags, uint64_t *res)
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InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags,
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uint64_t *res)
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{
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{
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return write(inst, *(uint64_t*)&data, addr, flags, res);
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return write(inst, *(uint64_t*)&data, addr, flags, res);
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}
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}
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template<>
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template<>
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Fault
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Fault
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InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags, uint64_t *res)
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InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags,
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uint64_t *res)
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{
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{
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return write(inst, *(uint32_t*)&data, addr, flags, res);
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return write(inst, *(uint32_t*)&data, addr, flags, res);
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}
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}
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@ -1498,7 +1523,8 @@ InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags, uint64
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template<>
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template<>
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Fault
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Fault
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InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags, uint64_t *res)
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InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags,
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uint64_t *res)
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{
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{
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return write(inst, (uint32_t)data, addr, flags, res);
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return write(inst, (uint32_t)data, addr, flags, res);
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}
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}
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@ -144,9 +144,11 @@ class InOrderCPU : public BaseCPU
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void scheduleTickEvent(int delay)
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void scheduleTickEvent(int delay)
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{
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{
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if (tickEvent.squashed())
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if (tickEvent.squashed())
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mainEventQueue.reschedule(&tickEvent, nextCycle(curTick + ticks(delay)));
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mainEventQueue.reschedule(&tickEvent,
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nextCycle(curTick + ticks(delay)));
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else if (!tickEvent.scheduled())
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else if (!tickEvent.scheduled())
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mainEventQueue.schedule(&tickEvent, nextCycle(curTick + ticks(delay)));
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mainEventQueue.schedule(&tickEvent,
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nextCycle(curTick + ticks(delay)));
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}
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}
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/** Unschedule tick event, regardless of its current state. */
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/** Unschedule tick event, regardless of its current state. */
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@ -228,7 +230,8 @@ class InOrderCPU : public BaseCPU
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/** Interface between the CPU and CPU resources. */
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/** Interface between the CPU and CPU resources. */
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ResourcePool *resPool;
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ResourcePool *resPool;
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/** Instruction used to signify that there is no *real* instruction in buffer slot */
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/** Instruction used to signify that there is no *real* instruction in
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buffer slot */
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DynInstPtr dummyBufferInst;
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DynInstPtr dummyBufferInst;
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/** Used by resources to signify a denied access to a resource. */
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/** Used by resources to signify a denied access to a resource. */
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@ -420,7 +423,11 @@ class InOrderCPU : public BaseCPU
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/** Get & Update Next Event Number */
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/** Get & Update Next Event Number */
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InstSeqNum getNextEventNum()
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InstSeqNum getNextEventNum()
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{
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{
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#ifdef DEBUG
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return cpuEventNum++;
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return cpuEventNum++;
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#else
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return 0;
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#endif
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}
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}
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/** Register file accessors */
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/** Register file accessors */
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@ -550,8 +557,8 @@ class InOrderCPU : public BaseCPU
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*/
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*/
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std::queue<ListIt> removeList;
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std::queue<ListIt> removeList;
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/** List of all the resource requests that will be removed at the end of this
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/** List of all the resource requests that will be removed at the end
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* cycle.
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* of this cycle.
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*/
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*/
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std::queue<ResourceRequest*> reqRemoveList;
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std::queue<ResourceRequest*> reqRemoveList;
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@ -632,8 +639,12 @@ class InOrderCPU : public BaseCPU
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// LL/SC debug functionality
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// LL/SC debug functionality
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unsigned stCondFails;
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unsigned stCondFails;
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unsigned readStCondFailures() { return stCondFails; }
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unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
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unsigned readStCondFailures()
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{ return stCondFails; }
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unsigned setStCondFailures(unsigned st_fails)
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{ return stCondFails = st_fails; }
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/** Returns a pointer to a thread context. */
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/** Returns a pointer to a thread context. */
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ThreadContext *tcBase(ThreadID tid = 0)
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ThreadContext *tcBase(ThreadID tid = 0)
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@ -663,9 +674,16 @@ class InOrderCPU : public BaseCPU
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/** The global sequence number counter. */
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/** The global sequence number counter. */
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InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
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InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
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#ifdef DEBUG
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/** The global event number counter. */
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/** The global event number counter. */
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InstSeqNum cpuEventNum;
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InstSeqNum cpuEventNum;
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/** Number of resource requests active in CPU **/
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unsigned resReqCount;
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Stats::Scalar maxResReqCount;
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#endif
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/** Counter of how many stages have completed switching out. */
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/** Counter of how many stages have completed switching out. */
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int switchCount;
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int switchCount;
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@ -80,7 +80,8 @@ Resource::regStats()
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{
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{
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instReqsProcessed
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instReqsProcessed
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.name(name() + ".instReqsProcessed")
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.name(name() + ".instReqsProcessed")
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.desc("Number of Instructions Requests that completed in this resource.");
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.desc("Number of Instructions Requests that completed in "
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"this resource.");
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}
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}
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int
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int
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@ -98,7 +99,8 @@ Resource::slotsInUse()
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void
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void
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Resource::freeSlot(int slot_idx)
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Resource::freeSlot(int slot_idx)
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{
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{
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DPRINTF(RefCount, "Removing [tid:%i] [sn:%i]'s request from resource [slot:%i].\n",
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DPRINTF(RefCount, "Removing [tid:%i] [sn:%i]'s request from resource "
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"[slot:%i].\n",
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reqMap[slot_idx]->inst->readTid(),
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reqMap[slot_idx]->inst->readTid(),
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reqMap[slot_idx]->inst->seqNum,
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reqMap[slot_idx]->inst->seqNum,
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slot_idx);
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slot_idx);
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@ -159,7 +161,8 @@ Resource::getSlot(DynInstPtr inst)
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while (map_it != map_end) {
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while (map_it != map_end) {
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if ((*map_it).second) {
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if ((*map_it).second) {
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DPRINTF(Resource, "Currently Serving request from: [tid:%i] [sn:%i].\n",
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DPRINTF(Resource, "Currently Serving request from: "
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"[tid:%i] [sn:%i].\n",
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(*map_it).second->getInst()->readTid(),
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(*map_it).second->getInst()->readTid(),
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(*map_it).second->getInst()->seqNum);
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(*map_it).second->getInst()->seqNum);
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}
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}
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@ -202,10 +205,12 @@ Resource::request(DynInstPtr inst)
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inst_req = getRequest(inst, stage_num, id, slot_num, cmd);
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inst_req = getRequest(inst, stage_num, id, slot_num, cmd);
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if (inst->staticInst) {
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if (inst->staticInst) {
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DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this resource.\n",
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DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this "
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"resource.\n",
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inst->readTid(), inst->seqNum);
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inst->readTid(), inst->seqNum);
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} else {
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} else {
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DPRINTF(Resource, "[tid:%i]: instruction requesting this resource.\n",
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DPRINTF(Resource, "[tid:%i]: instruction requesting this "
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"resource.\n",
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inst->readTid());
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inst->readTid());
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}
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}
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@ -232,7 +237,8 @@ Resource::requestAgain(DynInstPtr inst, bool &do_request)
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do_request = true;
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do_request = true;
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if (inst->staticInst) {
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if (inst->staticInst) {
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DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this resource again.\n",
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DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this resource "
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"again.\n",
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inst->readTid(), inst->seqNum);
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inst->readTid(), inst->seqNum);
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} else {
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} else {
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DPRINTF(Resource, "[tid:%i]: requesting this resource again.\n",
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DPRINTF(Resource, "[tid:%i]: requesting this resource again.\n",
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@ -394,7 +400,41 @@ Resource::unscheduleEvent(DynInstPtr inst)
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int ResourceRequest::resReqID = 0;
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int ResourceRequest::resReqID = 0;
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int ResourceRequest::resReqCount = 0;
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int ResourceRequest::maxReqCount = 0;
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ResourceRequest::ResourceRequest(Resource *_res, DynInstPtr _inst,
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int stage_num, int res_idx, int slot_num,
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unsigned _cmd)
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: res(_res), inst(_inst), cmd(_cmd), stageNum(stage_num),
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resIdx(res_idx), slotNum(slot_num), completed(false),
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squashed(false), processing(false), waiting(false)
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{
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#ifdef DEBUG
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reqID = resReqID++;
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res->cpu->resReqCount++;
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DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID,
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res->cpu->resReqCount);
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||||||
|
if (res->cpu->resReqCount > 100) {
|
||||||
|
fatal("Too many undeleted resource requests. Memory leak?\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
if (res->cpu->resReqCount > maxReqCount) {
|
||||||
|
maxReqCount = res->cpu->resReqCount;
|
||||||
|
res->cpu->maxResReqCount = maxReqCount;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
ResourceRequest::~ResourceRequest()
|
||||||
|
{
|
||||||
|
#ifdef DEBUG
|
||||||
|
res->cpu->resReqCount--;
|
||||||
|
DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID,
|
||||||
|
res->cpu->resReqCount);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
ResourceRequest::done(bool completed)
|
ResourceRequest::done(bool completed)
|
||||||
|
|
|
@ -70,7 +70,8 @@ class Resource {
|
||||||
/** Define this function if resource, has a port to connect to an outside
|
/** Define this function if resource, has a port to connect to an outside
|
||||||
* simulation object.
|
* simulation object.
|
||||||
*/
|
*/
|
||||||
virtual Port* getPort(const std::string &if_name, int idx) { return NULL; }
|
virtual Port* getPort(const std::string &if_name, int idx)
|
||||||
|
{ return NULL; }
|
||||||
|
|
||||||
/** Return ID for this resource */
|
/** Return ID for this resource */
|
||||||
int getId() { return id; }
|
int getId() { return id; }
|
||||||
|
@ -114,9 +115,9 @@ class Resource {
|
||||||
/** Free a resource slot */
|
/** Free a resource slot */
|
||||||
virtual void freeSlot(int slot_idx);
|
virtual void freeSlot(int slot_idx);
|
||||||
|
|
||||||
/** Request usage of a resource for this instruction. If this instruction already
|
/** Request usage of a resource for this instruction. If this instruction
|
||||||
* has made this request to this resource, and that request is uncompleted
|
* already has made this request to this resource, and that request is
|
||||||
* this function will just return that request
|
* uncompleted this function will just return that request
|
||||||
*/
|
*/
|
||||||
virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
|
virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
|
||||||
int res_idx, int slot_num,
|
int res_idx, int slot_num,
|
||||||
|
@ -166,7 +167,8 @@ class Resource {
|
||||||
/** Schedule resource event, regardless of its current state. */
|
/** Schedule resource event, regardless of its current state. */
|
||||||
void scheduleEvent(int slot_idx, int delay);
|
void scheduleEvent(int slot_idx, int delay);
|
||||||
|
|
||||||
/** Find instruction in list, Schedule resource event, regardless of its current state. */
|
/** Find instruction in list, Schedule resource event, regardless of its
|
||||||
|
* current state. */
|
||||||
bool scheduleEvent(DynInstPtr inst, int delay);
|
bool scheduleEvent(DynInstPtr inst, int delay);
|
||||||
|
|
||||||
/** Unschedule resource event, regardless of its current state. */
|
/** Unschedule resource event, regardless of its current state. */
|
||||||
|
@ -303,29 +305,13 @@ class ResourceRequest
|
||||||
|
|
||||||
static int resReqID;
|
static int resReqID;
|
||||||
|
|
||||||
static int resReqCount;
|
static int maxReqCount;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
ResourceRequest(Resource *_res, DynInstPtr _inst, int stage_num,
|
ResourceRequest(Resource *_res, DynInstPtr _inst, int stage_num,
|
||||||
int res_idx, int slot_num, unsigned _cmd)
|
int res_idx, int slot_num, unsigned _cmd);
|
||||||
: res(_res), inst(_inst), cmd(_cmd), stageNum(stage_num),
|
|
||||||
resIdx(res_idx), slotNum(slot_num), completed(false),
|
|
||||||
squashed(false), processing(false), waiting(false)
|
|
||||||
{
|
|
||||||
reqID = resReqID++;
|
|
||||||
resReqCount++;
|
|
||||||
DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID, resReqCount);
|
|
||||||
|
|
||||||
if (resReqCount > 100) {
|
virtual ~ResourceRequest();
|
||||||
fatal("Too many undeleted resource requests. Memory leak?\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
virtual ~ResourceRequest()
|
|
||||||
{
|
|
||||||
resReqCount--;
|
|
||||||
DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID, resReqCount);
|
|
||||||
}
|
|
||||||
|
|
||||||
int reqID;
|
int reqID;
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue