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Change MemReqPtr parameters to references.

Browse source 
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
    Change MemReqPtr parameters to references.

--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
This commit is contained in:
Steve Reinhardt 2004-02-02 10:47:21 -08:00
parent 7c8413db10
commit 7b07b0877f
7 changed files with 22 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/alpha/alpha_memory.cc
View file

@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const
void void
AlphaTlb::checkCacheability(MemReqPtr req) AlphaTlb::checkCacheability(MemReqPtr &req)
{ {
// in Alpha, cacheability is controlled by upper-level bits of the // in Alpha, cacheability is controlled by upper-level bits of the
// physical address // physical address
@ -260,7 +260,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const
Fault Fault
AlphaItb::translate(MemReqPtr req) const AlphaItb::translate(MemReqPtr &req) const
{ {
InternalProcReg *ipr = req->xc->regs.ipr; InternalProcReg *ipr = req->xc->regs.ipr;
@ -425,7 +425,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
} }
Fault Fault
AlphaDtb::translate(MemReqPtr req, bool write) const AlphaDtb::translate(MemReqPtr &req, bool write) const
{ {
RegFile *regs = &req->xc->regs; RegFile *regs = &req->xc->regs;
Addr pc = regs->pc; Addr pc = regs->pc;

6
arch/alpha/alpha_memory.hh
View file

@ -70,7 +70,7 @@ class AlphaTlb : public SimObject
return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK); return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
} }
static void checkCacheability(MemReqPtr req); static void checkCacheability(MemReqPtr &req);
// Checkpointing // Checkpointing
virtual void serialize(std::ostream &os); virtual void serialize(std::ostream &os);
@ -92,7 +92,7 @@ class AlphaItb : public AlphaTlb
AlphaItb(const std::string &name, int size); AlphaItb(const std::string &name, int size);
virtual void regStats(); virtual void regStats();
Fault translate(MemReqPtr req) const; Fault translate(MemReqPtr &req) const;
}; };
class AlphaDtb : public AlphaTlb class AlphaDtb : public AlphaTlb
@ -118,7 +118,7 @@ class AlphaDtb : public AlphaTlb
AlphaDtb(const std::string &name, int size); AlphaDtb(const std::string &name, int size);
virtual void regStats(); virtual void regStats();
Fault translate(MemReqPtr req, bool write) const; Fault translate(MemReqPtr &req, bool write) const;
}; };
#endif // __ALPHA_MEMORY_HH__ #endif // __ALPHA_MEMORY_HH__

18
cpu/exec_context.hh
View file

@ -189,17 +189,17 @@ class ExecContext
int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
Fault translateInstReq(MemReqPtr req) Fault translateInstReq(MemReqPtr &req)
{ {
return itb->translate(req); return itb->translate(req);
} }
Fault translateDataReadReq(MemReqPtr req) Fault translateDataReadReq(MemReqPtr &req)
{ {
return dtb->translate(req, false); return dtb->translate(req, false);
} }
Fault translateDataWriteReq(MemReqPtr req) Fault translateDataWriteReq(MemReqPtr &req)
{ {
return dtb->translate(req, true); return dtb->translate(req, true);
} }
@ -214,7 +214,7 @@ class ExecContext
int getInstAsid() { return asid; } int getInstAsid() { return asid; }
int getDataAsid() { return asid; } int getDataAsid() { return asid; }
Fault dummyTranslation(MemReqPtr req) Fault dummyTranslation(MemReqPtr &req)
{ {
#if 0 #if 0
assert((req->vaddr >> 48 & 0xffff) == 0); assert((req->vaddr >> 48 & 0xffff) == 0);
@ -225,15 +225,15 @@ class ExecContext
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return No_Fault; return No_Fault;
} }
Fault translateInstReq(MemReqPtr req) Fault translateInstReq(MemReqPtr &req)
{ {
return dummyTranslation(req); return dummyTranslation(req);
} }
Fault translateDataReadReq(MemReqPtr req) Fault translateDataReadReq(MemReqPtr &req)
{ {
return dummyTranslation(req); return dummyTranslation(req);
} }
Fault translateDataWriteReq(MemReqPtr req) Fault translateDataWriteReq(MemReqPtr &req)
{ {
return dummyTranslation(req); return dummyTranslation(req);
} }
@ -241,7 +241,7 @@ class ExecContext
#endif #endif
template <class T> template <class T>
Fault read(MemReqPtr req, T& data) Fault read(MemReqPtr &req, T& data)
{ {
#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
if (req->flags & LOCKED) { if (req->flags & LOCKED) {
@ -254,7 +254,7 @@ class ExecContext
} }
template <class T> template <class T>
Fault write(MemReqPtr req, T& data) Fault write(MemReqPtr &req, T& data)
{ {
#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)

2
cpu/memtest/memtest.cc
View file

@ -119,7 +119,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
} }
void void
MemTest::completeRequest(MemReqPtr req, uint8_t *data) MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
{ {
switch (req->cmd) { switch (req->cmd) {
case Read: case Read:

4
cpu/memtest/memtest.hh
View file

@ -108,7 +108,7 @@ class MemTest : public BaseCPU
Statistics::Scalar<> numCopies; Statistics::Scalar<> numCopies;
// called by MemCompleteEvent::process() // called by MemCompleteEvent::process()
void completeRequest(MemReqPtr req, uint8_t *data); void completeRequest(MemReqPtr &req, uint8_t *data);
friend class MemCompleteEvent; friend class MemCompleteEvent;
}; };
@ -122,7 +122,7 @@ class MemCompleteEvent : public Event
public: public:
MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester) MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
: Event(&mainEventQueue), : Event(&mainEventQueue),
req(_req), data(_data), tester(_tester) req(_req), data(_data), tester(_tester)
{ {

4
dev/alpha_console.cc
View file

@ -73,7 +73,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
} }
Fault Fault
AlphaConsole::read(MemReqPtr req, uint8_t *data) AlphaConsole::read(MemReqPtr &req, uint8_t *data)
{ {
memset(data, 0, req->size); memset(data, 0, req->size);
uint64_t val; uint64_t val;
@ -109,7 +109,7 @@ AlphaConsole::read(MemReqPtr req, uint8_t *data)
} }
Fault Fault
AlphaConsole::write(MemReqPtr req, const uint8_t *data) AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
{ {
uint64_t val; uint64_t val;

4
dev/alpha_console.hh
View file

@ -94,8 +94,8 @@ class AlphaConsole : public MmapDevice
/** /**
* memory mapped reads and writes * memory mapped reads and writes
*/ */
virtual Fault read(MemReqPtr req, uint8_t *data); virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr req, const uint8_t *data); virtual Fault write(MemReqPtr &req, const uint8_t *data);
/** /**
* standard serialization routines for checkpointing * standard serialization routines for checkpointing