7b07b0877f
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
139 lines
4 KiB
C++
139 lines
4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEMTEST_HH__
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#define __MEMTEST_HH__
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#include "sim/sim_object.hh"
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#include "mem/mem_interface.hh"
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#include "mem/functional_mem/functional_memory.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "base/statistics.hh"
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#include "sim/sim_stats.hh"
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class MemTest : public BaseCPU
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{
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public:
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MemTest(const std::string &name,
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MemInterface *_cache_interface,
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FunctionalMemory *main_mem,
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FunctionalMemory *check_mem,
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unsigned _memorySize,
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unsigned _percentReads,
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unsigned _percentUncacheable,
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unsigned _progressInterval,
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Addr _traceAddr,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads);
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// register statistics
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virtual void regStats();
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// main simulation loop (one cycle)
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void tick();
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protected:
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class TickEvent : public Event
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{
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private:
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MemTest *cpu;
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public:
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TickEvent(MemTest *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
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void process() {cpu->tick();}
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virtual const char *description() { return "tick event"; }
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};
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TickEvent tickEvent;
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MemInterface *cacheInterface;
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FunctionalMemory *mainMem;
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FunctionalMemory *checkMem;
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ExecContext *xc;
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unsigned size; // size of testing memory region
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unsigned percentReads; // target percentage of read accesses
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unsigned percentUncacheable;
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unsigned blockSize;
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Addr blockAddrMask;
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Addr blockAddr(Addr addr)
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{
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return (addr & ~blockAddrMask);
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}
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Addr traceBlockAddr;
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Addr baseAddr1; // fix this to option
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Addr baseAddr2; // fix this to option
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Addr uncacheAddr;
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unsigned progressInterval; // frequency of progress reports
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Tick nextProgressMessage; // access # for next progress report
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Tick noResponseCycles;
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Statistics::Scalar<> numReads;
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Statistics::Scalar<> numWrites;
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Statistics::Scalar<> numCopies;
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// called by MemCompleteEvent::process()
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void completeRequest(MemReqPtr &req, uint8_t *data);
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friend class MemCompleteEvent;
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};
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class MemCompleteEvent : public Event
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{
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MemReqPtr req;
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uint8_t *data;
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MemTest *tester;
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public:
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MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
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: Event(&mainEventQueue),
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req(_req), data(_data), tester(_tester)
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{
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}
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void process();
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virtual const char *description();
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};
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#endif // __MEMTEST_HH__
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