Change MemReqPtr parameters to references.
This avoids incrementing and decrementing the MemReq reference counters on every call and return. arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: cpu/exec_context.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: dev/alpha_console.cc: dev/alpha_console.hh: Change MemReqPtr parameters to references. --HG-- extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
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7c8413db10
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7 changed files with 22 additions and 22 deletions
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@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const
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void
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void
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AlphaTlb::checkCacheability(MemReqPtr req)
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AlphaTlb::checkCacheability(MemReqPtr &req)
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{
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{
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// in Alpha, cacheability is controlled by upper-level bits of the
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// in Alpha, cacheability is controlled by upper-level bits of the
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// physical address
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// physical address
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@ -260,7 +260,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const
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Fault
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Fault
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AlphaItb::translate(MemReqPtr req) const
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AlphaItb::translate(MemReqPtr &req) const
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{
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{
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InternalProcReg *ipr = req->xc->regs.ipr;
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InternalProcReg *ipr = req->xc->regs.ipr;
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@ -425,7 +425,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
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}
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}
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Fault
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Fault
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AlphaDtb::translate(MemReqPtr req, bool write) const
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AlphaDtb::translate(MemReqPtr &req, bool write) const
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{
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{
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RegFile *regs = &req->xc->regs;
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RegFile *regs = &req->xc->regs;
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Addr pc = regs->pc;
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Addr pc = regs->pc;
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@ -70,7 +70,7 @@ class AlphaTlb : public SimObject
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return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
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return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK);
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}
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}
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static void checkCacheability(MemReqPtr req);
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static void checkCacheability(MemReqPtr &req);
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// Checkpointing
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// Checkpointing
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virtual void serialize(std::ostream &os);
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virtual void serialize(std::ostream &os);
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@ -92,7 +92,7 @@ class AlphaItb : public AlphaTlb
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AlphaItb(const std::string &name, int size);
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AlphaItb(const std::string &name, int size);
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virtual void regStats();
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virtual void regStats();
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Fault translate(MemReqPtr req) const;
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Fault translate(MemReqPtr &req) const;
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};
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};
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class AlphaDtb : public AlphaTlb
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class AlphaDtb : public AlphaTlb
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@ -118,7 +118,7 @@ class AlphaDtb : public AlphaTlb
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AlphaDtb(const std::string &name, int size);
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AlphaDtb(const std::string &name, int size);
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virtual void regStats();
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virtual void regStats();
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Fault translate(MemReqPtr req, bool write) const;
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Fault translate(MemReqPtr &req, bool write) const;
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};
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};
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#endif // __ALPHA_MEMORY_HH__
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#endif // __ALPHA_MEMORY_HH__
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@ -189,17 +189,17 @@ class ExecContext
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int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
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int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
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int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
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int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
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Fault translateInstReq(MemReqPtr req)
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Fault translateInstReq(MemReqPtr &req)
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{
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{
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return itb->translate(req);
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return itb->translate(req);
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}
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}
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Fault translateDataReadReq(MemReqPtr req)
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Fault translateDataReadReq(MemReqPtr &req)
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{
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{
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return dtb->translate(req, false);
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return dtb->translate(req, false);
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}
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}
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Fault translateDataWriteReq(MemReqPtr req)
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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{
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return dtb->translate(req, true);
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return dtb->translate(req, true);
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}
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}
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@ -214,7 +214,7 @@ class ExecContext
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int getInstAsid() { return asid; }
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int getInstAsid() { return asid; }
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int getDataAsid() { return asid; }
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int getDataAsid() { return asid; }
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Fault dummyTranslation(MemReqPtr req)
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Fault dummyTranslation(MemReqPtr &req)
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{
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{
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#if 0
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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assert((req->vaddr >> 48 & 0xffff) == 0);
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@ -225,15 +225,15 @@ class ExecContext
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return No_Fault;
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return No_Fault;
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}
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}
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Fault translateInstReq(MemReqPtr req)
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Fault translateInstReq(MemReqPtr &req)
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{
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{
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return dummyTranslation(req);
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return dummyTranslation(req);
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}
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}
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Fault translateDataReadReq(MemReqPtr req)
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Fault translateDataReadReq(MemReqPtr &req)
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{
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{
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return dummyTranslation(req);
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return dummyTranslation(req);
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}
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}
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Fault translateDataWriteReq(MemReqPtr req)
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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{
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return dummyTranslation(req);
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return dummyTranslation(req);
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}
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}
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@ -241,7 +241,7 @@ class ExecContext
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#endif
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#endif
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template <class T>
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template <class T>
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Fault read(MemReqPtr req, T& data)
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Fault read(MemReqPtr &req, T& data)
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{
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{
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#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
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#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
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if (req->flags & LOCKED) {
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if (req->flags & LOCKED) {
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@ -254,7 +254,7 @@ class ExecContext
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}
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}
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template <class T>
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template <class T>
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Fault write(MemReqPtr req, T& data)
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Fault write(MemReqPtr &req, T& data)
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{
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{
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#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
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#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
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@ -119,7 +119,7 @@ printData(ostream &os, uint8_t *data, int nbytes)
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}
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}
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void
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void
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MemTest::completeRequest(MemReqPtr req, uint8_t *data)
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MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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{
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{
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switch (req->cmd) {
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switch (req->cmd) {
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case Read:
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case Read:
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@ -108,7 +108,7 @@ class MemTest : public BaseCPU
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Statistics::Scalar<> numCopies;
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Statistics::Scalar<> numCopies;
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// called by MemCompleteEvent::process()
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// called by MemCompleteEvent::process()
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void completeRequest(MemReqPtr req, uint8_t *data);
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void completeRequest(MemReqPtr &req, uint8_t *data);
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friend class MemCompleteEvent;
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friend class MemCompleteEvent;
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};
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};
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@ -122,7 +122,7 @@ class MemCompleteEvent : public Event
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public:
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public:
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MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester)
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MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
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: Event(&mainEventQueue),
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: Event(&mainEventQueue),
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req(_req), data(_data), tester(_tester)
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req(_req), data(_data), tester(_tester)
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{
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{
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@ -73,7 +73,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
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}
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}
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Fault
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Fault
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AlphaConsole::read(MemReqPtr req, uint8_t *data)
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AlphaConsole::read(MemReqPtr &req, uint8_t *data)
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{
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{
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memset(data, 0, req->size);
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memset(data, 0, req->size);
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uint64_t val;
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uint64_t val;
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@ -109,7 +109,7 @@ AlphaConsole::read(MemReqPtr req, uint8_t *data)
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}
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}
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Fault
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Fault
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AlphaConsole::write(MemReqPtr req, const uint8_t *data)
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AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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{
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{
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uint64_t val;
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uint64_t val;
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@ -94,8 +94,8 @@ class AlphaConsole : public MmapDevice
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/**
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/**
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* memory mapped reads and writes
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* memory mapped reads and writes
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*/
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*/
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virtual Fault read(MemReqPtr req, uint8_t *data);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr req, const uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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/**
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* standard serialization routines for checkpointing
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* standard serialization routines for checkpointing
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