AtomicSimpleCPU with a cache now runs the hello world! test program.
Need to clean up a bunch of flags/hacks in the code. Then onto Timming mode. Functional accesses also work properly, although not exactly how we wanted them. I'll need to clean that up as well. src/cpu/simple/atomic.cc: Atomic CPU needs to set thread context so stats work in cache. Temporarily just use CPU=0 ThreadID=0 src/mem/cache/cache_impl.hh: Need to return success/failure properly still Physical memory object doesn't assert SATISFIED anymore, need to remove that flag src/mem/cache/tags/lru.cc: Doesn't work if the REQ doesn't set it's ASID. Temporary fix use 0 always --HG-- extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050
This commit is contained in:
parent
1bdc65b00f
commit
7a49298134
3 changed files with 12 additions and 3 deletions
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@ -124,15 +124,18 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
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// @todo fix me and get the real cpu id & thread number!!!
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// @todo fix me and get the real cpu id & thread number!!!
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ifetch_req = new Request();
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ifetch_req = new Request();
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ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
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ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
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ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
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ifetch_pkt->dataStatic(&inst);
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ifetch_pkt->dataStatic(&inst);
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data_read_req = new Request();
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data_read_req = new Request();
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data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
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data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
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data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
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Packet::Broadcast);
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Packet::Broadcast);
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data_read_pkt->dataStatic(&dataReg);
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data_read_pkt->dataStatic(&dataReg);
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data_write_req = new Request();
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data_write_req = new Request();
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data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
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data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
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data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
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Packet::Broadcast);
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Packet::Broadcast);
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}
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}
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10
src/mem/cache/cache_impl.hh
vendored
10
src/mem/cache/cache_impl.hh
vendored
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@ -82,6 +82,8 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
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if (isCpuSide)
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if (isCpuSide)
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{
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{
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probe(pkt, true);
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probe(pkt, true);
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//TEMP ALWAYS SUCCES FOR NOW
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pkt->result = Packet::Success;
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}
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}
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else
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else
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{
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{
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@ -101,7 +103,11 @@ doFunctionalAccess(Packet *pkt, bool isCpuSide)
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{
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{
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if (isCpuSide)
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if (isCpuSide)
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{
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{
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//TEMP USE CPU?THREAD 0 0
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pkt->req->setThreadContext(0,0);
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probe(pkt, true);
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probe(pkt, true);
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//TEMP ALWAYS SUCCESFUL FOR NOW
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pkt->result = Packet::Success;
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}
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}
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else
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else
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{
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{
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@ -594,12 +600,12 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
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lat = memSidePort->sendAtomic(busPkt);
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lat = memSidePort->sendAtomic(busPkt);
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if (!(busPkt->flags & SATISFIED)) {
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/* if (!(busPkt->flags & SATISFIED)) {
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// blocked at a higher level, just return
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// blocked at a higher level, just return
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return 0;
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return 0;
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}
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}
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misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
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*/ misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
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CacheBlk::State old_state = (blk) ? blk->status : 0;
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CacheBlk::State old_state = (blk) ? blk->status : 0;
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tags->handleFill(blk, busPkt,
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tags->handleFill(blk, busPkt,
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2
src/mem/cache/tags/lru.cc
vendored
2
src/mem/cache/tags/lru.cc
vendored
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@ -188,7 +188,7 @@ LRUBlk*
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LRU::findBlock(Packet * &pkt, int &lat)
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LRU::findBlock(Packet * &pkt, int &lat)
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{
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{
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Addr addr = pkt->getAddr();
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Addr addr = pkt->getAddr();
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int asid = pkt->req->getAsid();
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int asid = 0;//pkt->req->getAsid();
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Addr tag = extractTag(addr);
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Addr tag = extractTag(addr);
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unsigned set = extractSet(addr);
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unsigned set = extractSet(addr);
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