From 7a4929813423c6f72827c58453cb9bd591f1801c Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Fri, 30 Jun 2006 17:21:58 -0400
Subject: [PATCH] AtomicSimpleCPU with a cache now runs the hello world! test
 program. Need to clean up a bunch of flags/hacks in the code.  Then onto
 Timming mode.

Functional accesses also work properly, although not exactly how we wanted them.  I'll need to clean that up as well.

src/cpu/simple/atomic.cc:
    Atomic CPU needs to set thread context so stats work in cache.  Temporarily just use CPU=0 ThreadID=0
src/mem/cache/cache_impl.hh:
    Need to return success/failure properly still
    Physical memory object doesn't assert SATISFIED anymore, need to remove that flag
src/mem/cache/tags/lru.cc:
    Doesn't work if the REQ doesn't set it's ASID.  Temporary fix use 0 always

--HG--
extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050
---
 src/cpu/simple/atomic.cc    |  3 +++
 src/mem/cache/cache_impl.hh | 10 ++++++++--
 src/mem/cache/tags/lru.cc   |  2 +-
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index be6f421b3..b7202cbbb 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -124,15 +124,18 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
 
     // @todo fix me and get the real cpu id & thread number!!!
     ifetch_req = new Request();
+    ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
     ifetch_pkt->dataStatic(&inst);
 
     data_read_req = new Request();
+    data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
     data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
                                Packet::Broadcast);
     data_read_pkt->dataStatic(&dataReg);
 
     data_write_req = new Request();
+    data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
     data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
                                 Packet::Broadcast);
 }
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 0cb33461b..aae5cbf01 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -82,6 +82,8 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
     if (isCpuSide)
     {
         probe(pkt, true);
+        //TEMP ALWAYS SUCCES FOR NOW
+        pkt->result = Packet::Success;
     }
     else
     {
@@ -101,7 +103,11 @@ doFunctionalAccess(Packet *pkt, bool isCpuSide)
 {
     if (isCpuSide)
     {
+        //TEMP USE CPU?THREAD 0 0
+        pkt->req->setThreadContext(0,0);
         probe(pkt, true);
+        //TEMP ALWAYS SUCCESFUL FOR NOW
+        pkt->result = Packet::Success;
     }
     else
     {
@@ -594,12 +600,12 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 
                 lat = memSidePort->sendAtomic(busPkt);
 
-                if (!(busPkt->flags & SATISFIED)) {
+/*		if (!(busPkt->flags & SATISFIED)) {
                     // blocked at a higher level, just return
                     return 0;
                 }
 
-                misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+*/		misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
 
                 CacheBlk::State old_state = (blk) ? blk->status : 0;
                 tags->handleFill(blk, busPkt,
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index b7259bd3a..556025a3a 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -188,7 +188,7 @@ LRUBlk*
 LRU::findBlock(Packet * &pkt, int &lat)
 {
     Addr addr = pkt->getAddr();
-    int asid = pkt->req->getAsid();
+    int asid = 0;//pkt->req->getAsid();
 
     Addr tag = extractTag(addr);
     unsigned set = extractSet(addr);