Add initial support for IDE
--HG-- extra : convert_revision : e07dc6c87b0b692d428b541d4032fcf82996ef15
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523
dev/ide_ctrl.cc
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523
dev/ide_ctrl.cc
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cstddef>
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#include <cstdlib>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/intr_control.hh"
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#include "dev/dma.hh"
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#include "dev/pcireg.h"
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#include "dev/pciconfigall.hh"
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#include "dev/ide_disk.hh"
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#include "dev/ide_ctrl.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/bus/dma_interface.hh"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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using namespace std;
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////
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// Initialization and destruction
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////
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IdeController::IdeController(const string &name, IntrControl *ic,
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const vector<IdeDisk *> &new_disks,
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MemoryController *mmu, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t, uint32_t bus_num,
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uint32_t dev_num, uint32_t func_num,
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Bus *host_bus, HierParams *hier)
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: PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
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{
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// put back pointer into Tsunami
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tsunami->disk_controller = this;
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// initialize the PIO interface addresses
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pri_cmd_addr = 0;
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pri_cmd_size = BARSize[0];
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pri_ctrl_addr = 0;
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pri_ctrl_size = BARSize[1];
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sec_cmd_addr = 0;
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sec_cmd_size = BARSize[2];
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sec_ctrl_addr = 0;
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sec_ctrl_size = BARSize[3];
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// initialize the bus master interface (BMI) address to be configured
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// via PCI
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bmi_addr = 0;
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bmi_size = BARSize[4];
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// zero out all of the registers
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memset(regs, 0, sizeof(regs));
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memset(pci_regs, 0, sizeof(pci_regs));
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// setup initial values
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*(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels
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*(uint8_t *)®s[BMI + BMIS0] = 0x60;
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*(uint8_t *)®s[BMI + BMIS1] = 0x60;
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// reset all internal variables
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io_enabled = false;
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bm_enabled = false;
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memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
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// create the PIO and DMA interfaces
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if (host_bus) {
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pioInterface = newPioInterface(name, hier, host_bus, this,
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&IdeController::cacheAccess);
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dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
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host_bus, 1);
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}
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// setup the disks attached to controller
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memset(disks, 0, sizeof(IdeDisk *) * 4);
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if (new_disks.size() > 3)
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panic("IDE controllers support a maximum of 4 devices attached!\n");
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for (int i = 0; i < new_disks.size(); i++) {
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disks[i] = new_disks[i];
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disks[i]->setController(this);
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}
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}
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IdeController::~IdeController()
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{
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for (int i = 0; i < 4; i++)
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if (disks[i])
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delete disks[i];
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}
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////
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// Bus timing and bus access functions
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////
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Tick
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IdeController::cacheAccess(MemReqPtr &req)
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{
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// @todo Add more accurate timing to cache access
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return curTick + 1000;
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}
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////
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// Read and write handling
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////
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void
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IdeController::ReadConfig(int offset, int size, uint8_t *data)
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{
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Addr origOffset = offset;
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if (offset < PCI_DEVICE_SPECIFIC) {
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PciDev::ReadConfig(offset, size, data);
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} else {
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if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
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offset -= PCI_IDE_TIMING;
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offset += IDETIM;
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if ((offset + size) > (IDETIM + 4))
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panic("PCI read of IDETIM with invalid size\n");
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} else if (offset == PCI_SLAVE_TIMING) {
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offset -= PCI_SLAVE_TIMING;
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offset += SIDETIM;
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if ((offset + size) > (SIDETIM + 1))
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panic("PCI read of SIDETIM with invalid size\n");
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} else if (offset == PCI_UDMA33_CTRL) {
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offset -= PCI_UDMA33_CTRL;
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offset += UDMACTL;
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if ((offset + size) > (UDMACTL + 1))
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panic("PCI read of UDMACTL with invalid size\n");
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} else if (offset >= PCI_UDMA33_TIMING &&
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offset < (PCI_UDMA33_TIMING + 2)) {
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offset -= PCI_UDMA33_TIMING;
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offset += UDMATIM;
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if ((offset + size) > (UDMATIM + 2))
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panic("PCI read of UDMATIM with invalid size\n");
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} else {
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panic("PCI read of unimplemented register: %x\n", offset);
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}
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memcpy((void *)data, (void *)&pci_regs[offset], size);
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}
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DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
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origOffset, offset, size, *(uint32_t *)data);
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}
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void
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IdeController::WriteConfig(int offset, int size, uint32_t data)
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{
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DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
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offset, size, data);
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// do standard write stuff if in standard PCI space
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if (offset < PCI_DEVICE_SPECIFIC) {
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PciDev::WriteConfig(offset, size, data);
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} else {
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if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
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offset -= PCI_IDE_TIMING;
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offset += IDETIM;
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if ((offset + size) > (IDETIM + 4))
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panic("PCI write to IDETIM with invalid size\n");
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} else if (offset == PCI_SLAVE_TIMING) {
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offset -= PCI_SLAVE_TIMING;
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offset += SIDETIM;
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if ((offset + size) > (SIDETIM + 1))
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panic("PCI write to SIDETIM with invalid size\n");
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} else if (offset == PCI_UDMA33_CTRL) {
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offset -= PCI_UDMA33_CTRL;
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offset += UDMACTL;
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if ((offset + size) > (UDMACTL + 1))
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panic("PCI write to UDMACTL with invalid size\n");
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} else if (offset >= PCI_UDMA33_TIMING &&
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offset < (PCI_UDMA33_TIMING + 2)) {
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offset -= PCI_UDMA33_TIMING;
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offset += UDMATIM;
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if ((offset + size) > (UDMATIM + 2))
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panic("PCI write to UDMATIM with invalid size\n");
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} else {
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panic("PCI write to unimplemented register: %x\n", offset);
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}
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memcpy((void *)&pci_regs[offset], (void *)&data, size);
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}
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if (offset == PCI_COMMAND) {
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if (config.data[offset] & IOSE)
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io_enabled = true;
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else
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io_enabled = false;
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if (config.data[offset] & BME)
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bm_enabled = true;
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else
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bm_enabled = false;
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} else if (data != 0xffffffff) {
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switch (offset) {
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case PCI0_BASE_ADDR0:
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pri_cmd_addr = BARAddrs[0];
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if (pioInterface)
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pioInterface->addAddrRange(pri_cmd_addr,
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pri_cmd_addr + pri_cmd_size - 1);
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pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000) & PA_IMPL_MASK);
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break;
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case PCI0_BASE_ADDR1:
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pri_ctrl_addr = BARAddrs[1];
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if (pioInterface)
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pioInterface->addAddrRange(pri_ctrl_addr,
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pri_ctrl_addr + pri_ctrl_size - 1);
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pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK);
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break;
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case PCI0_BASE_ADDR2:
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sec_cmd_addr = BARAddrs[2];
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if (pioInterface)
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pioInterface->addAddrRange(sec_cmd_addr,
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sec_cmd_addr + sec_cmd_size - 1);
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sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000) & PA_IMPL_MASK);
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break;
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case PCI0_BASE_ADDR3:
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sec_ctrl_addr = BARAddrs[3];
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if (pioInterface)
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pioInterface->addAddrRange(sec_ctrl_addr,
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sec_ctrl_addr + sec_ctrl_size - 1);
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sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK);
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break;
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case PCI0_BASE_ADDR4:
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bmi_addr = BARAddrs[4];
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if (pioInterface)
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pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
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bmi_addr = ((bmi_addr | 0xf0000000000) & PA_IMPL_MASK);
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break;
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}
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}
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}
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Fault
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IdeController::read(MemReqPtr &req, uint8_t *data)
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{
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Addr offset = getOffset(req->paddr);
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if (!io_enabled)
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return No_Fault;
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// sanity check the size (allows byte, word, or dword access)
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if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
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req->size != sizeof(uint32_t))
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panic("IDE controller read of invalid size: %#x\n", req->size);
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DPRINTF(IdeCtrl, "IDE default read from offset: %#x size: %#x data: %#x\n",
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offset, req->size, *(uint32_t *)®s[offset]);
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// copy the data from the control registers
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memcpy((void *)data, ®s[offset], req->size);
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return No_Fault;
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}
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Fault
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IdeController::write(MemReqPtr &req, const uint8_t *data)
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{
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int disk = 0; // selected disk index
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uint8_t oldVal, newVal;
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Addr offset = getOffset(req->paddr);
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if (!io_enabled)
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return No_Fault;
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if (offset >= BMI && !bm_enabled)
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return No_Fault;
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switch (offset) {
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// Bus master IDE command register
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case (BMI + BMIC1):
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case (BMI + BMIC0):
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if (req->size != sizeof(uint8_t))
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panic("Invalid BMIC write size: %x\n", req->size);
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// select the current disk based on DEV bit
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disk = getDisk(offset);
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oldVal = regs[offset];
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newVal = *data;
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// if a DMA transfer is in progress, R/W control cannot change
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if (oldVal & SSBM) {
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if ((oldVal & RWCON) ^ (newVal & RWCON)) {
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(oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
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}
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}
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// see if the start/stop bit is being changed
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if ((oldVal & SSBM) ^ (newVal & SSBM)) {
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if (oldVal & SSBM) {
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// stopping DMA transfer
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DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
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// clear the BMIDEA bit
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regs[offset + 0x2] &= ~BMIDEA;
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if (disks[disk] == NULL)
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panic("DMA stop for disk %d which does not exist\n", disk);
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// inform the disk of the DMA transfer abort
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disks[disk]->dmaStop();
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} else {
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// starting DMA transfer
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DPRINTF(IdeCtrl, "Starting DMA transfer\n");
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// set the BMIDEA bit
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regs[offset + 0x2] |= BMIDEA;
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if (disks[disk] == NULL)
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panic("DMA start for disk %d which does not exist\n",
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disk);
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// inform the disk of the DMA transfer start
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disks[disk]->dmaStart();
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}
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}
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// update the register value
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regs[offset] = newVal;
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break;
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// Bus master IDE status register
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case (BMI + BMIS0):
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case (BMI + BMIS1):
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if (req->size != sizeof(uint8_t))
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panic("Invalid BMIS write size: %x\n", req->size);
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oldVal = regs[offset];
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newVal = *data;
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|
|
||||||
|
// the BMIDEA bit is RO
|
||||||
|
newVal |= (oldVal & BMIDEA);
|
||||||
|
|
||||||
|
// to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
|
||||||
|
if ((oldVal & IDEINTS) && (newVal & IDEINTS))
|
||||||
|
newVal &= ~IDEINTS; // clear the interrupt?
|
||||||
|
else
|
||||||
|
(oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
|
||||||
|
|
||||||
|
if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
|
||||||
|
newVal &= ~IDEDMAE;
|
||||||
|
else
|
||||||
|
(oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
|
||||||
|
|
||||||
|
regs[offset] = newVal;
|
||||||
|
break;
|
||||||
|
|
||||||
|
// Bus master IDE descriptor table pointer register
|
||||||
|
case (BMI + BMIDTP0):
|
||||||
|
case (BMI + BMIDTP1):
|
||||||
|
if (req->size != sizeof(uint32_t))
|
||||||
|
panic("Invalid BMIDTP write size: %x\n", req->size);
|
||||||
|
|
||||||
|
*(uint32_t *)®s[offset] = *(uint32_t *)data & ~0x3;
|
||||||
|
break;
|
||||||
|
|
||||||
|
// Write the data word in the command register block
|
||||||
|
case (CMD1 + IDE_DATA_OFFSET):
|
||||||
|
case (CMD0 + IDE_DATA_OFFSET):
|
||||||
|
if (req->size != sizeof(uint16_t))
|
||||||
|
panic("Invalid command block data write size: %x\n", req->size);
|
||||||
|
|
||||||
|
break;
|
||||||
|
|
||||||
|
// Write the command byte in command register block
|
||||||
|
case (CMD1 + IDE_COMMAND_OFFSET):
|
||||||
|
case (CMD0 + IDE_COMMAND_OFFSET):
|
||||||
|
if (req->size != sizeof(uint8_t))
|
||||||
|
panic("Invalid command block command write size: %x\n", req->size);
|
||||||
|
|
||||||
|
// select the disk based on the DEV bit
|
||||||
|
disk = getDisk(offset);
|
||||||
|
|
||||||
|
if (cmd_in_progress[disk])
|
||||||
|
panic("Command on disk %d already in progress!\n", disk);
|
||||||
|
if (disks[disk] == NULL)
|
||||||
|
panic("Specified disk %d does not exist!\n", disk);
|
||||||
|
|
||||||
|
cmd_in_progress[disk] = true;
|
||||||
|
|
||||||
|
// write to both the command/status and alternate status
|
||||||
|
regs[offset] = *data;
|
||||||
|
regs[offset + 3] = *data;
|
||||||
|
|
||||||
|
// issue the command to the disk
|
||||||
|
if (disk < 2)
|
||||||
|
disks[disk]->startIO(®s[CMD0], ®s[BMI + BMIDTP0]);
|
||||||
|
else
|
||||||
|
disks[disk]->startIO(®s[CMD1], ®s[BMI + BMIDTP1]);
|
||||||
|
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
|
||||||
|
req->size != sizeof(uint32_t))
|
||||||
|
panic("IDE controller write of invalid write size: %x\n",
|
||||||
|
req->size);
|
||||||
|
|
||||||
|
DPRINTF(IdeCtrl, "IDE default write offset: %#x size: %#x data: %#x\n",
|
||||||
|
offset, req->size, *(uint32_t *)data);
|
||||||
|
|
||||||
|
// do a default copy of data into the registers
|
||||||
|
memcpy((void *)®s[offset], data, req->size);
|
||||||
|
}
|
||||||
|
|
||||||
|
return No_Fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
////
|
||||||
|
// Serialization
|
||||||
|
////
|
||||||
|
|
||||||
|
void
|
||||||
|
IdeController::serialize(std::ostream &os)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
IdeController::unserialize(Checkpoint *cp, const std::string §ion)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||||
|
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
|
||||||
|
|
||||||
|
SimObjectParam<IntrControl *> intr_ctrl;
|
||||||
|
SimObjectVectorParam<IdeDisk *> disks;
|
||||||
|
SimObjectParam<MemoryController *> mmu;
|
||||||
|
SimObjectParam<PciConfigAll *> configspace;
|
||||||
|
SimObjectParam<PciConfigData *> configdata;
|
||||||
|
SimObjectParam<Tsunami *> tsunami;
|
||||||
|
Param<uint32_t> pci_bus;
|
||||||
|
Param<uint32_t> pci_dev;
|
||||||
|
Param<uint32_t> pci_func;
|
||||||
|
SimObjectParam<Bus *> host_bus;
|
||||||
|
SimObjectParam<HierParams *> hier;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
|
||||||
|
|
||||||
|
INIT_PARAM(intr_ctrl, "Interrupt Controller"),
|
||||||
|
INIT_PARAM(disks, "IDE disks attached to this controller"),
|
||||||
|
INIT_PARAM(mmu, "Memory controller"),
|
||||||
|
INIT_PARAM(configspace, "PCI Configspace"),
|
||||||
|
INIT_PARAM(configdata, "PCI Config data"),
|
||||||
|
INIT_PARAM(tsunami, "Tsunami chipset pointer"),
|
||||||
|
INIT_PARAM(pci_bus, "PCI bus ID"),
|
||||||
|
INIT_PARAM(pci_dev, "PCI device number"),
|
||||||
|
INIT_PARAM(pci_func, "PCI function code"),
|
||||||
|
INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL),
|
||||||
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(IdeController)
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(IdeController)
|
||||||
|
{
|
||||||
|
return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
|
||||||
|
configspace, configdata, tsunami, pci_bus,
|
||||||
|
pci_dev, pci_func, host_bus, hier);
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("IdeController", IdeController)
|
||||||
|
|
||||||
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
257
dev/ide_ctrl.hh
Normal file
257
dev/ide_ctrl.hh
Normal file
|
@ -0,0 +1,257 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @file
|
||||||
|
* Simple PCI IDE controller with bus mastering capability
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __IDE_CTRL_HH__
|
||||||
|
#define __IDE_CTRL_HH__
|
||||||
|
|
||||||
|
#include "dev/pcidev.hh"
|
||||||
|
#include "dev/pcireg.h"
|
||||||
|
#include "dev/io_device.hh"
|
||||||
|
|
||||||
|
#define CMD0 0x00 // Channel 0 command block offset
|
||||||
|
#define CTRL0 0x08 // Channel 0 control block offset
|
||||||
|
#define CMD1 0x0c // Channel 1 command block offset
|
||||||
|
#define CTRL1 0x14 // Channel 1 control block offset
|
||||||
|
#define BMI 0x18 // Bus master IDE offset
|
||||||
|
|
||||||
|
#define BMIC0 0x0 // Bus master IDE command register
|
||||||
|
#define BMIS0 0x2 // Bus master IDE status register
|
||||||
|
#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
|
||||||
|
#define BMIC1 0x8 // Bus master IDE command register
|
||||||
|
#define BMIS1 0xa // Bus master IDE status register
|
||||||
|
#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
|
||||||
|
|
||||||
|
// Bus master IDE command register bit fields
|
||||||
|
#define RWCON 0x08 // Bus master read/write control
|
||||||
|
#define SSBM 0x01 // Start/stop bus master
|
||||||
|
|
||||||
|
// Bus master IDE status register bit fields
|
||||||
|
#define DMA1CAP 0x40 // Drive 1 DMA capable
|
||||||
|
#define DMA0CAP 0x20 // Drive 0 DMA capable
|
||||||
|
#define IDEINTS 0x04 // IDE Interrupt Status
|
||||||
|
#define IDEDMAE 0x02 // IDE DMA error
|
||||||
|
#define BMIDEA 0x01 // Bus master IDE active
|
||||||
|
|
||||||
|
// IDE Command byte fields
|
||||||
|
// Taken from include/linux/ide.h
|
||||||
|
#define IDE_DATA_OFFSET (0)
|
||||||
|
#define IDE_ERROR_OFFSET (1)
|
||||||
|
#define IDE_NSECTOR_OFFSET (2)
|
||||||
|
#define IDE_SECTOR_OFFSET (3)
|
||||||
|
#define IDE_LCYL_OFFSET (4)
|
||||||
|
#define IDE_HCYL_OFFSET (5)
|
||||||
|
#define IDE_SELECT_OFFSET (6)
|
||||||
|
#define IDE_STATUS_OFFSET (7)
|
||||||
|
#define IDE_CONTROL_OFFSET (8)
|
||||||
|
#define IDE_IRQ_OFFSET (9)
|
||||||
|
|
||||||
|
#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
|
||||||
|
#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
|
||||||
|
|
||||||
|
// PCI device specific register byte offsets
|
||||||
|
#define PCI_IDE_TIMING 0x40
|
||||||
|
#define PCI_SLAVE_TIMING 0x44
|
||||||
|
#define PCI_UDMA33_CTRL 0x48
|
||||||
|
#define PCI_UDMA33_TIMING 0x4a
|
||||||
|
|
||||||
|
#define IDETIM (0)
|
||||||
|
#define SIDETIM (4)
|
||||||
|
#define UDMACTL (5)
|
||||||
|
#define UDMATIM (6)
|
||||||
|
|
||||||
|
// PCI Command bit fields
|
||||||
|
#define BME 0x04 // Bus master function enable
|
||||||
|
#define IOSE 0x01 // I/O space enable
|
||||||
|
|
||||||
|
class IntrControl;
|
||||||
|
class IdeDisk;
|
||||||
|
class PciConfigAll;
|
||||||
|
class Tsunami;
|
||||||
|
class PhysicalMemory;
|
||||||
|
class BaseInterface;
|
||||||
|
class HierParams;
|
||||||
|
class Bus;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Device model for an Intel PIIX4 IDE controller
|
||||||
|
*/
|
||||||
|
|
||||||
|
class IdeController : public PciDev
|
||||||
|
{
|
||||||
|
private:
|
||||||
|
/** Primary command block registers */
|
||||||
|
Addr pri_cmd_addr;
|
||||||
|
Addr pri_cmd_size;
|
||||||
|
/** Primary control block registers */
|
||||||
|
Addr pri_ctrl_addr;
|
||||||
|
Addr pri_ctrl_size;
|
||||||
|
/** Secondary command block registers */
|
||||||
|
Addr sec_cmd_addr;
|
||||||
|
Addr sec_cmd_size;
|
||||||
|
/** Secondary control block registers */
|
||||||
|
Addr sec_ctrl_addr;
|
||||||
|
Addr sec_ctrl_size;
|
||||||
|
/** Bus master interface (BMI) registers */
|
||||||
|
Addr bmi_addr;
|
||||||
|
Addr bmi_size;
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Registers used for programmed I/O and bus master interface */
|
||||||
|
uint8_t regs[40];
|
||||||
|
/** Registers used in PCI configuration */
|
||||||
|
uint8_t pci_regs[8];
|
||||||
|
|
||||||
|
// Internal management variables
|
||||||
|
bool io_enabled;
|
||||||
|
bool bm_enabled;
|
||||||
|
bool cmd_in_progress[4];
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Pointer to the chipset */
|
||||||
|
Tsunami *tsunami;
|
||||||
|
/** IDE disks connected to controller */
|
||||||
|
IdeDisk *disks[4];
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Get offset into register file from access address */
|
||||||
|
Addr getOffset(const Addr &addr) {
|
||||||
|
Addr offset = addr;
|
||||||
|
|
||||||
|
if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
|
||||||
|
offset -= pri_cmd_addr;
|
||||||
|
offset += CMD0;
|
||||||
|
} else if (addr >= pri_ctrl_addr &&
|
||||||
|
addr < (pri_ctrl_addr + pri_ctrl_size)) {
|
||||||
|
offset -= pri_ctrl_addr;
|
||||||
|
offset += CTRL0;
|
||||||
|
} else if (addr >= sec_cmd_addr &&
|
||||||
|
addr < (sec_cmd_addr + sec_cmd_size)) {
|
||||||
|
offset -= sec_cmd_addr;
|
||||||
|
offset += CMD1;
|
||||||
|
} else if (addr >= sec_ctrl_addr &&
|
||||||
|
addr < (sec_ctrl_addr + sec_ctrl_size)) {
|
||||||
|
offset -= sec_ctrl_addr;
|
||||||
|
offset += CTRL1;
|
||||||
|
} else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
|
||||||
|
offset -= bmi_addr;
|
||||||
|
offset += BMI;
|
||||||
|
} else {
|
||||||
|
panic("IDE controller access to invalid address: %#x\n", addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
return offset;
|
||||||
|
};
|
||||||
|
/** Select the disk based on the register offset */
|
||||||
|
int getDisk(const Addr &offset) {
|
||||||
|
int disk = 0;
|
||||||
|
|
||||||
|
// If the offset is in the channel 1 range, disks are 2 or 3
|
||||||
|
if (offset >= CMD1 && offset < BMI && offset >= (BMI + BMIC1))
|
||||||
|
disk += 2;
|
||||||
|
|
||||||
|
if (disk < 2) {
|
||||||
|
if (regs[CMD0 + IDE_STATUS_OFFSET] & 0x10)
|
||||||
|
disk += 1;
|
||||||
|
} else {
|
||||||
|
if (regs[CMD1 + IDE_STATUS_OFFSET] & 0x10)
|
||||||
|
disk += 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return disk;
|
||||||
|
};
|
||||||
|
|
||||||
|
public:
|
||||||
|
/**
|
||||||
|
* Constructs and initializes this controller.
|
||||||
|
* @param name The name of this controller.
|
||||||
|
* @param ic The interrupt controller.
|
||||||
|
* @param mmu The memory controller
|
||||||
|
* @param cf PCI config space
|
||||||
|
* @param cd PCI config data
|
||||||
|
* @param bus_num The PCI bus number
|
||||||
|
* @param dev_num The PCI device number
|
||||||
|
* @param func_num The PCI function number
|
||||||
|
* @param host_bus The host bus to connect to
|
||||||
|
* @param hier The hierarchy parameters
|
||||||
|
*/
|
||||||
|
IdeController(const std::string &name, IntrControl *ic,
|
||||||
|
const vector<IdeDisk *> &new_disks,
|
||||||
|
MemoryController *mmu, PciConfigAll *cf,
|
||||||
|
PciConfigData *cd, Tsunami *t,
|
||||||
|
uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
|
||||||
|
Bus *host_bus, HierParams *hier);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Deletes the connected devices.
|
||||||
|
*/
|
||||||
|
~IdeController();
|
||||||
|
|
||||||
|
virtual void WriteConfig(int offset, int size, uint32_t data);
|
||||||
|
virtual void ReadConfig(int offset, int size, uint8_t *data);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Read a done field for a given target.
|
||||||
|
* @param req Contains the address of the field to read.
|
||||||
|
* @param data Return the field read.
|
||||||
|
* @return The fault condition of the access.
|
||||||
|
*/
|
||||||
|
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Write to the mmapped I/O control registers.
|
||||||
|
* @param req Contains the address to write to.
|
||||||
|
* @param data The data to write.
|
||||||
|
* @return The fault condition of the access.
|
||||||
|
*/
|
||||||
|
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Cache access timing specific to device
|
||||||
|
* @param req Memory request
|
||||||
|
*/
|
||||||
|
Tick cacheAccess(MemReqPtr &req);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Serialize this object to the given output stream.
|
||||||
|
* @param os The stream to serialize to.
|
||||||
|
*/
|
||||||
|
virtual void serialize(std::ostream &os);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Reconstruct the state of this object from a checkpoint.
|
||||||
|
* @param cp The checkpoint use.
|
||||||
|
* @param section The section name of this object
|
||||||
|
*/
|
||||||
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
};
|
||||||
|
#endif // __IDE_CTRL_HH_
|
92
dev/ide_disk.cc
Normal file
92
dev/ide_disk.cc
Normal file
|
@ -0,0 +1,92 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @file
|
||||||
|
* Device model implementation for an IDE disk
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <cerrno>
|
||||||
|
#include <cstring>
|
||||||
|
#include <deque>
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include "base/cprintf.hh" // csprintf
|
||||||
|
#include "base/trace.hh"
|
||||||
|
#include "dev/disk_image.hh"
|
||||||
|
#include "dev/ide_disk.hh"
|
||||||
|
#include "sim/builder.hh"
|
||||||
|
#include "sim/sim_object.hh"
|
||||||
|
#include "sim/universe.hh"
|
||||||
|
|
||||||
|
using namespace std;
|
||||||
|
|
||||||
|
IdeDisk::IdeDisk(const string &name, DiskImage *img, int delay)
|
||||||
|
: SimObject(name), ctrl(NULL), image(img)
|
||||||
|
{
|
||||||
|
diskDelay = delay * ticksPerSecond / 1000;
|
||||||
|
}
|
||||||
|
|
||||||
|
IdeDisk::~IdeDisk()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
IdeDisk::serialize(ostream &os)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
IdeDisk::unserialize(Checkpoint *cp, const string §ion)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||||
|
|
||||||
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
|
||||||
|
|
||||||
|
SimObjectParam<DiskImage *> image;
|
||||||
|
Param<int> disk_delay;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
|
||||||
|
|
||||||
|
INIT_PARAM(image, "Disk image"),
|
||||||
|
INIT_PARAM_DFLT(disk_delay, "Fixed disk delay in milliseconds", 0)
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
|
||||||
|
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(IdeDisk)
|
||||||
|
{
|
||||||
|
return new IdeDisk(getInstanceName(), image, disk_delay);
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
|
||||||
|
|
||||||
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
99
dev/ide_disk.hh
Normal file
99
dev/ide_disk.hh
Normal file
|
@ -0,0 +1,99 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @file
|
||||||
|
* Device model for an IDE disk
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __IDE_DISK_HH__
|
||||||
|
#define __IDE_DISK_HH__
|
||||||
|
|
||||||
|
#include "dev/io_device.hh"
|
||||||
|
|
||||||
|
class DiskImage;
|
||||||
|
class IdeController;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* SCSI Disk device model
|
||||||
|
*/
|
||||||
|
class IdeDisk : public SimObject
|
||||||
|
{
|
||||||
|
protected:
|
||||||
|
/** The IDE controller for this disk. */
|
||||||
|
IdeController *ctrl;
|
||||||
|
/** The image that contains the data of this disk. */
|
||||||
|
DiskImage *image;
|
||||||
|
|
||||||
|
protected:
|
||||||
|
/** The disk delay in milliseconds. */
|
||||||
|
int diskDelay;
|
||||||
|
|
||||||
|
public:
|
||||||
|
/**
|
||||||
|
* Create and initialize this Disk.
|
||||||
|
* @param name The name of this disk.
|
||||||
|
* @param img The disk image of this disk.
|
||||||
|
* @param disk_delay The disk delay in milliseconds
|
||||||
|
*/
|
||||||
|
IdeDisk(const std::string &name, DiskImage *img, int disk_delay);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Delete the data buffer.
|
||||||
|
*/
|
||||||
|
~IdeDisk();
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Set the controller for this device
|
||||||
|
* @param c The IDE controller
|
||||||
|
*/
|
||||||
|
void setController(IdeController *c) {
|
||||||
|
if (ctrl) panic("Cannot change the controller once set!\n");
|
||||||
|
ctrl = c;
|
||||||
|
}
|
||||||
|
|
||||||
|
void startIO(uint8_t *cmdBlk, uint8_t *prdPtr) {};
|
||||||
|
|
||||||
|
void dmaStart() {};
|
||||||
|
void dmaStop() {};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Serialize this object to the given output stream.
|
||||||
|
* @param os The stream to serialize to.
|
||||||
|
*/
|
||||||
|
void serialize(std::ostream &os);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Reconstruct the state of this object from a checkpoint.
|
||||||
|
* @param cp The checkpoint to use.
|
||||||
|
* @param section The section name describing this object.
|
||||||
|
*/
|
||||||
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
#endif // __IDE_DISK_HH__
|
|
@ -33,7 +33,7 @@
|
||||||
#include "cpu/intr_control.hh"
|
#include "cpu/intr_control.hh"
|
||||||
#include "dev/console.hh"
|
#include "dev/console.hh"
|
||||||
#include "dev/etherdev.hh"
|
#include "dev/etherdev.hh"
|
||||||
#include "dev/adaptec_ctrl.hh"
|
#include "dev/ide_ctrl.hh"
|
||||||
#include "dev/tlaser_clock.hh"
|
#include "dev/tlaser_clock.hh"
|
||||||
#include "dev/tsunami_cchip.hh"
|
#include "dev/tsunami_cchip.hh"
|
||||||
#include "dev/tsunami_pchip.hh"
|
#include "dev/tsunami_pchip.hh"
|
||||||
|
|
|
@ -37,7 +37,7 @@
|
||||||
|
|
||||||
#include "dev/platform.hh"
|
#include "dev/platform.hh"
|
||||||
|
|
||||||
class AdaptecController;
|
class IdeController;
|
||||||
class TlaserClock;
|
class TlaserClock;
|
||||||
class EtherDev;
|
class EtherDev;
|
||||||
class TsunamiCChip;
|
class TsunamiCChip;
|
||||||
|
@ -64,8 +64,8 @@ class Tsunami : public Platform
|
||||||
System *system;
|
System *system;
|
||||||
/** Pointer to the TsunamiIO device which has the RTC */
|
/** Pointer to the TsunamiIO device which has the RTC */
|
||||||
TsunamiIO *io;
|
TsunamiIO *io;
|
||||||
/** Pointer to the SCSI controller device */
|
/** Pointer to the disk controller device */
|
||||||
AdaptecController *scsi;
|
IdeController *disk_controller;
|
||||||
/** Pointer to the ethernet controller device */
|
/** Pointer to the ethernet controller device */
|
||||||
EtherDev *ethernet;
|
EtherDev *ethernet;
|
||||||
|
|
||||||
|
|
|
@ -224,6 +224,9 @@ LinuxSystem::LinuxSystem(const string _name, const uint64_t _init_param,
|
||||||
"pmap_scavenge_boot");
|
"pmap_scavenge_boot");
|
||||||
printfEvent = new LinuxPrintfEvent(&pcEventQueue, "printf");
|
printfEvent = new LinuxPrintfEvent(&pcEventQueue, "printf");
|
||||||
|
|
||||||
|
skipIdeDelay50msEvent = new LinuxSkipIdeDelay50msEvent(&pcEventQueue,
|
||||||
|
"ide_delay_50ms");
|
||||||
|
|
||||||
skipDelayLoopEvent = new LinuxSkipDelayLoopEvent(&pcEventQueue,
|
skipDelayLoopEvent = new LinuxSkipDelayLoopEvent(&pcEventQueue,
|
||||||
"calibrate_delay");
|
"calibrate_delay");
|
||||||
|
|
||||||
|
@ -333,6 +336,9 @@ LinuxSystem::LinuxSystem(const string _name, const uint64_t _init_param,
|
||||||
if (kernelSymtab->findAddress("pmap_scavenge_boot", addr))
|
if (kernelSymtab->findAddress("pmap_scavenge_boot", addr))
|
||||||
skipScavengeBootEvent->schedule(addr);
|
skipScavengeBootEvent->schedule(addr);
|
||||||
|
|
||||||
|
if (kernelSymtab->findAddress("ide_delay_50ms", addr))
|
||||||
|
skipIdeDelay50msEvent->schedule(addr+8);
|
||||||
|
|
||||||
if (kernelSymtab->findAddress("calibrate_delay", addr))
|
if (kernelSymtab->findAddress("calibrate_delay", addr))
|
||||||
skipDelayLoopEvent->schedule(addr+8);
|
skipDelayLoopEvent->schedule(addr+8);
|
||||||
|
|
||||||
|
|
|
@ -44,6 +44,7 @@ class BreakPCEvent;
|
||||||
class LinuxBadAddrEvent;
|
class LinuxBadAddrEvent;
|
||||||
class LinuxSkipFuncEvent;
|
class LinuxSkipFuncEvent;
|
||||||
class LinuxSkipDelayLoopEvent;
|
class LinuxSkipDelayLoopEvent;
|
||||||
|
class LinuxSkipIdeDelay50msEvent;
|
||||||
class LinuxPrintfEvent;
|
class LinuxPrintfEvent;
|
||||||
class LinuxDebugPrintfEvent;
|
class LinuxDebugPrintfEvent;
|
||||||
class LinuxDumpMbufEvent;
|
class LinuxDumpMbufEvent;
|
||||||
|
@ -101,6 +102,7 @@ class LinuxSystem : public System
|
||||||
LinuxBadAddrEvent *badaddrEvent;
|
LinuxBadAddrEvent *badaddrEvent;
|
||||||
LinuxSkipFuncEvent *skipPowerStateEvent;
|
LinuxSkipFuncEvent *skipPowerStateEvent;
|
||||||
LinuxSkipFuncEvent *skipScavengeBootEvent;
|
LinuxSkipFuncEvent *skipScavengeBootEvent;
|
||||||
|
LinuxSkipIdeDelay50msEvent *skipIdeDelay50msEvent;
|
||||||
LinuxSkipDelayLoopEvent *skipDelayLoopEvent;
|
LinuxSkipDelayLoopEvent *skipDelayLoopEvent;
|
||||||
LinuxPrintfEvent *printfEvent;
|
LinuxPrintfEvent *printfEvent;
|
||||||
LinuxDebugPrintfEvent *debugPrintfEvent;
|
LinuxDebugPrintfEvent *debugPrintfEvent;
|
||||||
|
|
Loading…
Reference in a new issue