257 lines
8.4 KiB
C++
257 lines
8.4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Simple PCI IDE controller with bus mastering capability
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*/
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#ifndef __IDE_CTRL_HH__
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#define __IDE_CTRL_HH__
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#include "dev/pcidev.hh"
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#include "dev/pcireg.h"
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#include "dev/io_device.hh"
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#define CMD0 0x00 // Channel 0 command block offset
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#define CTRL0 0x08 // Channel 0 control block offset
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#define CMD1 0x0c // Channel 1 command block offset
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#define CTRL1 0x14 // Channel 1 control block offset
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#define BMI 0x18 // Bus master IDE offset
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#define BMIC0 0x0 // Bus master IDE command register
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#define BMIS0 0x2 // Bus master IDE status register
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#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
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#define BMIC1 0x8 // Bus master IDE command register
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#define BMIS1 0xa // Bus master IDE status register
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#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
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// Bus master IDE command register bit fields
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#define RWCON 0x08 // Bus master read/write control
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#define SSBM 0x01 // Start/stop bus master
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// Bus master IDE status register bit fields
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#define DMA1CAP 0x40 // Drive 1 DMA capable
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#define DMA0CAP 0x20 // Drive 0 DMA capable
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#define IDEINTS 0x04 // IDE Interrupt Status
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#define IDEDMAE 0x02 // IDE DMA error
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#define BMIDEA 0x01 // Bus master IDE active
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// IDE Command byte fields
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// Taken from include/linux/ide.h
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#define IDE_DATA_OFFSET (0)
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#define IDE_ERROR_OFFSET (1)
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#define IDE_NSECTOR_OFFSET (2)
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#define IDE_SECTOR_OFFSET (3)
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#define IDE_LCYL_OFFSET (4)
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#define IDE_HCYL_OFFSET (5)
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#define IDE_SELECT_OFFSET (6)
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#define IDE_STATUS_OFFSET (7)
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#define IDE_CONTROL_OFFSET (8)
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#define IDE_IRQ_OFFSET (9)
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#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
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#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
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// PCI device specific register byte offsets
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#define PCI_IDE_TIMING 0x40
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#define PCI_SLAVE_TIMING 0x44
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#define PCI_UDMA33_CTRL 0x48
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#define PCI_UDMA33_TIMING 0x4a
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#define IDETIM (0)
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#define SIDETIM (4)
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#define UDMACTL (5)
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#define UDMATIM (6)
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// PCI Command bit fields
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#define BME 0x04 // Bus master function enable
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#define IOSE 0x01 // I/O space enable
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class IntrControl;
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class IdeDisk;
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class PciConfigAll;
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class Tsunami;
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class PhysicalMemory;
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class BaseInterface;
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class HierParams;
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class Bus;
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/**
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* Device model for an Intel PIIX4 IDE controller
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*/
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class IdeController : public PciDev
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{
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private:
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/** Primary command block registers */
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Addr pri_cmd_addr;
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Addr pri_cmd_size;
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/** Primary control block registers */
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Addr pri_ctrl_addr;
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Addr pri_ctrl_size;
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/** Secondary command block registers */
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Addr sec_cmd_addr;
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Addr sec_cmd_size;
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/** Secondary control block registers */
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Addr sec_ctrl_addr;
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Addr sec_ctrl_size;
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/** Bus master interface (BMI) registers */
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Addr bmi_addr;
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Addr bmi_size;
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private:
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/** Registers used for programmed I/O and bus master interface */
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uint8_t regs[40];
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/** Registers used in PCI configuration */
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uint8_t pci_regs[8];
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// Internal management variables
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bool io_enabled;
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bool bm_enabled;
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bool cmd_in_progress[4];
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private:
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/** Pointer to the chipset */
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Tsunami *tsunami;
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/** IDE disks connected to controller */
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IdeDisk *disks[4];
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private:
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/** Get offset into register file from access address */
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Addr getOffset(const Addr &addr) {
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Addr offset = addr;
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if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
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offset -= pri_cmd_addr;
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offset += CMD0;
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} else if (addr >= pri_ctrl_addr &&
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addr < (pri_ctrl_addr + pri_ctrl_size)) {
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offset -= pri_ctrl_addr;
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offset += CTRL0;
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} else if (addr >= sec_cmd_addr &&
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addr < (sec_cmd_addr + sec_cmd_size)) {
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offset -= sec_cmd_addr;
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offset += CMD1;
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} else if (addr >= sec_ctrl_addr &&
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addr < (sec_ctrl_addr + sec_ctrl_size)) {
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offset -= sec_ctrl_addr;
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offset += CTRL1;
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} else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
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offset -= bmi_addr;
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offset += BMI;
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} else {
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panic("IDE controller access to invalid address: %#x\n", addr);
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}
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return offset;
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};
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/** Select the disk based on the register offset */
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int getDisk(const Addr &offset) {
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int disk = 0;
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// If the offset is in the channel 1 range, disks are 2 or 3
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if (offset >= CMD1 && offset < BMI && offset >= (BMI + BMIC1))
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disk += 2;
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if (disk < 2) {
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if (regs[CMD0 + IDE_STATUS_OFFSET] & 0x10)
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disk += 1;
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} else {
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if (regs[CMD1 + IDE_STATUS_OFFSET] & 0x10)
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disk += 1;
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}
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return disk;
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};
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public:
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/**
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* Constructs and initializes this controller.
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* @param name The name of this controller.
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* @param ic The interrupt controller.
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* @param mmu The memory controller
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* @param cf PCI config space
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* @param cd PCI config data
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* @param bus_num The PCI bus number
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* @param dev_num The PCI device number
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* @param func_num The PCI function number
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* @param host_bus The host bus to connect to
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* @param hier The hierarchy parameters
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*/
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IdeController(const std::string &name, IntrControl *ic,
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const vector<IdeDisk *> &new_disks,
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MemoryController *mmu, PciConfigAll *cf,
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PciConfigData *cd, Tsunami *t,
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uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
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Bus *host_bus, HierParams *hier);
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/**
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* Deletes the connected devices.
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*/
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~IdeController();
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virtual void WriteConfig(int offset, int size, uint32_t data);
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virtual void ReadConfig(int offset, int size, uint8_t *data);
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/**
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* Read a done field for a given target.
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* @param req Contains the address of the field to read.
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* @param data Return the field read.
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* @return The fault condition of the access.
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*/
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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/**
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* Write to the mmapped I/O control registers.
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* @param req Contains the address to write to.
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* @param data The data to write.
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* @return The fault condition of the access.
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Cache access timing specific to device
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* @param req Memory request
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*/
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Tick cacheAccess(MemReqPtr &req);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __IDE_CTRL_HH_
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