factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.
configs/common/Simulation.py: enable going from checkpoint into arbitrary CPU with or without caches. --HG-- extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
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3 changed files with 57 additions and 32 deletions
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@ -32,7 +32,31 @@ from m5.objects import *
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m5.AddToPath('../common')
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from Caches import L1Cache
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def run(options, root, testsys):
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def setCPUClass(options):
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atomic = False
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if options.timing:
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TmpClass = TimingSimpleCPU
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elif options.detailed:
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TmpClass = DerivO3CPU
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else:
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TmpClass = AtomicSimpleCPU
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atomic = True
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CPUClass = None
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test_mem_mode = 'atomic'
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if not atomic:
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if options.checkpoint_restore:
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CPUClass = TmpClass
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TmpClass = AtomicSimpleCPU
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else:
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test_mem_mode = 'timing'
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return (TmpClass, test_mem_mode, CPUClass)
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def run(options, root, testsys, cpu_class):
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if options.maxtick:
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maxtick = options.maxtick
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elif options.maxtime:
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@ -49,6 +73,24 @@ def run(options, root, testsys):
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np = options.num_cpus
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max_checkpoints = options.max_checkpoints
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switch_cpus = None
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if cpu_class:
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switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
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for i in xrange(np)]
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for i in xrange(np):
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switch_cpus[i].system = testsys
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if not m5.build_env['FULL_SYSTEM']:
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switch_cpus[i].workload = testsys.cpu[i].workload
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switch_cpus[i].clock = testsys.cpu[0].clock
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if options.caches:
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switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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switch_cpus[i].connectMemPorts(testsys.membus)
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root.switch_cpus = switch_cpus
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switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
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if options.standard_switch:
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switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
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@ -65,17 +107,16 @@ def run(options, root, testsys):
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switch_cpus[i].clock = testsys.cpu[0].clock
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switch_cpus_1[i].clock = testsys.cpu[0].clock
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## add caches to the warmup timing CPU (which will be
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## xferred to O3 when you switch again)
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if options.caches:
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switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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else: # O3 CPU must have a cache to work.
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switch_cpus[i].connectMemPorts(testsys.membus)
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else:
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# O3 CPU must have a cache to work.
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switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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switch_cpus_1[i].connectMemPorts(testsys.membus)
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switch_cpus[i].connectMemPorts(testsys.membus)
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root.switch_cpus = switch_cpus
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root.switch_cpus_1 = switch_cpus_1
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@ -110,7 +151,7 @@ def run(options, root, testsys):
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m5.restoreCheckpoint(root,
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"/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
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if options.standard_switch:
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if options.standard_switch or cpu_class:
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exit_event = m5.simulate(10000)
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## when you change to Timing (or Atomic), you halt the system given
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@ -123,6 +164,7 @@ def run(options, root, testsys):
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m5.switchCpus(switch_cpu_list)
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m5.resume(testsys)
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if options.standard_switch:
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exit_event = m5.simulate(options.warmup)
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m5.switchCpus(switch_cpu_list1)
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@ -72,16 +72,8 @@ if args:
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DriveCPUClass = AtomicSimpleCPU
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drive_mem_mode = 'atomic'
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# system under test can be any of these CPUs
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if options.detailed:
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TestCPUClass = DerivO3CPU
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test_mem_mode = 'timing'
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elif options.timing:
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TestCPUClass = TimingSimpleCPU
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test_mem_mode = 'timing'
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else:
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TestCPUClass = AtomicSimpleCPU
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test_mem_mode = 'atomic'
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# system under test can be any CPU
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(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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TestCPUClass.clock = '2GHz'
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DriveCPUClass.clock = '2GHz'
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@ -103,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
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np = options.num_cpus
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test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
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for i in xrange(np):
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if options.caches and not options.standard_switch:
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if options.caches and not options.standard_switch and not FutureClass:
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test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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test_sys.cpu[i].connectMemPorts(test_sys.membus)
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@ -119,4 +111,4 @@ else:
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print "Error I don't know how to create more than 2 systems."
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sys.exit(1)
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Simulation.run(options, root, test_sys)
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Simulation.run(options, root, test_sys, FutureClass)
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@ -88,16 +88,7 @@ if options.detailed:
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process += [smt_process, ]
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smt_idx += 1
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if options.timing:
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CPUClass = TimingSimpleCPU
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test_mem_mode = 'timing'
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elif options.detailed:
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CPUClass = DerivO3CPU
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test_mem_mode = 'timing'
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else:
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CPUClass = AtomicSimpleCPU
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test_mem_mode = 'atomic'
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(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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CPUClass.clock = '2GHz'
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@ -110,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
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system.physmem.port = system.membus.port
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for i in xrange(np):
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if options.caches and not options.standard_switch:
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if options.caches and not options.standard_switch and not FutureClass:
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system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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system.cpu[i].connectMemPorts(system.membus)
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@ -118,4 +109,4 @@ for i in xrange(np):
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root = Root(system = system)
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Simulation.run(options, root, system)
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Simulation.run(options, root, system, FutureClass)
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