ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines so that it can be used to determine the correct enqueue latency for response messages.
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3 changed files with 6 additions and 0 deletions
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@ -149,6 +149,8 @@ structure (CacheMemory, external = "yes") {
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void deallocate(Address);
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void deallocate(Address);
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AbstractCacheEntry lookup(Address);
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AbstractCacheEntry lookup(Address);
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bool isTagPresent(Address);
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bool isTagPresent(Address);
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Cycles getTagLatency();
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Cycles getDataLatency();
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void setMRU(Address);
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void setMRU(Address);
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void recordRequestType(CacheRequestType);
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void recordRequestType(CacheRequestType);
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bool checkResourceAvailable(CacheResourceType, Address);
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bool checkResourceAvailable(CacheResourceType, Address);
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@ -70,6 +70,7 @@ class BankedArray
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// This is so we don't get aliasing on blocks being replaced
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// This is so we don't get aliasing on blocks being replaced
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bool tryAccess(int64 idx);
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bool tryAccess(int64 idx);
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Cycles getLatency() const { return accessLatency; }
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};
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};
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#endif
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#endif
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@ -91,6 +91,9 @@ class CacheMemory : public SimObject
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const AbstractCacheEntry* lookup(const Address& address) const;
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const AbstractCacheEntry* lookup(const Address& address) const;
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Cycles getLatency() const { return m_latency; }
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Cycles getLatency() const { return m_latency; }
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Cycles getTagLatency() const { return tagArray.getLatency(); }
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Cycles getDataLatency() const { return dataArray.getLatency(); }
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// Hook for checkpointing the contents of the cache
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// Hook for checkpointing the contents of the cache
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void recordCacheContents(int cntrl, CacheRecorder* tr) const;
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void recordCacheContents(int cntrl, CacheRecorder* tr) const;
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