Mips Code Cleanup:
Fix some author stuff and copyright dates Take out full system code src/arch/mips/isa/base.isa: src/arch/mips/isa/bitfields.isa: copyright info src/arch/mips/isa/decoder.isa: src/arch/mips/isa/formats/basic.isa: src/arch/mips/isa/formats/branch.isa: src/arch/mips/isa/formats/control.isa: src/arch/mips/isa/formats/fp.isa: src/arch/mips/isa/formats/int.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/noop.isa: src/arch/mips/isa/formats/tlbop.isa: src/arch/mips/isa/formats/trap.isa: src/arch/mips/isa/formats/unimp.isa: src/arch/mips/isa/formats/unknown.isa: src/arch/mips/isa/formats/util.isa: src/arch/mips/isa/includes.isa: src/arch/mips/isa/main.isa: src/arch/mips/isa/operands.isa: src/arch/mips/process.cc: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/stacktrace.hh: copyright 2006 src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: copyright 2006 take out full system src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/regfile.hh: copyright 2006 use FloatRegVal src/arch/mips/regfile/int_regfile.hh: copyright 2006 move HI/LO to types.hh src/arch/mips/types.hh: copyright 2006 typedef FloatRegVal --HG-- extra : convert_revision : 1d0d72cd655a4e28622745a6c6b06349da533a1d
This commit is contained in:
parent
1c55389578
commit
74b9868c78
27 changed files with 69 additions and 163 deletions
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -38,7 +38,6 @@ output header {{
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using namespace MipsISA;
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using namespace MipsISA;
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/**
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/**
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* Base class for all MIPS static instructions.
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* Base class for all MIPS static instructions.
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*/
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*/
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,5 +1,33 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Korey Sewell
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Nop
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// Nop
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,7 +1,7 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// -*- mode:c++ -*-
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// -*- mode:c++ -*-
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// Copyright (c) 2003-2006 The Regents of The University of Michigan
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
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'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
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#Special Integer Reg operands
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#Special Integer Reg operands
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'HI': ('IntReg', 'uw','32', 'IsInteger', 6),
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'HI': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6),
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'LO': ('IntReg', 'uw','33', 'IsInteger', 7),
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'LO': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7),
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#Immediate Value operand
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#Immediate Value operand
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
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'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
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#Special Floating Point Control Reg Operands
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#Special Floating Point Control Reg Operands
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'FIR': ('FloatReg', 'uw', '32', 'IsFloating', 1),
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'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
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'FCCR': ('FloatReg', 'uw', '33', 'IsFloating', 2),
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'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
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'FEXR': ('FloatReg', 'uw', '34', 'IsFloating', 3),
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'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
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'FENR': ('FloatReg', 'uw', '35', 'IsFloating', 3),
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'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
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'FCSR': ('FloatReg', 'uw', '36', 'IsFloating', 3),
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'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
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#Operands For Paired Singles FP Operations
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#Operands For Paired Singles FP Operations
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'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
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'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
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*/
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*/
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/isa_traits.hh"
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#include "config/full_system.hh"
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//#include "config/full_system.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/static_inst.hh"
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#include "sim/serialize.hh"
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#include "sim/serialize.hh"
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#include "base/bitfield.hh"
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#include "base/bitfield.hh"
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MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
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MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
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{
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{
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panic("Copy Regs Not Implemented Yet\n");
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panic("Copy Regs Not Implemented Yet\n");
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/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
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uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
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lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
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lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
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#if FULL_SYSTEM
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copyIprs(xc);
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#endif*/
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}
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}
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void
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void
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MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
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MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
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{
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{
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panic("Copy Misc. Regs Not Implemented Yet\n");
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panic("Copy Misc. Regs Not Implemented Yet\n");
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/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
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uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
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lock_flag = xc->readMiscReg(MipsISA::Lock_Flag_DepTag);
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lock_addr = xc->readMiscReg(MipsISA::Lock_Addr_DepTag);
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#endif*/
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}
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}
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#if FULL_SYSTEM
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static inline Addr
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TruncPage(Addr addr)
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{ return addr & ~(MipsISA::PageBytes - 1); }
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static inline Addr
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RoundPage(Addr addr)
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{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
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#endif
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void
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void
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IntRegFile::serialize(std::ostream &os)
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IntRegFile::serialize(std::ostream &os)
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{
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{
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(npc);
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SERIALIZE_SCALAR(nnpc);
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SERIALIZE_SCALAR(nnpc);
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#if FULL_SYSTEM
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SERIALIZE_ARRAY(palregs, NumIntRegs);
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SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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SERIALIZE_SCALAR(intrflag);
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SERIALIZE_SCALAR(pal_shadow);
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#endif
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}
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}
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(npc);
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UNSERIALIZE_SCALAR(nnpc);
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UNSERIALIZE_SCALAR(nnpc);
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#if FULL_SYSTEM
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UNSERIALIZE_ARRAY(palregs, NumIntRegs);
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UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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UNSERIALIZE_SCALAR(intrflag);
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UNSERIALIZE_SCALAR(pal_shadow);
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#endif
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}
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}
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#if FULL_SYSTEM
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void
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PTE::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(tag);
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SERIALIZE_SCALAR(ppn);
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SERIALIZE_SCALAR(xre);
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SERIALIZE_SCALAR(xwe);
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SERIALIZE_SCALAR(asn);
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SERIALIZE_SCALAR(asma);
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SERIALIZE_SCALAR(fonr);
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SERIALIZE_SCALAR(fonw);
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SERIALIZE_SCALAR(valid);
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}
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void
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PTE::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(tag);
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UNSERIALIZE_SCALAR(ppn);
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UNSERIALIZE_SCALAR(xre);
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UNSERIALIZE_SCALAR(xwe);
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UNSERIALIZE_SCALAR(asn);
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UNSERIALIZE_SCALAR(asma);
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||||||
UNSERIALIZE_SCALAR(fonr);
|
|
||||||
UNSERIALIZE_SCALAR(fonw);
|
|
||||||
UNSERIALIZE_SCALAR(valid);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif //FULL_SYSTEM
|
|
||||||
|
|
|
@ -57,12 +57,6 @@ namespace LittleEndianGuest {};
|
||||||
class StaticInst;
|
class StaticInst;
|
||||||
class StaticInstPtr;
|
class StaticInstPtr;
|
||||||
|
|
||||||
namespace MIPS34K {
|
|
||||||
int DTB_ASN_ASN(uint64_t reg);
|
|
||||||
int ITB_ASN_ASN(uint64_t reg);
|
|
||||||
};
|
|
||||||
|
|
||||||
#if !FULL_SYSTEM
|
|
||||||
class SyscallReturn {
|
class SyscallReturn {
|
||||||
public:
|
public:
|
||||||
template <class T>
|
template <class T>
|
||||||
|
@ -95,7 +89,6 @@ class SyscallReturn {
|
||||||
uint64_t retval;
|
uint64_t retval;
|
||||||
bool success;
|
bool success;
|
||||||
};
|
};
|
||||||
#endif
|
|
||||||
|
|
||||||
namespace MipsISA
|
namespace MipsISA
|
||||||
{
|
{
|
||||||
|
@ -140,12 +133,6 @@ namespace MipsISA
|
||||||
|
|
||||||
void copyRegs(ThreadContext *src, ThreadContext *dest);
|
void copyRegs(ThreadContext *src, ThreadContext *dest);
|
||||||
|
|
||||||
uint64_t fpConvert(double fp_val, ConvertType cvt_type);
|
|
||||||
double roundFP(double val, int digits);
|
|
||||||
double truncFP(double val);
|
|
||||||
bool getFPConditionCode(uint32_t fcsr_reg, int cc);
|
|
||||||
uint32_t makeCCVector(uint32_t fcsr, int num, bool val);
|
|
||||||
|
|
||||||
// Machine operations
|
// Machine operations
|
||||||
|
|
||||||
void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
|
void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
|
||||||
|
@ -191,12 +178,6 @@ namespace MipsISA
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
|
|
||||||
#include "arch/mips/mips34k.hh"
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
using namespace MipsISA;
|
using namespace MipsISA;
|
||||||
|
|
||||||
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
|
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
|
||||||
|
|
|
@ -1,3 +1,4 @@
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2003-2004 The Regents of The University of Michigan
|
* Copyright (c) 2003-2004 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -100,7 +100,7 @@ namespace MipsISA
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault setReg(int floatReg, const FloatReg &val, int width)
|
Fault setReg(int floatReg, const FloatRegVal &val, int width)
|
||||||
{
|
{
|
||||||
using namespace std;
|
using namespace std;
|
||||||
switch(width)
|
switch(width)
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -65,11 +65,6 @@ namespace MipsISA
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
enum MiscIntRegNums {
|
|
||||||
HI = NumIntArchRegs,
|
|
||||||
LO
|
|
||||||
};
|
|
||||||
|
|
||||||
} // namespace MipsISA
|
} // namespace MipsISA
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -45,18 +45,12 @@ namespace MipsISA
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
uint64_t fpcr; // floating point condition codes
|
uint64_t fpcr; // floating point condition codes
|
||||||
uint64_t uniq; // process-unique register
|
|
||||||
bool lock_flag; // lock flag for LL/SC
|
bool lock_flag; // lock flag for LL/SC
|
||||||
Addr lock_addr; // lock address for LL/SC
|
Addr lock_addr; // lock address for LL/SC
|
||||||
|
|
||||||
MiscReg miscRegFile[NumMiscRegs];
|
MiscReg miscRegFile[NumMiscRegs];
|
||||||
|
|
||||||
public:
|
public:
|
||||||
//These functions should be removed once the simplescalar cpu model
|
|
||||||
//has been replaced.
|
|
||||||
int getInstAsid();
|
|
||||||
int getDataAsid();
|
|
||||||
|
|
||||||
void copyMiscRegs(ThreadContext *tc);
|
void copyMiscRegs(ThreadContext *tc);
|
||||||
|
|
||||||
MiscReg readReg(int misc_reg)
|
MiscReg readReg(int misc_reg)
|
||||||
|
@ -80,17 +74,6 @@ namespace MipsISA
|
||||||
miscRegFile[misc_reg] = val; return NoFault;
|
miscRegFile[misc_reg] = val; return NoFault;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void clearIprs() { }
|
|
||||||
|
|
||||||
protected:
|
|
||||||
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
|
|
||||||
|
|
||||||
private:
|
|
||||||
MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { }
|
|
||||||
|
|
||||||
Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { }
|
|
||||||
#endif
|
|
||||||
friend class RegFile;
|
friend class RegFile;
|
||||||
};
|
};
|
||||||
} // namespace MipsISA
|
} // namespace MipsISA
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -81,12 +81,12 @@ namespace MipsISA
|
||||||
return miscRegFile.setRegWithEffect(miscReg, val, tc);
|
return miscRegFile.setRegWithEffect(miscReg, val, tc);
|
||||||
}
|
}
|
||||||
|
|
||||||
FloatReg readFloatReg(int floatReg)
|
FloatRegVal readFloatReg(int floatReg)
|
||||||
{
|
{
|
||||||
return floatRegFile.readReg(floatReg,SingleWidth);
|
return floatRegFile.readReg(floatReg,SingleWidth);
|
||||||
}
|
}
|
||||||
|
|
||||||
FloatReg readFloatReg(int floatReg, int width)
|
FloatRegVal readFloatReg(int floatReg, int width)
|
||||||
{
|
{
|
||||||
return floatRegFile.readReg(floatReg,width);
|
return floatRegFile.readReg(floatReg,width);
|
||||||
}
|
}
|
||||||
|
@ -101,12 +101,12 @@ namespace MipsISA
|
||||||
return floatRegFile.readRegBits(floatReg,width);
|
return floatRegFile.readRegBits(floatReg,width);
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault setFloatReg(int floatReg, const FloatReg &val)
|
Fault setFloatReg(int floatReg, const FloatRegVal &val)
|
||||||
{
|
{
|
||||||
return floatRegFile.setReg(floatReg, val, SingleWidth);
|
return floatRegFile.setReg(floatReg, val, SingleWidth);
|
||||||
}
|
}
|
||||||
|
|
||||||
Fault setFloatReg(int floatReg, const FloatReg &val, int width)
|
Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
|
||||||
{
|
{
|
||||||
return floatRegFile.setReg(floatReg, val, width);
|
return floatRegFile.setReg(floatReg, val, width);
|
||||||
}
|
}
|
||||||
|
@ -168,16 +168,6 @@ namespace MipsISA
|
||||||
nnpc = val;
|
nnpc = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
IntReg palregs[NumIntRegs]; // PAL shadow registers
|
|
||||||
InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
|
|
||||||
int intrflag; // interrupt flag
|
|
||||||
bool pal_shadow; // using pal_shadow registers
|
|
||||||
inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
|
|
||||||
inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
|
|
||||||
#endif // FULL_SYSTEM
|
|
||||||
|
|
||||||
void serialize(std::ostream &os);
|
void serialize(std::ostream &os);
|
||||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||||
|
|
||||||
|
@ -193,9 +183,6 @@ namespace MipsISA
|
||||||
|
|
||||||
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
|
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
void copyIprs(ThreadContext *src, ThreadContext *dest);
|
|
||||||
#endif
|
|
||||||
} // namespace MipsISA
|
} // namespace MipsISA
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -25,7 +25,7 @@
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
*
|
*
|
||||||
* Authors: Korey Sewell
|
* Authors: Ali Saidi
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __ARCH_MIPS_STACKTRACE_HH__
|
#ifndef __ARCH_MIPS_STACKTRACE_HH__
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||||
* All rights reserved.
|
* All rights reserved.
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
@ -42,14 +42,15 @@ namespace MipsISA
|
||||||
typedef uint32_t IntReg;
|
typedef uint32_t IntReg;
|
||||||
|
|
||||||
// floating point register file entry type
|
// floating point register file entry type
|
||||||
typedef double FloatReg;
|
|
||||||
typedef uint32_t FloatReg32;
|
typedef uint32_t FloatReg32;
|
||||||
typedef uint64_t FloatReg64;
|
typedef uint64_t FloatReg64;
|
||||||
typedef uint64_t FloatRegBits;
|
typedef uint64_t FloatRegBits;
|
||||||
|
|
||||||
|
typedef double FloatRegVal;
|
||||||
|
typedef double FloatReg;
|
||||||
|
|
||||||
// cop-0/cop-1 system control register
|
// cop-0/cop-1 system control register
|
||||||
typedef uint64_t MiscReg;
|
typedef uint64_t MiscReg;
|
||||||
typedef uint64_t InternalProcReg;
|
|
||||||
|
|
||||||
typedef union {
|
typedef union {
|
||||||
IntReg intreg;
|
IntReg intreg;
|
||||||
|
|
Loading…
Reference in a new issue