74b9868c78
Fix some author stuff and copyright dates Take out full system code src/arch/mips/isa/base.isa: src/arch/mips/isa/bitfields.isa: copyright info src/arch/mips/isa/decoder.isa: src/arch/mips/isa/formats/basic.isa: src/arch/mips/isa/formats/branch.isa: src/arch/mips/isa/formats/control.isa: src/arch/mips/isa/formats/fp.isa: src/arch/mips/isa/formats/int.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/noop.isa: src/arch/mips/isa/formats/tlbop.isa: src/arch/mips/isa/formats/trap.isa: src/arch/mips/isa/formats/unimp.isa: src/arch/mips/isa/formats/unknown.isa: src/arch/mips/isa/formats/util.isa: src/arch/mips/isa/includes.isa: src/arch/mips/isa/main.isa: src/arch/mips/isa/operands.isa: src/arch/mips/process.cc: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/stacktrace.hh: copyright 2006 src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: copyright 2006 take out full system src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/regfile.hh: copyright 2006 use FloatRegVal src/arch/mips/regfile/int_regfile.hh: copyright 2006 move HI/LO to types.hh src/arch/mips/types.hh: copyright 2006 typedef FloatRegVal --HG-- extra : convert_revision : 1d0d72cd655a4e28622745a6c6b06349da533a1d
183 lines
5.4 KiB
C++
183 lines
5.4 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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*/
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#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
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#define __ARCH_MIPS_ISA_TRAITS_HH__
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#include "arch/mips/constants.hh"
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#include "arch/mips/types.hh"
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#include "arch/mips/regfile/regfile.hh"
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#include "arch/mips/faults.hh"
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#include "arch/mips/utility.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/byteswap.hh"
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#include "sim/host.hh"
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#include "sim/faults.hh"
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#include <vector>
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class FastCPU;
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class FullCPU;
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class Checkpoint;
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class ThreadContext;
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namespace LittleEndianGuest {};
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#define TARGET_MIPS
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class StaticInst;
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class StaticInstPtr;
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class SyscallReturn {
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public:
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template <class T>
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SyscallReturn(T v, bool s)
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{
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retval = (uint32_t)v;
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success = s;
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}
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template <class T>
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SyscallReturn(T v)
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{
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success = (v >= 0);
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retval = (uint32_t)v;
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}
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~SyscallReturn() {}
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SyscallReturn& operator=(const SyscallReturn& s) {
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retval = s.retval;
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success = s.success;
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return *this;
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}
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bool successful() { return success; }
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uint64_t value() { return retval; }
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private:
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uint64_t retval;
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bool success;
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};
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namespace MipsISA
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{
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using namespace LittleEndianGuest;
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static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
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{
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if (return_value.successful()) {
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// no error
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regs->setIntReg(SyscallSuccessReg, 0);
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regs->setIntReg(ReturnValueReg1, return_value.value());
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} else {
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// got an error, return details
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regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
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regs->setIntReg(ReturnValueReg1, -return_value.value());
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}
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}
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StaticInstPtr decodeInst(ExtMachInst);
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static inline ExtMachInst
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makeExtMI(MachInst inst, const uint64_t &pc) {
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#if FULL_SYSTEM
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ExtMachInst ext_inst = inst;
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if (pc && 0x1)
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return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
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else
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return ext_inst;
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#else
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return ExtMachInst(inst);
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#endif
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param tc The thread context.
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*/
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template <class TC>
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void zeroRegisters(TC *tc);
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const Addr MaxAddr = (Addr)-1;
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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// Machine operations
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void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
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int regnum);
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void restoreMachineReg(RegFile ®s, const AnyReg ®,
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int regnum);
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#if 0
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static void serializeSpecialRegs(const Serializable::Proxy &proxy,
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const RegFile ®s);
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static void unserializeSpecialRegs(const IniFile *db,
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const std::string &category,
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ConfigNode *node,
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RegFile ®s);
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#endif
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static inline Addr alignAddress(const Addr &addr,
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unsigned int nbytes) {
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return (addr & ~(nbytes - 1));
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}
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// Instruction address compression hooks
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static inline Addr realPCToFetchPC(const Addr &addr) {
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return addr;
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}
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static inline Addr fetchPCToRealPC(const Addr &addr) {
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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static inline size_t fetchInstSize() {
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return sizeof(MachInst);
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}
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static inline MachInst makeRegisterCopy(int dest, int src) {
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panic("makeRegisterCopy not implemented");
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return 0;
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}
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};
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using namespace MipsISA;
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#endif // __ARCH_MIPS_ISA_TRAITS_HH__
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