Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : f97469b7d19c82deb3d068f80546d729757c25e3
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commit
743737c28b
8 changed files with 44 additions and 25 deletions
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@ -75,6 +75,8 @@ else:
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cpu = AtomicSimpleCPU()
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cpu.workload = process
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cpu.mem = magicbus
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cpu.icache_port=magicbus.port
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cpu.dcache_port=magicbus.port
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system = System(physmem = mem, cpu = cpu)
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mem.port = magicbus.port
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@ -63,7 +63,7 @@ BaseCPU::BaseCPU(Params *p)
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params(p), number_of_threads(p->numberOfThreads), system(p->system)
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#else
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BaseCPU::BaseCPU(Params *p)
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: SimObject(p->name), clock(p->clock), params(p),
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: MemObject(p->name), clock(p->clock), params(p),
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number_of_threads(p->numberOfThreads), system(p->system)
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#endif
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{
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@ -37,15 +37,16 @@
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_object.hh"
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#include "mem/mem_object.hh"
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#include "arch/isa_traits.hh"
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class BranchPred;
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class CheckerCPU;
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class ThreadContext;
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class System;
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class Port;
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class BaseCPU : public SimObject
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class BaseCPU : public MemObject
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{
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protected:
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// CPU's clock period in terms of the number of ticks of curTime.
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@ -55,18 +55,28 @@ AtomicSimpleCPU::TickEvent::description()
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return "AtomicSimpleCPU tick event";
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}
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Port *
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AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "dcache_port")
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return &dcachePort;
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else if (if_name == "icache_port")
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return &icachePort;
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else
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panic("No Such Port\n");
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}
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void
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AtomicSimpleCPU::init()
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{
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//Create Memory Ports (conect them up)
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Port *mem_dport = mem->getPort("");
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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// Port *mem_dport = mem->getPort("");
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// dcachePort.setPeer(mem_dport);
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// mem_dport->setPeer(&dcachePort);
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Port *mem_iport = mem->getPort("");
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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// Port *mem_iport = mem->getPort("");
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// icachePort.setPeer(mem_iport);
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// mem_iport->setPeer(&icachePort);
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BaseCPU::init();
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#if FULL_SYSTEM
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@ -122,6 +122,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
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public:
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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@ -37,19 +37,20 @@
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using namespace std;
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using namespace TheISA;
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Port *
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TimingSimpleCPU::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "dcache_port")
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return &dcachePort;
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else if (if_name == "icache_port")
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return &icachePort;
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else
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panic("No Such Port\n");
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}
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void
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TimingSimpleCPU::init()
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{
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//Create Memory Ports (conect them up)
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Port *mem_dport = mem->getPort("");
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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Port *mem_iport = mem->getPort("");
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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BaseCPU::init();
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#if FULL_SYSTEM
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for (int i = 0; i < threadContexts.size(); ++i) {
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@ -451,12 +452,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
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bool
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TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
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{
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if (cpu->_status == DcacheWaitResponse)
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cpu->completeDataAccess(pkt);
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else if (cpu->_status == IcacheWaitResponse)
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cpu->completeIfetch(pkt);
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else
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assert("OOPS" && 0);
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cpu->completeIfetch(pkt);
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return true;
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}
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@ -130,6 +130,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
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public:
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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8
src/mem/cache/base_cache.cc
vendored
8
src/mem/cache/base_cache.cc
vendored
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@ -144,7 +144,13 @@ BaseCache::getPort(const std::string &if_name, int idx)
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cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
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return cpuSidePort;
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}
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if (if_name == "functional")
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else if (if_name == "functional")
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{
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if(cpuSidePort == NULL)
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cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
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return cpuSidePort;
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}
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else if (if_name == "cpu_side")
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{
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if(cpuSidePort == NULL)
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cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
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