diff --git a/configs/test/test.py b/configs/test/test.py
index 625304a08..e7b0971ef 100644
--- a/configs/test/test.py
+++ b/configs/test/test.py
@@ -75,6 +75,8 @@ else:
     cpu = AtomicSimpleCPU()
 cpu.workload = process
 cpu.mem = magicbus
+cpu.icache_port=magicbus.port
+cpu.dcache_port=magicbus.port
 
 system = System(physmem = mem, cpu = cpu)
 mem.port = magicbus.port
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 0b9c80591..548f012df 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -63,7 +63,7 @@ BaseCPU::BaseCPU(Params *p)
       params(p), number_of_threads(p->numberOfThreads), system(p->system)
 #else
 BaseCPU::BaseCPU(Params *p)
-    : SimObject(p->name), clock(p->clock), params(p),
+    : MemObject(p->name), clock(p->clock), params(p),
       number_of_threads(p->numberOfThreads), system(p->system)
 #endif
 {
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 5256a411f..2be6e4e81 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -37,15 +37,16 @@
 #include "base/statistics.hh"
 #include "config/full_system.hh"
 #include "sim/eventq.hh"
-#include "sim/sim_object.hh"
+#include "mem/mem_object.hh"
 #include "arch/isa_traits.hh"
 
 class BranchPred;
 class CheckerCPU;
 class ThreadContext;
 class System;
+class Port;
 
-class BaseCPU : public SimObject
+class BaseCPU : public MemObject
 {
   protected:
     // CPU's clock period in terms of the number of ticks of curTime.
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b7202cbbb..12bfdeb9b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -55,18 +55,28 @@ AtomicSimpleCPU::TickEvent::description()
     return "AtomicSimpleCPU tick event";
 }
 
+Port *
+AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
+{
+    if (if_name == "dcache_port")
+        return &dcachePort;
+    else if (if_name == "icache_port")
+        return &icachePort;
+    else
+        panic("No Such Port\n");
+}
 
 void
 AtomicSimpleCPU::init()
 {
     //Create Memory Ports (conect them up)
-    Port *mem_dport = mem->getPort("");
-    dcachePort.setPeer(mem_dport);
-    mem_dport->setPeer(&dcachePort);
+//    Port *mem_dport = mem->getPort("");
+//    dcachePort.setPeer(mem_dport);
+//    mem_dport->setPeer(&dcachePort);
 
-    Port *mem_iport = mem->getPort("");
-    icachePort.setPeer(mem_iport);
-    mem_iport->setPeer(&icachePort);
+//    Port *mem_iport = mem->getPort("");
+//    icachePort.setPeer(mem_iport);
+//    mem_iport->setPeer(&icachePort);
 
     BaseCPU::init();
 #if FULL_SYSTEM
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 951a8da06..179b4a721 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -122,6 +122,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
   public:
 
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
+
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 036037ba9..12a47fb3e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -37,19 +37,20 @@
 using namespace std;
 using namespace TheISA;
 
+Port *
+TimingSimpleCPU::getPort(const std::string &if_name, int idx)
+{
+    if (if_name == "dcache_port")
+        return &dcachePort;
+    else if (if_name == "icache_port")
+        return &icachePort;
+    else
+        panic("No Such Port\n");
+}
 
 void
 TimingSimpleCPU::init()
 {
-    //Create Memory Ports (conect them up)
-    Port *mem_dport = mem->getPort("");
-    dcachePort.setPeer(mem_dport);
-    mem_dport->setPeer(&dcachePort);
-
-    Port *mem_iport = mem->getPort("");
-    icachePort.setPeer(mem_iport);
-    mem_iport->setPeer(&icachePort);
-
     BaseCPU::init();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
@@ -451,12 +452,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    if (cpu->_status == DcacheWaitResponse)
-        cpu->completeDataAccess(pkt);
-    else if (cpu->_status == IcacheWaitResponse)
-        cpu->completeIfetch(pkt);
-    else
-        assert("OOPS" && 0);
+    cpu->completeIfetch(pkt);
     return true;
 }
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index c360e553e..d5b5d6648 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -130,6 +130,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
   public:
 
+    virtual Port *getPort(const std::string &if_name, int idx = -1);
+
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 4fbda4074..b2caca765 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -144,7 +144,13 @@ BaseCache::getPort(const std::string &if_name, int idx)
             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
         return cpuSidePort;
     }
-    if (if_name == "functional")
+    else if (if_name == "functional")
+    {
+        if(cpuSidePort == NULL)
+            cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+        return cpuSidePort;
+    }
+    else if (if_name == "cpu_side")
     {
         if(cpuSidePort == NULL)
             cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);